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Subhransu S. Prusty3582f9a2015-07-03 16:04:03 +05301/*
2 * Skylake SST DSP Support
3 *
4 * Copyright (C) 2014-15, Intel Corporation.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as version 2, as
8 * published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
14 */
15
16#ifndef __SKL_SST_DSP_H__
17#define __SKL_SST_DSP_H__
18
Subhransu S. Prustya750ba52015-07-10 22:18:44 +053019#include <linux/interrupt.h>
Jeeja KPb26199e2017-03-24 23:10:31 +053020#include <linux/uuid.h>
Subhransu S. Prustyebe89072017-04-25 12:18:20 +053021#include <linux/firmware.h>
Subhransu S. Prustyb6626802015-07-10 22:18:39 +053022#include <sound/memalloc.h>
Vinod Koul3e40a782015-07-10 22:18:42 +053023#include "skl-sst-cldma.h"
Subhransu S. Prustyb6626802015-07-10 22:18:39 +053024
Vinod Koul3e40a782015-07-10 22:18:42 +053025struct sst_dsp;
Subhransu S. Prustya750ba52015-07-10 22:18:44 +053026struct skl_sst;
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +053027struct sst_dsp_device;
Jeeja KPb26199e2017-03-24 23:10:31 +053028struct skl_lib_info;
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +053029
Subhransu S. Prusty3582f9a2015-07-03 16:04:03 +053030/* Intel HD Audio General DSP Registers */
31#define SKL_ADSP_GEN_BASE 0x0
32#define SKL_ADSP_REG_ADSPCS (SKL_ADSP_GEN_BASE + 0x04)
33#define SKL_ADSP_REG_ADSPIC (SKL_ADSP_GEN_BASE + 0x08)
34#define SKL_ADSP_REG_ADSPIS (SKL_ADSP_GEN_BASE + 0x0C)
35#define SKL_ADSP_REG_ADSPIC2 (SKL_ADSP_GEN_BASE + 0x10)
36#define SKL_ADSP_REG_ADSPIS2 (SKL_ADSP_GEN_BASE + 0x14)
37
38/* Intel HD Audio Inter-Processor Communication Registers */
39#define SKL_ADSP_IPC_BASE 0x40
40#define SKL_ADSP_REG_HIPCT (SKL_ADSP_IPC_BASE + 0x00)
41#define SKL_ADSP_REG_HIPCTE (SKL_ADSP_IPC_BASE + 0x04)
42#define SKL_ADSP_REG_HIPCI (SKL_ADSP_IPC_BASE + 0x08)
43#define SKL_ADSP_REG_HIPCIE (SKL_ADSP_IPC_BASE + 0x0C)
44#define SKL_ADSP_REG_HIPCCTL (SKL_ADSP_IPC_BASE + 0x10)
45
46/* HIPCI */
47#define SKL_ADSP_REG_HIPCI_BUSY BIT(31)
48
49/* HIPCIE */
50#define SKL_ADSP_REG_HIPCIE_DONE BIT(30)
51
52/* HIPCCTL */
53#define SKL_ADSP_REG_HIPCCTL_DONE BIT(1)
54#define SKL_ADSP_REG_HIPCCTL_BUSY BIT(0)
55
56/* HIPCT */
57#define SKL_ADSP_REG_HIPCT_BUSY BIT(31)
58
Vinod Koul39fa37d2016-03-11 10:12:49 +053059/* FW base IDs */
60#define SKL_INSTANCE_ID 0
61#define SKL_BASE_FW_MODULE_ID 0
62
Subhransu S. Prusty3582f9a2015-07-03 16:04:03 +053063/* Intel HD Audio SRAM Window 1 */
64#define SKL_ADSP_SRAM1_BASE 0xA000
65
66#define SKL_ADSP_MMIO_LEN 0x10000
67
Omair M Abdullahc99b8052015-12-03 23:29:54 +053068#define SKL_ADSP_W0_STAT_SZ 0x1000
Subhransu S. Prusty3582f9a2015-07-03 16:04:03 +053069
Omair M Abdullahc99b8052015-12-03 23:29:54 +053070#define SKL_ADSP_W0_UP_SZ 0x1000
Subhransu S. Prusty3582f9a2015-07-03 16:04:03 +053071
72#define SKL_ADSP_W1_SZ 0x1000
73
Subhransu S. Prustya750ba52015-07-10 22:18:44 +053074#define SKL_FW_STS_MASK 0xf
75
76#define SKL_FW_INIT 0x1
77#define SKL_FW_RFW_START 0xf
78
Subhransu S. Prusty3582f9a2015-07-03 16:04:03 +053079#define SKL_ADSPIC_IPC 1
80#define SKL_ADSPIS_IPC 1
81
Jayachandran B052f1032016-06-21 10:17:41 +053082/* Core ID of core0 */
83#define SKL_DSP_CORE0_ID 0
84
85/* Mask for a given core index, c = 0.. number of supported cores - 1 */
86#define SKL_DSP_CORE_MASK(c) BIT(c)
87
88/*
89 * Core 0 mask = SKL_DSP_CORE_MASK(0); Defined separately
90 * since Core0 is primary core and it is used often
91 */
92#define SKL_DSP_CORE0_MASK BIT(0)
93
94/*
95 * Mask for a given number of cores
96 * nc = number of supported cores
97 */
98#define SKL_DSP_CORES_MASK(nc) GENMASK((nc - 1), 0)
99
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +0530100/* ADSPCS - Audio DSP Control & Status */
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +0530101
Jayachandran B052f1032016-06-21 10:17:41 +0530102/*
103 * Core Reset - asserted high
104 * CRST Mask for a given core mask pattern, cm
105 */
106#define SKL_ADSPCS_CRST_SHIFT 0
107#define SKL_ADSPCS_CRST_MASK(cm) ((cm) << SKL_ADSPCS_CRST_SHIFT)
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +0530108
Jayachandran B052f1032016-06-21 10:17:41 +0530109/*
110 * Core run/stall - when set to '1' core is stalled
111 * CSTALL Mask for a given core mask pattern, cm
112 */
113#define SKL_ADSPCS_CSTALL_SHIFT 8
114#define SKL_ADSPCS_CSTALL_MASK(cm) ((cm) << SKL_ADSPCS_CSTALL_SHIFT)
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +0530115
Jayachandran B052f1032016-06-21 10:17:41 +0530116/*
117 * Set Power Active - when set to '1' turn cores on
118 * SPA Mask for a given core mask pattern, cm
119 */
120#define SKL_ADSPCS_SPA_SHIFT 16
121#define SKL_ADSPCS_SPA_MASK(cm) ((cm) << SKL_ADSPCS_SPA_SHIFT)
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +0530122
Jayachandran B052f1032016-06-21 10:17:41 +0530123/*
124 * Current Power Active - power status of cores, set by hardware
125 * CPA Mask for a given core mask pattern, cm
126 */
127#define SKL_ADSPCS_CPA_SHIFT 24
128#define SKL_ADSPCS_CPA_MASK(cm) ((cm) << SKL_ADSPCS_CPA_SHIFT)
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +0530129
Jayachandran B5bb4cd42016-11-03 17:07:17 +0530130/* DSP Core state */
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +0530131enum skl_dsp_states {
132 SKL_DSP_RUNNING = 1,
Jayachandran B5bb4cd42016-11-03 17:07:17 +0530133 /* Running in D0i3 state; can be in streaming or non-streaming D0i3 */
134 SKL_DSP_RUNNING_D0I3, /* Running in D0i3 state*/
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +0530135 SKL_DSP_RESET,
136};
137
Jayachandran B5bb4cd42016-11-03 17:07:17 +0530138/* D0i3 substates */
139enum skl_dsp_d0i3_states {
140 SKL_DSP_D0I3_NONE = -1, /* No D0i3 */
141 SKL_DSP_D0I3_NON_STREAMING = 0,
142 SKL_DSP_D0I3_STREAMING = 1,
143};
144
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +0530145struct skl_dsp_fw_ops {
146 int (*load_fw)(struct sst_dsp *ctx);
147 /* FW module parser/loader */
Ramesh Babu1ef015e2016-07-26 18:06:48 +0530148 int (*load_library)(struct sst_dsp *ctx,
Subhransu S. Prustyebe89072017-04-25 12:18:20 +0530149 struct skl_lib_info *linfo, int lib_count);
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +0530150 int (*parse_fw)(struct sst_dsp *ctx);
Jayachandran B052f1032016-06-21 10:17:41 +0530151 int (*set_state_D0)(struct sst_dsp *ctx, unsigned int core_id);
152 int (*set_state_D3)(struct sst_dsp *ctx, unsigned int core_id);
Jayachandran B5bb4cd42016-11-03 17:07:17 +0530153 int (*set_state_D0i3)(struct sst_dsp *ctx);
154 int (*set_state_D0i0)(struct sst_dsp *ctx);
Subhransu S. Prustya750ba52015-07-10 22:18:44 +0530155 unsigned int (*get_fw_errcode)(struct sst_dsp *ctx);
Shreyas NC09305da2016-04-21 11:45:22 +0530156 int (*load_mod)(struct sst_dsp *ctx, u16 mod_id, u8 *mod_name);
Dharageswari R6c5768b2015-12-03 23:29:50 +0530157 int (*unload_mod)(struct sst_dsp *ctx, u16 mod_id);
158
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +0530159};
160
Subhransu S. Prustyb6626802015-07-10 22:18:39 +0530161struct skl_dsp_loader_ops {
Jeeja KP92eb4f62016-03-11 10:12:56 +0530162 int stream_tag;
163
Subhransu S. Prustyb6626802015-07-10 22:18:39 +0530164 int (*alloc_dma_buf)(struct device *dev,
165 struct snd_dma_buffer *dmab, size_t size);
166 int (*free_dma_buf)(struct device *dev,
167 struct snd_dma_buffer *dmab);
Jeeja KP92eb4f62016-03-11 10:12:56 +0530168 int (*prepare)(struct device *dev, unsigned int format,
169 unsigned int byte_size,
170 struct snd_dma_buffer *bufp);
171 int (*trigger)(struct device *dev, bool start, int stream_tag);
172
173 int (*cleanup)(struct device *dev, struct snd_dma_buffer *dmab,
174 int stream_tag);
Subhransu S. Prustyb6626802015-07-10 22:18:39 +0530175};
176
Jeeja KPb26199e2017-03-24 23:10:31 +0530177#define MAX_INSTANCE_BUFF 2
178
179struct uuid_module {
180 uuid_le uuid;
181 int id;
182 int is_loadable;
183 int max_instance;
184 u64 pvt_id[MAX_INSTANCE_BUFF];
185 int *instance_id;
186
187 struct list_head list;
188};
189
Dharageswari R6c5768b2015-12-03 23:29:50 +0530190struct skl_load_module_info {
191 u16 mod_id;
192 const struct firmware *fw;
193};
194
195struct skl_module_table {
196 struct skl_load_module_info *mod_info;
197 unsigned int usage_cnt;
198 struct list_head list;
199};
200
Vinod Koul3e40a782015-07-10 22:18:42 +0530201void skl_cldma_process_intr(struct sst_dsp *ctx);
202void skl_cldma_int_disable(struct sst_dsp *ctx);
203int skl_cldma_prepare(struct sst_dsp *ctx);
Jeeja KPb7d0254c52017-03-13 22:11:31 +0530204int skl_cldma_wait_interruptible(struct sst_dsp *ctx);
Vinod Koul3e40a782015-07-10 22:18:42 +0530205
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +0530206void skl_dsp_set_state_locked(struct sst_dsp *ctx, int state);
207struct sst_dsp *skl_dsp_ctx_init(struct device *dev,
208 struct sst_dsp_device *sst_dev, int irq);
Subhransu S. Prusty8e9d8e12017-12-18 10:46:49 +0530209int skl_dsp_acquire_irq(struct sst_dsp *sst);
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +0530210bool is_skl_dsp_running(struct sst_dsp *ctx);
Jayachandran B052f1032016-06-21 10:17:41 +0530211
212unsigned int skl_dsp_get_enabled_cores(struct sst_dsp *ctx);
213void skl_dsp_init_core_state(struct sst_dsp *ctx);
214int skl_dsp_enable_core(struct sst_dsp *ctx, unsigned int core_mask);
215int skl_dsp_disable_core(struct sst_dsp *ctx, unsigned int core_mask);
216int skl_dsp_core_power_up(struct sst_dsp *ctx, unsigned int core_mask);
217int skl_dsp_core_power_down(struct sst_dsp *ctx, unsigned int core_mask);
218int skl_dsp_core_unset_reset_state(struct sst_dsp *ctx,
219 unsigned int core_mask);
220int skl_dsp_start_core(struct sst_dsp *ctx, unsigned int core_mask);
221
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +0530222irqreturn_t skl_dsp_sst_interrupt(int irq, void *dev_id);
223int skl_dsp_wake(struct sst_dsp *ctx);
224int skl_dsp_sleep(struct sst_dsp *ctx);
225void skl_dsp_free(struct sst_dsp *dsp);
226
Jayachandran B052f1032016-06-21 10:17:41 +0530227int skl_dsp_get_core(struct sst_dsp *ctx, unsigned int core_id);
228int skl_dsp_put_core(struct sst_dsp *ctx, unsigned int core_id);
229
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +0530230int skl_dsp_boot(struct sst_dsp *ctx);
Subhransu S. Prustya750ba52015-07-10 22:18:44 +0530231int skl_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
Vinod Koulaecf6fd2015-11-05 21:34:15 +0530232 const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
233 struct skl_sst **dsp);
Jeeja KP92eb4f62016-03-11 10:12:56 +0530234int bxt_sst_dsp_init(struct device *dev, void __iomem *mmio_base, int irq,
235 const char *fw_name, struct skl_dsp_loader_ops dsp_ops,
236 struct skl_sst **dsp);
Vinod Koul78cdbbd2016-07-26 18:06:42 +0530237int skl_sst_init_fw(struct device *dev, struct skl_sst *ctx);
238int bxt_sst_init_fw(struct device *dev, struct skl_sst *ctx);
Subhransu S. Prustya750ba52015-07-10 22:18:44 +0530239void skl_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx);
Jeeja KP92eb4f62016-03-11 10:12:56 +0530240void bxt_sst_dsp_cleanup(struct device *dev, struct skl_sst *ctx);
Subhransu S. Prustye973e31a2015-07-09 21:38:55 +0530241
Senthilnathan Veppura8e2c192016-07-26 18:06:44 +0530242int snd_skl_parse_uuids(struct sst_dsp *ctx, const struct firmware *fw,
Dharageswari R0556ba42016-08-10 09:40:48 +0530243 unsigned int offset, int index);
Jeeja KPb26199e2017-03-24 23:10:31 +0530244int skl_get_pvt_id(struct skl_sst *ctx, uuid_le *uuid_mod, int instance_id);
245int skl_put_pvt_id(struct skl_sst *ctx, uuid_le *uuid_mod, int *pvt_id);
Dharageswari R55a92ea2016-09-22 14:00:39 +0530246int skl_get_pvt_instance_id_map(struct skl_sst *ctx,
247 int module_id, int instance_id);
Shreyas NCea6b3e92016-05-30 17:42:59 +0530248void skl_freeup_uuid_list(struct skl_sst *ctx);
249
Ramesh Babu6eee8722016-05-30 17:42:55 +0530250int skl_dsp_strip_extended_manifest(struct firmware *fw);
G Kranthicb729d82017-03-13 22:11:29 +0530251void skl_dsp_enable_notification(struct skl_sst *ctx, bool enable);
Pradeep Tewani94523142017-12-06 16:34:03 +0530252
253void skl_dsp_set_astate_cfg(struct skl_sst *ctx, u32 cnt, void *data);
254
G Kranthi9fe9c712017-04-25 12:18:19 +0530255int skl_sst_ctx_init(struct device *dev, int irq, const char *fw_name,
256 struct skl_dsp_loader_ops dsp_ops, struct skl_sst **dsp,
257 struct sst_dsp_device *skl_dev);
Subhransu S. Prustyebe89072017-04-25 12:18:20 +0530258int skl_prepare_lib_load(struct skl_sst *skl, struct skl_lib_info *linfo,
259 struct firmware *stripped_fw,
260 unsigned int hdr_offset, int index);
261void skl_release_library(struct skl_lib_info *linfo, int lib_count);
G Kranthicb729d82017-03-13 22:11:29 +0530262
Subhransu S. Prusty3582f9a2015-07-03 16:04:03 +0530263#endif /*__SKL_SST_DSP_H__*/