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Tarek Dakhran107e6aa2014-05-27 06:54:13 +09001/*
2 * SAMSUNG EXYNOS5410 SoC device tree source
3 *
4 * Copyright (c) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
6 *
7 * SAMSUNG EXYNOS5410 SoC device nodes are listed in this file.
8 * EXYNOS5410 based board files can include this file and provide
9 * values for board specfic bindings.
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
14 */
15
16#include "skeleton.dtsi"
17#include <dt-bindings/clock/exynos5410.h>
18
19/ {
20 compatible = "samsung,exynos5410", "samsung,exynos5";
21 interrupt-parent = <&gic>;
22
Tomasz Figa1e64f482014-06-26 13:24:35 +020023 aliases {
Hakjoo Kim1eca8252015-03-15 23:00:33 +010024 pinctrl0 = &pinctrl_0;
25 pinctrl1 = &pinctrl_1;
26 pinctrl2 = &pinctrl_2;
27 pinctrl3 = &pinctrl_3;
Tomasz Figa1e64f482014-06-26 13:24:35 +020028 serial0 = &uart0;
29 serial1 = &uart1;
30 serial2 = &uart2;
31 };
32
Tarek Dakhran107e6aa2014-05-27 06:54:13 +090033 cpus {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 CPU0: cpu@0 {
38 device_type = "cpu";
39 compatible = "arm,cortex-a15";
40 reg = <0x0>;
Andreas Faerber22298d62014-07-08 08:17:14 +090041 clock-frequency = <1600000000>;
Tarek Dakhran107e6aa2014-05-27 06:54:13 +090042 };
43
44 CPU1: cpu@1 {
45 device_type = "cpu";
46 compatible = "arm,cortex-a15";
47 reg = <0x1>;
Andreas Faerber22298d62014-07-08 08:17:14 +090048 clock-frequency = <1600000000>;
Tarek Dakhran107e6aa2014-05-27 06:54:13 +090049 };
50
51 CPU2: cpu@2 {
52 device_type = "cpu";
53 compatible = "arm,cortex-a15";
54 reg = <0x2>;
Andreas Faerber22298d62014-07-08 08:17:14 +090055 clock-frequency = <1600000000>;
Tarek Dakhran107e6aa2014-05-27 06:54:13 +090056 };
57
58 CPU3: cpu@3 {
59 device_type = "cpu";
60 compatible = "arm,cortex-a15";
61 reg = <0x3>;
Andreas Faerber22298d62014-07-08 08:17:14 +090062 clock-frequency = <1600000000>;
Tarek Dakhran107e6aa2014-05-27 06:54:13 +090063 };
64 };
65
66 soc: soc {
67 compatible = "simple-bus";
68 #address-cells = <1>;
69 #size-cells = <1>;
70 ranges;
71
72 combiner: interrupt-controller@10440000 {
73 compatible = "samsung,exynos4210-combiner";
74 #interrupt-cells = <2>;
75 interrupt-controller;
76 samsung,combiner-nr = <32>;
77 reg = <0x10440000 0x1000>;
78 interrupts = <0 0 0>, <0 1 0>, <0 2 0>, <0 3 0>,
79 <0 4 0>, <0 5 0>, <0 6 0>, <0 7 0>,
80 <0 8 0>, <0 9 0>, <0 10 0>, <0 11 0>,
81 <0 12 0>, <0 13 0>, <0 14 0>, <0 15 0>,
82 <0 16 0>, <0 17 0>, <0 18 0>, <0 19 0>,
83 <0 20 0>, <0 21 0>, <0 22 0>, <0 23 0>,
84 <0 24 0>, <0 25 0>, <0 26 0>, <0 27 0>,
85 <0 28 0>, <0 29 0>, <0 30 0>, <0 31 0>;
86 };
87
88 gic: interrupt-controller@10481000 {
89 compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
90 #interrupt-cells = <3>;
91 interrupt-controller;
92 reg = <0x10481000 0x1000>,
93 <0x10482000 0x1000>,
94 <0x10484000 0x2000>,
95 <0x10486000 0x2000>;
96 interrupts = <1 9 0xf04>;
97 };
98
99 chipid@10000000 {
100 compatible = "samsung,exynos4210-chipid";
101 reg = <0x10000000 0x100>;
102 };
103
Andreas Faerber0a8f5942014-07-29 06:09:56 +0900104 pmu_system_controller: system-controller@10040000 {
105 compatible = "samsung,exynos5410-pmu", "syscon";
106 reg = <0x10040000 0x5000>;
107 };
108
Alim Akhtar35135f42015-10-20 14:54:43 +0530109 poweroff: syscon-poweroff {
110 compatible = "syscon-poweroff";
111 regmap = <&pmu_system_controller>;
112 offset = <0x330C>; /* PS_HOLD_CONTROL */
113 mask = <0x5200>; /* reset value */
114 };
115
116 reboot: syscon-reboot {
117 compatible = "syscon-reboot";
118 regmap = <&pmu_system_controller>;
119 offset = <0x0400>; /* SWRESET */
120 mask = <0x1>;
121 };
122
Tarek Dakhran107e6aa2014-05-27 06:54:13 +0900123 mct: mct@101C0000 {
124 compatible = "samsung,exynos4210-mct";
125 reg = <0x101C0000 0xB00>;
126 interrupt-parent = <&interrupt_map>;
127 interrupts = <0>, <1>, <2>, <3>,
128 <4>, <5>, <6>, <7>,
129 <8>, <9>, <10>, <11>;
130 clocks = <&fin_pll>, <&clock CLK_MCT>;
131 clock-names = "fin_pll", "mct";
132
133 interrupt_map: interrupt-map {
134 #interrupt-cells = <1>;
135 #address-cells = <0>;
136 #size-cells = <0>;
137 interrupt-map = <0 &combiner 23 3>,
138 <1 &combiner 23 4>,
139 <2 &combiner 25 2>,
140 <3 &combiner 25 3>,
141 <4 &gic 0 120 0>,
142 <5 &gic 0 121 0>,
143 <6 &gic 0 122 0>,
144 <7 &gic 0 123 0>,
145 <8 &gic 0 128 0>,
146 <9 &gic 0 129 0>,
147 <10 &gic 0 130 0>,
148 <11 &gic 0 131 0>;
149 };
150 };
151
152 sysram@02020000 {
153 compatible = "mmio-sram";
154 reg = <0x02020000 0x54000>;
155 #address-cells = <1>;
156 #size-cells = <1>;
157 ranges = <0 0x02020000 0x54000>;
158
159 smp-sysram@0 {
160 compatible = "samsung,exynos4210-sysram";
161 reg = <0x0 0x1000>;
162 };
163
164 smp-sysram@53000 {
165 compatible = "samsung,exynos4210-sysram-ns";
166 reg = <0x53000 0x1000>;
167 };
168 };
169
170 clock: clock-controller@10010000 {
171 compatible = "samsung,exynos5410-clock";
172 reg = <0x10010000 0x30000>;
173 #clock-cells = <1>;
174 };
175
176 mmc_0: mmc@12200000 {
177 compatible = "samsung,exynos5250-dw-mshc";
178 reg = <0x12200000 0x1000>;
179 interrupts = <0 75 0>;
180 #address-cells = <1>;
181 #size-cells = <0>;
182 clocks = <&clock CLK_MMC0>, <&clock CLK_SCLK_MMC0>;
183 clock-names = "biu", "ciu";
184 fifo-depth = <0x80>;
185 status = "disabled";
186 };
187
188 mmc_1: mmc@12210000 {
189 compatible = "samsung,exynos5250-dw-mshc";
190 reg = <0x12210000 0x1000>;
191 interrupts = <0 76 0>;
192 #address-cells = <1>;
193 #size-cells = <0>;
194 clocks = <&clock CLK_MMC1>, <&clock CLK_SCLK_MMC1>;
195 clock-names = "biu", "ciu";
196 fifo-depth = <0x80>;
197 status = "disabled";
198 };
199
200 mmc_2: mmc@12220000 {
201 compatible = "samsung,exynos5250-dw-mshc";
202 reg = <0x12220000 0x1000>;
203 interrupts = <0 77 0>;
204 #address-cells = <1>;
205 #size-cells = <0>;
206 clocks = <&clock CLK_MMC2>, <&clock CLK_SCLK_MMC2>;
207 clock-names = "biu", "ciu";
208 fifo-depth = <0x80>;
209 status = "disabled";
210 };
211
Hakjoo Kim1eca8252015-03-15 23:00:33 +0100212 pinctrl_0: pinctrl@13400000 {
213 compatible = "samsung,exynos5410-pinctrl";
214 reg = <0x13400000 0x1000>;
215 interrupts = <0 45 0>;
216
217 wakeup-interrupt-controller {
218 compatible = "samsung,exynos4210-wakeup-eint";
219 interrupt-parent = <&gic>;
220 interrupts = <0 32 0>;
221 };
222 };
223
224 pinctrl_1: pinctrl@14000000 {
225 compatible = "samsung,exynos5410-pinctrl";
226 reg = <0x14000000 0x1000>;
227 interrupts = <0 46 0>;
228 };
229
230 pinctrl_2: pinctrl@10d10000 {
231 compatible = "samsung,exynos5410-pinctrl";
232 reg = <0x10d10000 0x1000>;
233 interrupts = <0 50 0>;
234 };
235
236 pinctrl_3: pinctrl@03860000 {
237 compatible = "samsung,exynos5410-pinctrl";
238 reg = <0x03860000 0x1000>;
239 interrupts = <0 47 0>;
240 };
241
Tarek Dakhran107e6aa2014-05-27 06:54:13 +0900242 uart0: serial@12C00000 {
243 compatible = "samsung,exynos4210-uart";
244 reg = <0x12C00000 0x100>;
245 interrupts = <0 51 0>;
246 clocks = <&clock CLK_UART0>, <&clock CLK_SCLK_UART0>;
247 clock-names = "uart", "clk_uart_baud0";
248 status = "disabled";
249 };
250
251 uart1: serial@12C10000 {
252 compatible = "samsung,exynos4210-uart";
253 reg = <0x12C10000 0x100>;
254 interrupts = <0 52 0>;
255 clocks = <&clock CLK_UART1>, <&clock CLK_SCLK_UART1>;
256 clock-names = "uart", "clk_uart_baud0";
257 status = "disabled";
258 };
259
260 uart2: serial@12C20000 {
261 compatible = "samsung,exynos4210-uart";
262 reg = <0x12C20000 0x100>;
263 interrupts = <0 53 0>;
264 clocks = <&clock CLK_UART2>, <&clock CLK_SCLK_UART2>;
265 clock-names = "uart", "clk_uart_baud0";
266 status = "disabled";
267 };
268 };
269};
Hakjoo Kim1eca8252015-03-15 23:00:33 +0100270
271#include "exynos5410-pinctrl.dtsi"