blob: 3dfebfb8434ff63e9b2ce7a2b2a86a7b01fad281 [file] [log] [blame]
Johannes Berg02a7fa02011-04-05 09:42:12 -07001/******************************************************************************
2 *
Wey-Yi Guy4e318262011-12-27 11:21:32 -08003 * Copyright(c) 2003 - 2012 Intel Corporation. All rights reserved.
Johannes Berg02a7fa02011-04-05 09:42:12 -07004 *
5 * Portions of this file are derived from the ipw3945 project.
6 *
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of version 2 of the GNU General Public License as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * more details.
15 *
16 * You should have received a copy of the GNU General Public License along with
17 * this program; if not, write to the Free Software Foundation, Inc.,
18 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 *
20 * The full GNU General Public License is included in this distribution in the
21 * file called LICENSE.
22 *
23 * Contact Information:
24 * Intel Linux Wireless <ilw@linux.intel.com>
25 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
26 *
27 *****************************************************************************/
Emmanuel Grumbach83ed9012011-08-25 23:11:14 -070028#include <linux/delay.h>
29#include <linux/device.h>
Don Frycc5f7e32012-05-16 22:54:27 +020030#include <linux/export.h>
Johannes Berg02a7fa02011-04-05 09:42:12 -070031
32#include "iwl-io.h"
Paul Bolle6ac7d112012-06-06 14:17:46 +020033#include "iwl-csr.h"
Emmanuel Grumbach83ed9012011-08-25 23:11:14 -070034#include "iwl-debug.h"
Johannes Berg02a7fa02011-04-05 09:42:12 -070035
36#define IWL_POLL_INTERVAL 10 /* microseconds */
37
Emmanuel Grumbach1042db22012-01-03 16:56:15 +020038static inline void __iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)
Johannes Berg02a7fa02011-04-05 09:42:12 -070039{
Emmanuel Grumbach1042db22012-01-03 16:56:15 +020040 iwl_write32(trans, reg, iwl_read32(trans, reg) | mask);
Johannes Berg02a7fa02011-04-05 09:42:12 -070041}
42
Emmanuel Grumbach1042db22012-01-03 16:56:15 +020043static inline void __iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
Johannes Berg02a7fa02011-04-05 09:42:12 -070044{
Emmanuel Grumbach1042db22012-01-03 16:56:15 +020045 iwl_write32(trans, reg, iwl_read32(trans, reg) & ~mask);
Johannes Berg02a7fa02011-04-05 09:42:12 -070046}
47
Emmanuel Grumbach1042db22012-01-03 16:56:15 +020048void iwl_set_bit(struct iwl_trans *trans, u32 reg, u32 mask)
Johannes Berg02a7fa02011-04-05 09:42:12 -070049{
50 unsigned long flags;
51
Emmanuel Grumbach1042db22012-01-03 16:56:15 +020052 spin_lock_irqsave(&trans->reg_lock, flags);
53 __iwl_set_bit(trans, reg, mask);
54 spin_unlock_irqrestore(&trans->reg_lock, flags);
Johannes Berg02a7fa02011-04-05 09:42:12 -070055}
Don Frycc5f7e32012-05-16 22:54:27 +020056EXPORT_SYMBOL_GPL(iwl_set_bit);
Johannes Berg02a7fa02011-04-05 09:42:12 -070057
Emmanuel Grumbach1042db22012-01-03 16:56:15 +020058void iwl_clear_bit(struct iwl_trans *trans, u32 reg, u32 mask)
Johannes Berg02a7fa02011-04-05 09:42:12 -070059{
60 unsigned long flags;
61
Emmanuel Grumbach1042db22012-01-03 16:56:15 +020062 spin_lock_irqsave(&trans->reg_lock, flags);
63 __iwl_clear_bit(trans, reg, mask);
64 spin_unlock_irqrestore(&trans->reg_lock, flags);
Johannes Berg02a7fa02011-04-05 09:42:12 -070065}
Don Frycc5f7e32012-05-16 22:54:27 +020066EXPORT_SYMBOL_GPL(iwl_clear_bit);
Johannes Berg02a7fa02011-04-05 09:42:12 -070067
Johannes Berg2baa2e572012-05-29 14:47:30 +020068void iwl_set_bits_mask(struct iwl_trans *trans, u32 reg, u32 mask, u32 value)
69{
70 unsigned long flags;
71 u32 v;
72
73#ifdef CONFIG_IWLWIFI_DEBUG
74 WARN_ON_ONCE(value & ~mask);
75#endif
76
77 spin_lock_irqsave(&trans->reg_lock, flags);
78 v = iwl_read32(trans, reg);
79 v &= ~mask;
80 v |= value;
81 iwl_write32(trans, reg, v);
82 spin_unlock_irqrestore(&trans->reg_lock, flags);
83}
84EXPORT_SYMBOL_GPL(iwl_set_bits_mask);
85
Emmanuel Grumbach1042db22012-01-03 16:56:15 +020086int iwl_poll_bit(struct iwl_trans *trans, u32 addr,
Johannes Berg02a7fa02011-04-05 09:42:12 -070087 u32 bits, u32 mask, int timeout)
88{
89 int t = 0;
90
91 do {
Emmanuel Grumbach1042db22012-01-03 16:56:15 +020092 if ((iwl_read32(trans, addr) & mask) == (bits & mask))
Johannes Berg02a7fa02011-04-05 09:42:12 -070093 return t;
94 udelay(IWL_POLL_INTERVAL);
95 t += IWL_POLL_INTERVAL;
96 } while (t < timeout);
97
98 return -ETIMEDOUT;
99}
Don Frycc5f7e32012-05-16 22:54:27 +0200100EXPORT_SYMBOL_GPL(iwl_poll_bit);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700101
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200102int iwl_grab_nic_access_silent(struct iwl_trans *trans)
Johannes Berg02a7fa02011-04-05 09:42:12 -0700103{
104 int ret;
Johannes Berg02a7fa02011-04-05 09:42:12 -0700105
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200106 lockdep_assert_held(&trans->reg_lock);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700107
108 /* this bit wakes up the NIC */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200109 __iwl_set_bit(trans, CSR_GP_CNTRL,
110 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700111
112 /*
113 * These bits say the device is running, and should keep running for
114 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1),
115 * but they do not indicate that embedded SRAM is restored yet;
116 * 3945 and 4965 have volatile SRAM, and must save/restore contents
117 * to/from host DRAM when sleeping/waking for power-saving.
118 * Each direction takes approximately 1/4 millisecond; with this
119 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a
120 * series of register accesses are expected (e.g. reading Event Log),
121 * to keep device from sleeping.
122 *
123 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that
124 * SRAM is okay/restored. We don't check that here because this call
125 * is just for hardware register access; but GP1 MAC_SLEEP check is a
126 * good idea before accessing 3945/4965 SRAM (e.g. reading Event Log).
127 *
128 * 5000 series and later (including 1000 series) have non-volatile SRAM,
129 * and do not save/restore SRAM when power cycling.
130 */
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200131 ret = iwl_poll_bit(trans, CSR_GP_CNTRL,
Johannes Berg02a7fa02011-04-05 09:42:12 -0700132 CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN,
133 (CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY |
134 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP), 15000);
135 if (ret < 0) {
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200136 iwl_write32(trans, CSR_RESET, CSR_RESET_REG_FLAG_FORCE_NMI);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700137 return -EIO;
138 }
139
140 return 0;
141}
Don Frycc5f7e32012-05-16 22:54:27 +0200142EXPORT_SYMBOL_GPL(iwl_grab_nic_access_silent);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700143
Stanislaw Gruszkabfe4b802012-03-07 09:52:24 -0800144bool iwl_grab_nic_access(struct iwl_trans *trans)
Johannes Berg41199042011-04-19 07:42:03 -0700145{
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200146 int ret = iwl_grab_nic_access_silent(trans);
Stanislaw Gruszkaaa5affb2012-03-07 09:52:23 -0800147 if (unlikely(ret)) {
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200148 u32 val = iwl_read32(trans, CSR_GP_CNTRL);
Stanislaw Gruszkaaa5affb2012-03-07 09:52:23 -0800149 WARN_ONCE(1, "Timeout waiting for hardware access "
150 "(CSR_GP_CNTRL 0x%08x)\n", val);
Stanislaw Gruszkabfe4b802012-03-07 09:52:24 -0800151 return false;
Johannes Berg41199042011-04-19 07:42:03 -0700152 }
153
Stanislaw Gruszkabfe4b802012-03-07 09:52:24 -0800154 return true;
Johannes Berg41199042011-04-19 07:42:03 -0700155}
Don Frycc5f7e32012-05-16 22:54:27 +0200156EXPORT_SYMBOL_GPL(iwl_grab_nic_access);
Johannes Berg41199042011-04-19 07:42:03 -0700157
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200158void iwl_release_nic_access(struct iwl_trans *trans)
Johannes Berg02a7fa02011-04-05 09:42:12 -0700159{
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200160 lockdep_assert_held(&trans->reg_lock);
161 __iwl_clear_bit(trans, CSR_GP_CNTRL,
Johannes Berg02a7fa02011-04-05 09:42:12 -0700162 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ);
Stanislaw Gruszka3a73a302012-03-07 09:52:25 -0800163 /*
164 * Above we read the CSR_GP_CNTRL register, which will flush
165 * any previous writes, but we need the write that clears the
166 * MAC_ACCESS_REQ bit to be performed before any other writes
167 * scheduled on different CPUs (after we drop reg_lock).
168 */
169 mmiowb();
Johannes Berg02a7fa02011-04-05 09:42:12 -0700170}
Don Frycc5f7e32012-05-16 22:54:27 +0200171EXPORT_SYMBOL_GPL(iwl_release_nic_access);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700172
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200173u32 iwl_read_direct32(struct iwl_trans *trans, u32 reg)
Johannes Berg02a7fa02011-04-05 09:42:12 -0700174{
175 u32 value;
176 unsigned long flags;
177
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200178 spin_lock_irqsave(&trans->reg_lock, flags);
179 iwl_grab_nic_access(trans);
180 value = iwl_read32(trans, reg);
181 iwl_release_nic_access(trans);
182 spin_unlock_irqrestore(&trans->reg_lock, flags);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700183
184 return value;
185}
Don Frycc5f7e32012-05-16 22:54:27 +0200186EXPORT_SYMBOL_GPL(iwl_read_direct32);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700187
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200188void iwl_write_direct32(struct iwl_trans *trans, u32 reg, u32 value)
Johannes Berg02a7fa02011-04-05 09:42:12 -0700189{
190 unsigned long flags;
191
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200192 spin_lock_irqsave(&trans->reg_lock, flags);
Stanislaw Gruszkabfe4b802012-03-07 09:52:24 -0800193 if (likely(iwl_grab_nic_access(trans))) {
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200194 iwl_write32(trans, reg, value);
195 iwl_release_nic_access(trans);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700196 }
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200197 spin_unlock_irqrestore(&trans->reg_lock, flags);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700198}
Don Frycc5f7e32012-05-16 22:54:27 +0200199EXPORT_SYMBOL_GPL(iwl_write_direct32);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700200
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200201int iwl_poll_direct_bit(struct iwl_trans *trans, u32 addr, u32 mask,
Johannes Berg02a7fa02011-04-05 09:42:12 -0700202 int timeout)
203{
204 int t = 0;
205
206 do {
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200207 if ((iwl_read_direct32(trans, addr) & mask) == mask)
Johannes Berg02a7fa02011-04-05 09:42:12 -0700208 return t;
209 udelay(IWL_POLL_INTERVAL);
210 t += IWL_POLL_INTERVAL;
211 } while (t < timeout);
212
213 return -ETIMEDOUT;
214}
Don Frycc5f7e32012-05-16 22:54:27 +0200215EXPORT_SYMBOL_GPL(iwl_poll_direct_bit);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700216
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200217static inline u32 __iwl_read_prph(struct iwl_trans *trans, u32 reg)
Johannes Berg02a7fa02011-04-05 09:42:12 -0700218{
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200219 iwl_write32(trans, HBUS_TARG_PRPH_RADDR, reg | (3 << 24));
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200220 return iwl_read32(trans, HBUS_TARG_PRPH_RDAT);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700221}
222
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200223static inline void __iwl_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
Johannes Berg02a7fa02011-04-05 09:42:12 -0700224{
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200225 iwl_write32(trans, HBUS_TARG_PRPH_WADDR,
Johannes Berg02a7fa02011-04-05 09:42:12 -0700226 ((addr & 0x0000FFFF) | (3 << 24)));
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200227 iwl_write32(trans, HBUS_TARG_PRPH_WDAT, val);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700228}
229
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200230u32 iwl_read_prph(struct iwl_trans *trans, u32 reg)
Johannes Berg02a7fa02011-04-05 09:42:12 -0700231{
232 unsigned long flags;
233 u32 val;
234
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200235 spin_lock_irqsave(&trans->reg_lock, flags);
236 iwl_grab_nic_access(trans);
237 val = __iwl_read_prph(trans, reg);
238 iwl_release_nic_access(trans);
239 spin_unlock_irqrestore(&trans->reg_lock, flags);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700240 return val;
241}
Don Frycc5f7e32012-05-16 22:54:27 +0200242EXPORT_SYMBOL_GPL(iwl_read_prph);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700243
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200244void iwl_write_prph(struct iwl_trans *trans, u32 addr, u32 val)
Johannes Berg02a7fa02011-04-05 09:42:12 -0700245{
246 unsigned long flags;
247
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200248 spin_lock_irqsave(&trans->reg_lock, flags);
Stanislaw Gruszkabfe4b802012-03-07 09:52:24 -0800249 if (likely(iwl_grab_nic_access(trans))) {
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200250 __iwl_write_prph(trans, addr, val);
251 iwl_release_nic_access(trans);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700252 }
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200253 spin_unlock_irqrestore(&trans->reg_lock, flags);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700254}
Don Frycc5f7e32012-05-16 22:54:27 +0200255EXPORT_SYMBOL_GPL(iwl_write_prph);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700256
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200257void iwl_set_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask)
Johannes Berg02a7fa02011-04-05 09:42:12 -0700258{
259 unsigned long flags;
260
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200261 spin_lock_irqsave(&trans->reg_lock, flags);
Stanislaw Gruszkabfe4b802012-03-07 09:52:24 -0800262 if (likely(iwl_grab_nic_access(trans))) {
263 __iwl_write_prph(trans, reg,
264 __iwl_read_prph(trans, reg) | mask);
265 iwl_release_nic_access(trans);
266 }
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200267 spin_unlock_irqrestore(&trans->reg_lock, flags);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700268}
Don Frycc5f7e32012-05-16 22:54:27 +0200269EXPORT_SYMBOL_GPL(iwl_set_bits_prph);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700270
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200271void iwl_set_bits_mask_prph(struct iwl_trans *trans, u32 reg,
Johannes Berg02a7fa02011-04-05 09:42:12 -0700272 u32 bits, u32 mask)
273{
274 unsigned long flags;
275
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200276 spin_lock_irqsave(&trans->reg_lock, flags);
Stanislaw Gruszkabfe4b802012-03-07 09:52:24 -0800277 if (likely(iwl_grab_nic_access(trans))) {
278 __iwl_write_prph(trans, reg,
279 (__iwl_read_prph(trans, reg) & mask) | bits);
280 iwl_release_nic_access(trans);
281 }
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200282 spin_unlock_irqrestore(&trans->reg_lock, flags);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700283}
Don Frycc5f7e32012-05-16 22:54:27 +0200284EXPORT_SYMBOL_GPL(iwl_set_bits_mask_prph);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700285
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200286void iwl_clear_bits_prph(struct iwl_trans *trans, u32 reg, u32 mask)
Johannes Berg02a7fa02011-04-05 09:42:12 -0700287{
288 unsigned long flags;
289 u32 val;
290
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200291 spin_lock_irqsave(&trans->reg_lock, flags);
Stanislaw Gruszkabfe4b802012-03-07 09:52:24 -0800292 if (likely(iwl_grab_nic_access(trans))) {
293 val = __iwl_read_prph(trans, reg);
294 __iwl_write_prph(trans, reg, (val & ~mask));
295 iwl_release_nic_access(trans);
296 }
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200297 spin_unlock_irqrestore(&trans->reg_lock, flags);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700298}
Don Frycc5f7e32012-05-16 22:54:27 +0200299EXPORT_SYMBOL_GPL(iwl_clear_bits_prph);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700300
Emmanuel Grumbache4b16812012-06-06 08:18:40 +0300301void _iwl_read_targ_mem_dwords(struct iwl_trans *trans, u32 addr,
302 void *buf, int dwords)
Johannes Berg02a7fa02011-04-05 09:42:12 -0700303{
304 unsigned long flags;
Johannes Berge46f6532011-04-13 03:14:43 -0700305 int offs;
306 u32 *vals = buf;
Johannes Berg02a7fa02011-04-05 09:42:12 -0700307
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200308 spin_lock_irqsave(&trans->reg_lock, flags);
Stanislaw Gruszkabfe4b802012-03-07 09:52:24 -0800309 if (likely(iwl_grab_nic_access(trans))) {
310 iwl_write32(trans, HBUS_TARG_MEM_RADDR, addr);
Emmanuel Grumbache4b16812012-06-06 08:18:40 +0300311 for (offs = 0; offs < dwords; offs++)
Stanislaw Gruszkabfe4b802012-03-07 09:52:24 -0800312 vals[offs] = iwl_read32(trans, HBUS_TARG_MEM_RDAT);
313 iwl_release_nic_access(trans);
314 }
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200315 spin_unlock_irqrestore(&trans->reg_lock, flags);
Johannes Berge46f6532011-04-13 03:14:43 -0700316}
Emmanuel Grumbache4b16812012-06-06 08:18:40 +0300317EXPORT_SYMBOL_GPL(_iwl_read_targ_mem_dwords);
Johannes Berge46f6532011-04-13 03:14:43 -0700318
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200319u32 iwl_read_targ_mem(struct iwl_trans *trans, u32 addr)
Johannes Berge46f6532011-04-13 03:14:43 -0700320{
321 u32 value;
322
Emmanuel Grumbache4b16812012-06-06 08:18:40 +0300323 _iwl_read_targ_mem_dwords(trans, addr, &value, 1);
Johannes Berge46f6532011-04-13 03:14:43 -0700324
Johannes Berg02a7fa02011-04-05 09:42:12 -0700325 return value;
326}
Don Frycc5f7e32012-05-16 22:54:27 +0200327EXPORT_SYMBOL_GPL(iwl_read_targ_mem);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700328
Emmanuel Grumbache4b16812012-06-06 08:18:40 +0300329int _iwl_write_targ_mem_dwords(struct iwl_trans *trans, u32 addr,
330 void *buf, int dwords)
Johannes Berg02a7fa02011-04-05 09:42:12 -0700331{
332 unsigned long flags;
Hsu, Kennyee8ba882011-12-09 03:11:18 -0800333 int offs, result = 0;
334 u32 *vals = buf;
Johannes Berg02a7fa02011-04-05 09:42:12 -0700335
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200336 spin_lock_irqsave(&trans->reg_lock, flags);
Stanislaw Gruszkabfe4b802012-03-07 09:52:24 -0800337 if (likely(iwl_grab_nic_access(trans))) {
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200338 iwl_write32(trans, HBUS_TARG_MEM_WADDR, addr);
Emmanuel Grumbache4b16812012-06-06 08:18:40 +0300339 for (offs = 0; offs < dwords; offs++)
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200340 iwl_write32(trans, HBUS_TARG_MEM_WDAT, vals[offs]);
341 iwl_release_nic_access(trans);
Hsu, Kennyee8ba882011-12-09 03:11:18 -0800342 } else
343 result = -EBUSY;
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200344 spin_unlock_irqrestore(&trans->reg_lock, flags);
Hsu, Kennyee8ba882011-12-09 03:11:18 -0800345
346 return result;
347}
Emmanuel Grumbache4b16812012-06-06 08:18:40 +0300348EXPORT_SYMBOL_GPL(_iwl_write_targ_mem_dwords);
Hsu, Kennyee8ba882011-12-09 03:11:18 -0800349
Emmanuel Grumbach1042db22012-01-03 16:56:15 +0200350int iwl_write_targ_mem(struct iwl_trans *trans, u32 addr, u32 val)
Hsu, Kennyee8ba882011-12-09 03:11:18 -0800351{
Emmanuel Grumbache4b16812012-06-06 08:18:40 +0300352 return _iwl_write_targ_mem_dwords(trans, addr, &val, 1);
Johannes Berg02a7fa02011-04-05 09:42:12 -0700353}
Don Frycc5f7e32012-05-16 22:54:27 +0200354EXPORT_SYMBOL_GPL(iwl_write_targ_mem);