blob: 966512b2cacf37824bc2b2bccda04e6f26f12ddf [file] [log] [blame]
Cyrill Gorcunov47a486c2008-06-24 22:52:03 +02001/*
2 * local apic based NMI watchdog for various CPUs.
3 *
4 * This file also handles reservation of performance counters for coordination
5 * with other users (like oprofile).
6 *
7 * Note that these events normally don't tick when the CPU idles. This means
8 * the frequency varies with CPU load.
9 *
10 * Original code for K7/P6 written by Keith Owens
11 *
12 */
Andi Kleen09198e62007-05-02 19:27:20 +020013
14#include <linux/percpu.h>
15#include <linux/module.h>
16#include <linux/kernel.h>
17#include <linux/bitops.h>
18#include <linux/smp.h>
Don Zickus4a7863c2010-12-22 14:00:03 -050019#include <asm/nmi.h>
Ingo Molnar8b1fa1d2008-07-29 12:36:02 +020020#include <linux/kprobes.h>
21
Andi Kleen09198e62007-05-02 19:27:20 +020022#include <asm/apic.h>
Ingo Molnarcdd6c482009-09-21 12:02:48 +020023#include <asm/perf_event.h>
Andi Kleen09198e62007-05-02 19:27:20 +020024
Cyrill Gorcunov47a486c2008-06-24 22:52:03 +020025/*
26 * this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
27 * offset from MSR_P4_BSU_ESCR0.
28 *
29 * It will be the max for all platforms (for now)
Andi Kleen09198e62007-05-02 19:27:20 +020030 */
31#define NMI_MAX_COUNTER_BITS 66
32
Cyrill Gorcunov47a486c2008-06-24 22:52:03 +020033/*
34 * perfctr_nmi_owner tracks the ownership of the perfctr registers:
Andi Kleen09198e62007-05-02 19:27:20 +020035 * evtsel_nmi_owner tracks the ownership of the event selection
36 * - different performance counters/ event selection may be reserved for
37 * different subsystems this reservation system just tries to coordinate
38 * things a little
39 */
40static DECLARE_BITMAP(perfctr_nmi_owner, NMI_MAX_COUNTER_BITS);
41static DECLARE_BITMAP(evntsel_nmi_owner, NMI_MAX_COUNTER_BITS);
42
Andi Kleen09198e62007-05-02 19:27:20 +020043/* converts an msr to an appropriate reservation bit */
44static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr)
45{
Andi Kleen5dcccd82007-07-04 01:38:13 +020046 /* returns the bit offset of the performance counter register */
47 switch (boot_cpu_data.x86_vendor) {
48 case X86_VENDOR_AMD:
Robert Richter69d8e1e2011-02-02 17:40:58 +010049 if (msr >= MSR_F15H_PERF_CTR)
50 return (msr - MSR_F15H_PERF_CTR) >> 1;
Alan Cox8bdbd962009-07-04 00:35:45 +010051 return msr - MSR_K7_PERFCTR0;
Andi Kleen5dcccd82007-07-04 01:38:13 +020052 case X86_VENDOR_INTEL:
53 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
Alan Cox8bdbd962009-07-04 00:35:45 +010054 return msr - MSR_ARCH_PERFMON_PERFCTR0;
Andi Kleen5dcccd82007-07-04 01:38:13 +020055
56 switch (boot_cpu_data.x86) {
57 case 6:
Alan Cox8bdbd962009-07-04 00:35:45 +010058 return msr - MSR_P6_PERFCTR0;
Andi Kleen5dcccd82007-07-04 01:38:13 +020059 case 15:
Alan Cox8bdbd962009-07-04 00:35:45 +010060 return msr - MSR_P4_BPU_PERFCTR0;
Andi Kleen5dcccd82007-07-04 01:38:13 +020061 }
62 }
63 return 0;
Andi Kleen09198e62007-05-02 19:27:20 +020064}
65
Cyrill Gorcunov47a486c2008-06-24 22:52:03 +020066/*
67 * converts an msr to an appropriate reservation bit
68 * returns the bit offset of the event selection register
69 */
Andi Kleen09198e62007-05-02 19:27:20 +020070static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr)
71{
Andi Kleen5dcccd82007-07-04 01:38:13 +020072 /* returns the bit offset of the event selection register */
73 switch (boot_cpu_data.x86_vendor) {
74 case X86_VENDOR_AMD:
Robert Richter69d8e1e2011-02-02 17:40:58 +010075 if (msr >= MSR_F15H_PERF_CTL)
76 return (msr - MSR_F15H_PERF_CTL) >> 1;
Alan Cox8bdbd962009-07-04 00:35:45 +010077 return msr - MSR_K7_EVNTSEL0;
Andi Kleen5dcccd82007-07-04 01:38:13 +020078 case X86_VENDOR_INTEL:
79 if (cpu_has(&boot_cpu_data, X86_FEATURE_ARCH_PERFMON))
Alan Cox8bdbd962009-07-04 00:35:45 +010080 return msr - MSR_ARCH_PERFMON_EVENTSEL0;
Andi Kleen5dcccd82007-07-04 01:38:13 +020081
82 switch (boot_cpu_data.x86) {
83 case 6:
Alan Cox8bdbd962009-07-04 00:35:45 +010084 return msr - MSR_P6_EVNTSEL0;
Andi Kleen5dcccd82007-07-04 01:38:13 +020085 case 15:
Alan Cox8bdbd962009-07-04 00:35:45 +010086 return msr - MSR_P4_BSU_ESCR0;
Andi Kleen5dcccd82007-07-04 01:38:13 +020087 }
88 }
89 return 0;
90
Andi Kleen09198e62007-05-02 19:27:20 +020091}
92
93/* checks for a bit availability (hack for oprofile) */
94int avail_to_resrv_perfctr_nmi_bit(unsigned int counter)
95{
96 BUG_ON(counter > NMI_MAX_COUNTER_BITS);
97
Alan Cox8bdbd962009-07-04 00:35:45 +010098 return !test_bit(counter, perfctr_nmi_owner);
Andi Kleen09198e62007-05-02 19:27:20 +020099}
Cyrill Gorcunov47a486c2008-06-24 22:52:03 +0200100EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit);
Andi Kleen09198e62007-05-02 19:27:20 +0200101
102int reserve_perfctr_nmi(unsigned int msr)
103{
104 unsigned int counter;
105
106 counter = nmi_perfctr_msr_to_bit(msr);
Stephane Eranian124d3952007-10-19 20:35:04 +0200107 /* register not managed by the allocator? */
108 if (counter > NMI_MAX_COUNTER_BITS)
109 return 1;
Andi Kleen09198e62007-05-02 19:27:20 +0200110
111 if (!test_and_set_bit(counter, perfctr_nmi_owner))
112 return 1;
113 return 0;
114}
Cyrill Gorcunov47a486c2008-06-24 22:52:03 +0200115EXPORT_SYMBOL(reserve_perfctr_nmi);
Andi Kleen09198e62007-05-02 19:27:20 +0200116
117void release_perfctr_nmi(unsigned int msr)
118{
119 unsigned int counter;
120
121 counter = nmi_perfctr_msr_to_bit(msr);
Stephane Eranian124d3952007-10-19 20:35:04 +0200122 /* register not managed by the allocator? */
123 if (counter > NMI_MAX_COUNTER_BITS)
124 return;
Andi Kleen09198e62007-05-02 19:27:20 +0200125
126 clear_bit(counter, perfctr_nmi_owner);
127}
Cyrill Gorcunov47a486c2008-06-24 22:52:03 +0200128EXPORT_SYMBOL(release_perfctr_nmi);
Andi Kleen09198e62007-05-02 19:27:20 +0200129
130int reserve_evntsel_nmi(unsigned int msr)
131{
132 unsigned int counter;
133
134 counter = nmi_evntsel_msr_to_bit(msr);
Stephane Eranian124d3952007-10-19 20:35:04 +0200135 /* register not managed by the allocator? */
136 if (counter > NMI_MAX_COUNTER_BITS)
137 return 1;
Andi Kleen09198e62007-05-02 19:27:20 +0200138
139 if (!test_and_set_bit(counter, evntsel_nmi_owner))
140 return 1;
141 return 0;
142}
Cyrill Gorcunov47a486c2008-06-24 22:52:03 +0200143EXPORT_SYMBOL(reserve_evntsel_nmi);
Andi Kleen09198e62007-05-02 19:27:20 +0200144
145void release_evntsel_nmi(unsigned int msr)
146{
147 unsigned int counter;
148
149 counter = nmi_evntsel_msr_to_bit(msr);
Stephane Eranian124d3952007-10-19 20:35:04 +0200150 /* register not managed by the allocator? */
151 if (counter > NMI_MAX_COUNTER_BITS)
152 return;
Andi Kleen09198e62007-05-02 19:27:20 +0200153
154 clear_bit(counter, evntsel_nmi_owner);
155}
Andi Kleen09198e62007-05-02 19:27:20 +0200156EXPORT_SYMBOL(release_evntsel_nmi);