Documentation/devicetree/bindings/sound/st,stm32-i2s.txt

STMicroelectronics STM32 SPI/I2S Controller

The SPI/I2S block supports I2S/PCM protocols when configured on I2S mode.
Only some SPI instances support I2S.

Required properties:
  - compatible: Must be "st,stm32h7-i2s"
  - reg: Offset and length of the device's register set.
  - interrupts: Must contain the interrupt line id.
  - clocks: Must contain phandle and clock specifier pairs for each entry
	in clock-names.
  - clock-names: Must contain "i2sclk", "pclk", "x8k" and "x11k".
	"i2sclk": clock which feeds the internal clock generator
	"pclk": clock which feeds the peripheral bus interface
	"x8k": I2S parent clock for sampling rates multiple of 8kHz.
	"x11k": I2S parent clock for sampling rates multiple of 11.025kHz.
  - dmas: DMA specifiers for tx and rx dma.
    See Documentation/devicetree/bindings/dma/stm32-dma.txt.
  - dma-names: Identifier for each DMA request line. Must be "tx" and "rx".
  - pinctrl-names: should contain only value "default"
  - pinctrl-0: see Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.txt

Optional properties:
  - resets: Reference to a reset controller asserting the reset controller

The device node should contain one 'port' child node with one child 'endpoint'
node, according to the bindings defined in Documentation/devicetree/bindings/
graph.txt.

Example:
sound_card {
	compatible = "audio-graph-card";
	dais = <&i2s2_port>;
};

i2s2: audio-controller@40003800 {
	compatible = "st,stm32h7-i2s";
	reg = <0x40003800 0x400>;
	interrupts = <36>;
	clocks = <&rcc PCLK1>, <&rcc SPI2_CK>, <&rcc PLL1_Q>, <&rcc PLL2_P>;
	clock-names = "pclk", "i2sclk",  "x8k", "x11k";
	dmas = <&dmamux2 2 39 0x400 0x1>,
           <&dmamux2 3 40 0x400 0x1>;
	dma-names = "rx", "tx";
	pinctrl-names = "default";
	pinctrl-0 = <&pinctrl_i2s2>;

	i2s2_port: port@0 {
		cpu_endpoint: endpoint {
			remote-endpoint = <&codec_endpoint>;
			format = "i2s";
		};
	};
};

audio-codec {
	codec_port: port@0 {
		codec_endpoint: endpoint {
			remote-endpoint = <&cpu_endpoint>;
		};
	};
};