drivers/misc/mediatek/gpu/gpu_rgx/m1.9ED4917962/hwdefs/km/configs/rgxconfig_km_8.V.2.39.h

/*************************************************************************/ /*!
@Title          RGX Config BVNC 8.V.2.39
@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
@License        Dual MIT/GPLv2

The contents of this file are subject to the MIT license as set out below.

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EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
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*/ /**************************************************************************/

#ifndef _RGXCONFIG_KM_8_V_2_39_H_
#define _RGXCONFIG_KM_8_V_2_39_H_

/***** Automatically generated file (15/09/2017 07:00:44): Do not edit manually ********************/
/***** Timestamp:  (15/09/2017 07:00:44)************************************************************/

#define RGX_BNC_KM_B 8
#define RGX_BNC_KM_N 2
#define RGX_BNC_KM_C 39

/******************************************************************************
 * DDK Defines
 *****************************************************************************/
#define RGX_FEATURE_AXI_ACELITE 
#define RGX_FEATURE_PHYS_BUS_WIDTH (40)
#define RGX_FEATURE_VIRTUAL_ADDRESS_SPACE_BITS (40)
#define RGX_FEATURE_PERFBUS 
#define RGX_FEATURE_GS_RTA_SUPPORT 
#define RGX_FEATURE_COMPUTE 
#define RGX_FEATURE_COMPUTE_MORTON_CAPABLE 
#define RGX_FEATURE_COMPUTE_OVERLAP 
#define RGX_FEATURE_TPU_FILTERING_MODE_CONTROL 
#define RGX_FEATURE_TPU_CEM_DATAMASTER_GLOBAL_REGISTERS 
#define RGX_FEATURE_SCALABLE_VDM_GPP 
#define RGX_FEATURE_VDM_DRAWINDIRECT 
#define RGX_FEATURE_SLC_VIVT 
#define RGX_FEATURE_VDM_OBJECT_LEVEL_LLS 
#define RGX_FEATURE_PDS_PER_DUST 
#define RGX_FEATURE_META (LTP218)
#define RGX_FEATURE_COMPUTE_OVERLAP_WITH_BARRIERS 
#define RGX_FEATURE_TESSELLATION 
#define RGX_FEATURE_TPU_DM_GLOBAL_REGISTERS 
#define RGX_FEATURE_PDS_TEMPSIZE8 
#define RGX_FEATURE_META_DMA 
#define RGX_FEATURE_META_DMA_CHANNEL_COUNT (4)
#define RGX_FEATURE_META_COREMEM_BANKS (8)
#define RGX_FEATURE_META_COREMEM_SIZE (64)
#define RGX_FEATURE_FBCDC_ARCHITECTURE (3)
#define RGX_FEATURE_FBCDC_ALGORITHM (2)
#define RGX_FEATURE_SLC_CACHE_LINE_SIZE_BITS (512)
#define RGX_FEATURE_NUM_CLUSTERS (2)
#define RGX_FEATURE_NUM_ISP_IPP_PIPES (4)
#define RGX_FEATURE_SLC_SIZE_IN_KILOBYTES (128)
#define RGX_FEATURE_SLC_BANKS (2)
#define RGX_FEATURE_SCALABLE_TE_ARCH (1)
#define RGX_FEATURE_SCALABLE_VCE (1)
#define RGX_FEATURE_GPU_VIRTUALISATION 
#define RGX_FEATURE_S7_CACHE_HIERARCHY 
#define RGX_FEATURE_S7_TOP_INFRASTRUCTURE 
#define RGX_FEATURE_CLUSTER_GROUPING 


#endif /* _RGXCONFIG_8_V_2_39_H_ */