enable coral camera
Change-Id: Ide7b9c8ee32226eb230ce2c53d69887b49d8ac51
diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
index 484d117..4aba1c9 100644
--- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
@@ -492,9 +492,11 @@
mipicsi: mipicsi@15008000 {
compatible = "mediatek,mt8167s-mipicsi-common", "syscon"; //?
- reg = <0 15008000 0 0x10>;
+ reg = <0 0x15008000 0 0x10>;
reg-names = "seninf_top";
clocks =
+ <&topckgen CLK_TOP_UNIVPLL_D4>,
+ <&topckgen CLK_TOP_SMI_MM_SEL>,
<&topckgen CLK_TOP_CAMTG_MM_SEL>,
<&topckgen CLK_TOP_USB_PHY48M>,
<&topckgen CLK_TOP_UNIVPLL_D6>,
@@ -510,6 +512,8 @@
<&topckgen CLK_TOP_MFG_MM>,
<&mmsys CLK_MM_CAM_MDP>;
clock-names =
+ "TOP_UNIVPLL_D4",
+ "TOP_SMI_MM_SEL",
"top_camtg_sel",
"TOP_CAM_TG_48M", /* 48M */
"TOP_CAM_TG_208M", /* 208M, divided in setTgPhase */
@@ -524,6 +528,8 @@
"mipi_dbg",
"mfg_mm",
"cam_mdp";
+ assigned-clocks = <&topckgen CLK_TOP_SMI_MM_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D4>;
};
mipicsi0: mipicsi@10011800 {
@@ -536,12 +542,10 @@
mediatek,seninf_mux_camsv = <&seninf1_mux_camsv0>;
reg = <0 0x10011800 0 0x60>, // (ana)
<0 0x15008100 0 0x4>, // (seninf_ctrl)
- <0 0x15008300 0 0x100>, // (seninf)
- <0 0x15008000 0 0x10>; // (seninf_top)
+ <0 0x15008300 0 0x100>; // (seninf)
reg-names = "mipi_rx_config",
"seninf",
- "ncsi2",
- "seninf_top";
+ "ncsi2";
mediatek,mipicsiid = <0>;
status="okay";
};
