| #ifndef __ASM_MPSPEC_H | |
| #define __ASM_MPSPEC_H | |
| /* | |
| * Structure definitions for SMP machines following the | |
| * Intel Multiprocessing Specification 1.1 and 1.4. | |
| */ | |
| /* | |
| * This tag identifies where the SMP configuration | |
| * information is. | |
| */ | |
| #define SMP_MAGIC_IDENT (('_'<<24)|('P'<<16)|('M'<<8)|'_') | |
| /* | |
| * A maximum of 255 APICs with the current APIC ID architecture. | |
| */ | |
| #define MAX_APICS 255 | |
| struct intel_mp_floating | |
| { | |
| char mpf_signature[4]; /* "_MP_" */ | |
| unsigned int mpf_physptr; /* Configuration table address */ | |
| unsigned char mpf_length; /* Our length (paragraphs) */ | |
| unsigned char mpf_specification;/* Specification version */ | |
| unsigned char mpf_checksum; /* Checksum (makes sum 0) */ | |
| unsigned char mpf_feature1; /* Standard or configuration ? */ | |
| unsigned char mpf_feature2; /* Bit7 set for IMCR|PIC */ | |
| unsigned char mpf_feature3; /* Unused (0) */ | |
| unsigned char mpf_feature4; /* Unused (0) */ | |
| unsigned char mpf_feature5; /* Unused (0) */ | |
| }; | |
| struct mp_config_table | |
| { | |
| char mpc_signature[4]; | |
| #define MPC_SIGNATURE "PCMP" | |
| unsigned short mpc_length; /* Size of table */ | |
| char mpc_spec; /* 0x01 */ | |
| char mpc_checksum; | |
| char mpc_oem[8]; | |
| char mpc_productid[12]; | |
| unsigned int mpc_oemptr; /* 0 if not present */ | |
| unsigned short mpc_oemsize; /* 0 if not present */ | |
| unsigned short mpc_oemcount; | |
| unsigned int mpc_lapic; /* APIC address */ | |
| unsigned int reserved; | |
| }; | |
| /* Followed by entries */ | |
| #define MP_PROCESSOR 0 | |
| #define MP_BUS 1 | |
| #define MP_IOAPIC 2 | |
| #define MP_INTSRC 3 | |
| #define MP_LINTSRC 4 | |
| struct mpc_config_processor | |
| { | |
| unsigned char mpc_type; | |
| unsigned char mpc_apicid; /* Local APIC number */ | |
| unsigned char mpc_apicver; /* Its versions */ | |
| unsigned char mpc_cpuflag; | |
| #define CPU_ENABLED 1 /* Processor is available */ | |
| #define CPU_BOOTPROCESSOR 2 /* Processor is the BP */ | |
| unsigned int mpc_cpufeature; | |
| #define CPU_STEPPING_MASK 0x0F | |
| #define CPU_MODEL_MASK 0xF0 | |
| #define CPU_FAMILY_MASK 0xF00 | |
| unsigned int mpc_featureflag; /* CPUID feature value */ | |
| unsigned int mpc_reserved[2]; | |
| }; | |
| struct mpc_config_bus | |
| { | |
| unsigned char mpc_type; | |
| unsigned char mpc_busid; | |
| unsigned char mpc_bustype[6]; | |
| }; | |
| /* List of Bus Type string values, Intel MP Spec. */ | |
| #define BUSTYPE_EISA "EISA" | |
| #define BUSTYPE_ISA "ISA" | |
| #define BUSTYPE_INTERN "INTERN" /* Internal BUS */ | |
| #define BUSTYPE_MCA "MCA" | |
| #define BUSTYPE_VL "VL" /* Local bus */ | |
| #define BUSTYPE_PCI "PCI" | |
| #define BUSTYPE_PCMCIA "PCMCIA" | |
| #define BUSTYPE_CBUS "CBUS" | |
| #define BUSTYPE_CBUSII "CBUSII" | |
| #define BUSTYPE_FUTURE "FUTURE" | |
| #define BUSTYPE_MBI "MBI" | |
| #define BUSTYPE_MBII "MBII" | |
| #define BUSTYPE_MPI "MPI" | |
| #define BUSTYPE_MPSA "MPSA" | |
| #define BUSTYPE_NUBUS "NUBUS" | |
| #define BUSTYPE_TC "TC" | |
| #define BUSTYPE_VME "VME" | |
| #define BUSTYPE_XPRESS "XPRESS" | |
| struct mpc_config_ioapic | |
| { | |
| unsigned char mpc_type; | |
| unsigned char mpc_apicid; | |
| unsigned char mpc_apicver; | |
| unsigned char mpc_flags; | |
| #define MPC_APIC_USABLE 0x01 | |
| unsigned int mpc_apicaddr; | |
| }; | |
| struct mpc_config_intsrc | |
| { | |
| unsigned char mpc_type; | |
| unsigned char mpc_irqtype; | |
| unsigned short mpc_irqflag; | |
| unsigned char mpc_srcbus; | |
| unsigned char mpc_srcbusirq; | |
| unsigned char mpc_dstapic; | |
| unsigned char mpc_dstirq; | |
| }; | |
| enum mp_irq_source_types { | |
| mp_INT = 0, | |
| mp_NMI = 1, | |
| mp_SMI = 2, | |
| mp_ExtINT = 3 | |
| }; | |
| #define MP_IRQDIR_DEFAULT 0 | |
| #define MP_IRQDIR_HIGH 1 | |
| #define MP_IRQDIR_LOW 3 | |
| struct mpc_config_lintsrc | |
| { | |
| unsigned char mpc_type; | |
| unsigned char mpc_irqtype; | |
| unsigned short mpc_irqflag; | |
| unsigned char mpc_srcbusid; | |
| unsigned char mpc_srcbusirq; | |
| unsigned char mpc_destapic; | |
| #define MP_APIC_ALL 0xFF | |
| unsigned char mpc_destapiclint; | |
| }; | |
| /* | |
| * Default configurations | |
| * | |
| * 1 2 CPU ISA 82489DX | |
| * 2 2 CPU EISA 82489DX neither IRQ 0 timer nor IRQ 13 DMA chaining | |
| * 3 2 CPU EISA 82489DX | |
| * 4 2 CPU MCA 82489DX | |
| * 5 2 CPU ISA+PCI | |
| * 6 2 CPU EISA+PCI | |
| * 7 2 CPU MCA+PCI | |
| */ | |
| #define MAX_MP_BUSSES 256 | |
| /* Each PCI slot may be a combo card with its own bus. 4 IRQ pins per slot. */ | |
| #define MAX_IRQ_SOURCES (MAX_MP_BUSSES * 4) | |
| extern DECLARE_BITMAP(mp_bus_not_pci, MAX_MP_BUSSES); | |
| extern int mp_bus_id_to_pci_bus [MAX_MP_BUSSES]; | |
| extern unsigned int boot_cpu_physical_apicid; | |
| extern int smp_found_config; | |
| extern void find_smp_config (void); | |
| extern void get_smp_config (void); | |
| extern int nr_ioapics; | |
| extern unsigned char apic_version [MAX_APICS]; | |
| extern int mp_irq_entries; | |
| extern struct mpc_config_intsrc mp_irqs [MAX_IRQ_SOURCES]; | |
| extern int mpc_default_type; | |
| extern unsigned long mp_lapic_addr; | |
| #ifdef CONFIG_ACPI | |
| extern void mp_register_lapic (u8 id, u8 enabled); | |
| extern void mp_register_lapic_address (u64 address); | |
| extern void mp_register_ioapic (u8 id, u32 address, u32 gsi_base); | |
| extern void mp_override_legacy_irq (u8 bus_irq, u8 polarity, u8 trigger, u32 gsi); | |
| extern void mp_config_acpi_legacy_irqs (void); | |
| extern int mp_register_gsi (u32 gsi, int triggering, int polarity); | |
| #endif | |
| extern int using_apic_timer; | |
| #define PHYSID_ARRAY_SIZE BITS_TO_LONGS(MAX_APICS) | |
| struct physid_mask | |
| { | |
| unsigned long mask[PHYSID_ARRAY_SIZE]; | |
| }; | |
| typedef struct physid_mask physid_mask_t; | |
| #define physid_set(physid, map) set_bit(physid, (map).mask) | |
| #define physid_clear(physid, map) clear_bit(physid, (map).mask) | |
| #define physid_isset(physid, map) test_bit(physid, (map).mask) | |
| #define physid_test_and_set(physid, map) test_and_set_bit(physid, (map).mask) | |
| #define physids_and(dst, src1, src2) bitmap_and((dst).mask, (src1).mask, (src2).mask, MAX_APICS) | |
| #define physids_or(dst, src1, src2) bitmap_or((dst).mask, (src1).mask, (src2).mask, MAX_APICS) | |
| #define physids_clear(map) bitmap_zero((map).mask, MAX_APICS) | |
| #define physids_complement(dst, src) bitmap_complement((dst).mask, (src).mask, MAX_APICS) | |
| #define physids_empty(map) bitmap_empty((map).mask, MAX_APICS) | |
| #define physids_equal(map1, map2) bitmap_equal((map1).mask, (map2).mask, MAX_APICS) | |
| #define physids_weight(map) bitmap_weight((map).mask, MAX_APICS) | |
| #define physids_shift_right(d, s, n) bitmap_shift_right((d).mask, (s).mask, n, MAX_APICS) | |
| #define physids_shift_left(d, s, n) bitmap_shift_left((d).mask, (s).mask, n, MAX_APICS) | |
| #define physids_coerce(map) ((map).mask[0]) | |
| #define physids_promote(physids) \ | |
| ({ \ | |
| physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | |
| __physid_mask.mask[0] = physids; \ | |
| __physid_mask; \ | |
| }) | |
| #define physid_mask_of_physid(physid) \ | |
| ({ \ | |
| physid_mask_t __physid_mask = PHYSID_MASK_NONE; \ | |
| physid_set(physid, __physid_mask); \ | |
| __physid_mask; \ | |
| }) | |
| #define PHYSID_MASK_ALL { {[0 ... PHYSID_ARRAY_SIZE-1] = ~0UL} } | |
| #define PHYSID_MASK_NONE { {[0 ... PHYSID_ARRAY_SIZE-1] = 0UL} } | |
| extern physid_mask_t phys_cpu_present_map; | |
| #endif | |