drivers/misc/mediatek/gpu/gpu_rgx/m1.9ED4917962/services/include/info_page_defs.h

/*************************************************************************/ /*!
@File
@Title          Kernel/User mode general purpose shared memory.
@Copyright      Copyright (c) Imagination Technologies Ltd. All Rights Reserved
@Description    General purpose memory shared between kernel driver and user
                mode.
@License        Dual MIT/GPLv2

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*/ /**************************************************************************/

#ifndef _INFO_PAGE_DEFS_H_
#define _INFO_PAGE_DEFS_H_

/* The CacheOp information page entries, each entry is of size(IMG_UINT32) on
 * both 32/64-bit CPU */

#define CACHEOP_INFO_SIZE         sizeof(IMG_UINT32)

/* The CacheOp information page entries, each entry is of size(IMG_UINT32)
 * on both 32/64-bit CPU */
#define CACHEOP_INFO_GFSEQNUM0    0x00 /*!< Current global flush sequence number */
#define CACHEOP_INFO_GFSEQNUM1    0x01 /*!< Validity global flush sequence number */
#define CACHEOP_INFO_UMRBFONLY    0x02 /*!< Use UM flush only (i.e no KM GF) */
#define CACHEOP_INFO_UMKMTHRESHLD 0x03 /*!< UM=>KM routing threshold in bytes */
#define CACHEOP_INFO_KMGFTHRESHLD 0x04 /*!< KM/GF threshold in bytes */
#define CACHEOP_INFO_KMDFTHRESHLD 0x05 /*!< KM/DF threshold in bytes */
#define CACHEOP_INFO_LINESIZE     0x06 /*!< CPU d-cache line size */
#define CACHEOP_INFO_PGSIZE       0x07 /*!< CPU MMU page size */

/* HWPerf information page entries */

#define HWPERF_INFO_IDX_START      0x08
#define HWPERF_FILTER_SERVICES_IDX (HWPERF_INFO_IDX_START + 0)
#define HWPERF_FILTER_EGL_IDX      (HWPERF_INFO_IDX_START + 1)
#define HWPERF_FILTER_OPENGLES_IDX (HWPERF_INFO_IDX_START + 2)
#define HWPERF_FILTER_OPENCL_IDX   (HWPERF_INFO_IDX_START + 3)
#define HWPERF_FILTER_OPENRL_IDX   (HWPERF_INFO_IDX_START + 4)
#define HWPERF_INFO_IDX_END        (HWPERF_INFO_IDX_START + 5)

#endif /* _INFO_PAGE_DEFS_H_ */