Documentation/devicetree/bindings/mips/mscc.txt

* Microsemi MIPS CPUs

Boards with a SoC of the Microsemi MIPS family shall have the following
properties:

Required properties:
- compatible: "mscc,ocelot"


* Other peripherals:

o CPU chip regs:

The SoC has a few registers (DEVCPU_GCB:CHIP_REGS) handling miscellaneous
functionalities: chip ID, general purpose register for software use, reset
controller, hardware status and configuration, efuses.

Required properties:
- compatible: Should be "mscc,ocelot-chip-regs", "simple-mfd", "syscon"
- reg : Should contain registers location and length

Example:
	syscon@71070000 {
		compatible = "mscc,ocelot-chip-regs", "simple-mfd", "syscon";
		reg = <0x71070000 0x1c>;
	};


o CPU system control:

The SoC has a few registers (ICPU_CFG:CPU_SYSTEM_CTRL) handling configuration of
the CPU: 8 general purpose registers, reset control, CPU en/disabling, CPU
endianness, CPU bus control, CPU status.

Required properties:
- compatible: Should be "mscc,ocelot-cpu-syscon", "syscon"
- reg : Should contain registers location and length

Example:
	syscon@70000000 {
		compatible = "mscc,ocelot-cpu-syscon", "syscon";
		reg = <0x70000000 0x2c>;
	};