Merge remote-tracking branch 'origin/baylibre-4.19' into master
Change-Id: Ida76bfb5533f4069182a776f9213f368bbc42513
diff --git a/arch/arm64/boot/dts/mediatek/mt8167-coral.dts b/arch/arm64/boot/dts/mediatek/mt8167-coral.dts
index cd48899..eb5f8df 100644
--- a/arch/arm64/boot/dts/mediatek/mt8167-coral.dts
+++ b/arch/arm64/boot/dts/mediatek/mt8167-coral.dts
@@ -40,7 +40,6 @@
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&pio 17 GPIO_ACTIVE_LOW>;
- regulator-always-on;
};
ga1600_pmic: ga1600_pmic {
@@ -85,6 +84,98 @@
pinctrl-0 = <&aud_pins_default>;
mediatek,jack-detect-gpio = <&pio 40 0>;
};
+
+ auxadc: adc@11003000 {
+ compatible = "mediatek,mt2712-auxadc";
+ reg = <0 0x11003000 0 0x1000>;
+ clocks = <&topckgen CLK_TOP_AUX_ADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "okay";
+ };
+
+ thermal: thermal@1100d000 {
+ #thermal-sensor-cells = <0>;
+ compatible = "mediatek,mt8516-thermal";
+ reg = <0 0x1100d000 0 0x1000>;
+ interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_LOW>;
+ clocks = <&topckgen CLK_TOP_THEM>, <&topckgen CLK_TOP_AUX_ADC>;
+ clock-names = "therm", "auxadc";
+ mediatek,auxadc = <&auxadc>;
+ mediatek,apmixedsys = <&apmixedsys>;
+ nvmem-cells = <&thermal_calibration>;
+ nvmem-cell-names = "calibration-data";
+ };
+
+ efuse: efuse@10009000 {
+ compatible = "mediatek,mt8173-efuse";
+ reg = <0 0x10009000 0 0x1000>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+ thermal_calibration: calib@180 {
+ reg = <0x180 0xc>;
+ };
+};
+
+ thermal-zones {
+ cpu_thermal: cpu_thermal {
+ polling-delay-passive = <1000>; /* ms */
+ polling-delay = <1000>; /* ms */
+
+ thermal-sensors = <&thermal>;
+
+ trips {
+ cpu_alert0: trip0 {
+ temperature = <85000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_alert1: trip1 {
+ temperature = <90000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_alert2: trip2 {
+ temperature = <95000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_alert3: trip3 {
+ temperature = <100000>;
+ hysteresis = <2000>;
+ type = "passive";
+ };
+
+ cpu_crit0: trip4 {
+ temperature = <105000>;
+ hysteresis = <2000>;
+ type = "critical";
+ };
+ };
+
+ cooling-maps {
+ map0 {
+ trip = <&cpu_alert0>;
+ cooling-device = <&cpu0 0 4>;
+ };
+ map1 {
+ trip = <&cpu_alert1>;
+ cooling-device = <&cpu0 0 3>;
+ };
+ map2 {
+ trip = <&cpu_alert2>;
+ cooling-device = <&cpu0 0 2>;
+ };
+ map3 {
+ trip = <&cpu_alert3>;
+ cooling-device = <&cpu0 0 1>;
+ };
+ };
+ };
+ };
};
&afe {
@@ -116,6 +207,7 @@
};
&mt6392_vcamaf_reg {
+ regulator-min-microvolt = <3300000>;
regulator-always-on;
};
@@ -124,6 +216,19 @@
regulator-always-on;
};
+&mt6392_vgp2_reg {
+ regulator-min-microvolt = <3300000>;
+ regulator-always-on;
+};
+
+&mt6392_vmch_reg {
+ regulator-min-microvolt = <3300000>;
+};
+
+&mt6392_vmc_reg {
+ regulator-min-microvolt = <3300000>;
+};
+
&uart0 {
status = "okay";
};
@@ -531,6 +636,7 @@
status = "okay";
dr_mode = "otg";
usb-role-switch;
+ vbus-supply = <&usb0_vbus>;
port {
usb0_role_switch: endpoint {
@@ -547,7 +653,6 @@
usb_con: connector {
compatible = "usb-c-connector";
label = "USB-C";
- vbus-supply = <&usb0_vbus>;
};
ports {
diff --git a/arch/arm64/boot/dts/mediatek/mt8516.dtsi b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
index 1aa0152..aab0b64 100644
--- a/arch/arm64/boot/dts/mediatek/mt8516.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8516.dtsi
@@ -58,6 +58,7 @@
<&topckgen CLK_TOP_MAINPLL_D2>,
<&apmixedsys CLK_APMIXED_ARMPLL>;
clock-names = "cpu", "intermediate", "armpll";
+ #cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
@@ -72,6 +73,7 @@
<&topckgen CLK_TOP_MAINPLL_D2>,
<&apmixedsys CLK_APMIXED_ARMPLL>;
clock-names = "cpu", "intermediate", "armpll";
+ #cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
@@ -86,6 +88,7 @@
<&topckgen CLK_TOP_MAINPLL_D2>,
<&apmixedsys CLK_APMIXED_ARMPLL>;
clock-names = "cpu", "intermediate", "armpll";
+ #cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
@@ -100,6 +103,7 @@
<&topckgen CLK_TOP_MAINPLL_D2>,
<&apmixedsys CLK_APMIXED_ARMPLL>;
clock-names = "cpu", "intermediate", "armpll";
+ #cooling-cells = <2>;
operating-points-v2 = <&cluster0_opp>;
};
diff --git a/drivers/gpu/drm/mediatek/mtk_cec.c b/drivers/gpu/drm/mediatek/mtk_cec.c
index 5ce84d0..491084b 100644
--- a/drivers/gpu/drm/mediatek/mtk_cec.c
+++ b/drivers/gpu/drm/mediatek/mtk_cec.c
@@ -178,7 +178,7 @@
hpd = mtk_cec_hpd_high(dev);
if (cec->hpd != hpd) {
- dev_dbg(dev, "hotplug event! cur hpd = %d, hpd = %d\n",
+ dev_info(dev, "hotplug event! cur hpd = %d, hpd = %d\n",
cec->hpd, hpd);
cec->hpd = hpd;
mtk_cec_hpd_event(cec, hpd);
diff --git a/drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c b/drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c
index f1403d6..92ed530 100644
--- a/drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c
+++ b/drivers/media/platform/mtk-mdp/mtk_mdp_m2m.c
@@ -405,7 +405,8 @@
int sizeimage = (pix_mp->width * pix_mp->height *
fmt->depth[i]) / 8;
- pix_mp->plane_fmt[i].bytesperline = bpl;
+ if (pix_mp->plane_fmt[i].bytesperline < bpl)
+ pix_mp->plane_fmt[i].bytesperline = bpl;
if (pix_mp->plane_fmt[i].sizeimage < sizeimage)
pix_mp->plane_fmt[i].sizeimage = sizeimage;
memset(pix_mp->plane_fmt[i].reserved, 0,
diff --git a/drivers/media/platform/mtk-mdp/mtk_mdp_vpu.c b/drivers/media/platform/mtk-mdp/mtk_mdp_vpu.c
index a3e7b55..317ea67 100644
--- a/drivers/media/platform/mtk-mdp/mtk_mdp_vpu.c
+++ b/drivers/media/platform/mtk-mdp/mtk_mdp_vpu.c
@@ -168,9 +168,17 @@
request_size = cmdq->cmd_size;
if (unlikely(request_size > handle->buf_size)) {
request_size = roundup(request_size, PAGE_SIZE);
- err = -1;//cmdq_pkt_realloc_cmd_buffer(handle, request_size);
- if (err < 0)
+
+ handle = cmdq_pkt_create(ctx->mdp_dev->cmdq_client, request_size);
+ if (IS_ERR(handle)) {
+ err = PTR_ERR(handle);
+ dev_err(&ctx->mdp_dev->pdev->dev,
+ "Create cmdq ptk failed %d\n", err);
return err;
+ }
+
+ cmdq_pkt_destroy(ctx->cmdq_handle);
+ ctx->cmdq_handle = handle;
}
memcpy(handle->va_base,
diff --git a/drivers/misc/mediatek/usb11/musbfsh_host.c b/drivers/misc/mediatek/usb11/musbfsh_host.c
index a1bc443..4a8fe88 100644
--- a/drivers/misc/mediatek/usb11/musbfsh_host.c
+++ b/drivers/misc/mediatek/usb11/musbfsh_host.c
@@ -1421,7 +1421,7 @@
/* with CPPI, DMA sometimes triggers "extra" irqs */
if (!urb) {
- WARNING("extra TX%d ready, csr %04x\n", epnum, tx_csr);
+ INFO("extra TX%d ready, csr %04x\n", epnum, tx_csr);
return;
}
@@ -1490,7 +1490,7 @@
/* second cppi case */
if (dma_channel_status(dma) == MUSBFSH_DMA_STATUS_BUSY) {
- WARNING("extra TX%d ready, csr %04x\n", epnum, tx_csr);
+ INFO("extra TX%d ready, csr %04x\n", epnum, tx_csr);
return;
}
@@ -2531,7 +2531,7 @@
dma = is_in ? ep->rx_channel : ep->tx_channel;
if (dma) {
stat = ep->musbfsh->dma_controller->channel_abort(dma);
- WARNING("abort %cX%d DMA for urb %p --> %d\n",
+ INFO("abort %cX%d DMA for urb %p --> %d\n",
is_in ? 'R' : 'T', ep->epnum, urb, stat);
urb->actual_length += dma->actual_len;
dma->actual_len = 0L;
diff --git a/drivers/thermal/mtk_thermal.c b/drivers/thermal/mtk_thermal.c
index 248a236..f2d2a98 100644
--- a/drivers/thermal/mtk_thermal.c
+++ b/drivers/thermal/mtk_thermal.c
@@ -232,6 +232,12 @@
/* The calibration coefficient of sensor */
#define MT8183_CALIBRATION 153
+#define MT8516_TEMP_AUXADC_CHANNEL (11)
+#define MT8516_NUM_CONTROLLER (1)
+#define MT8516_NUM_SENSORS (3)
+#define MT8516_NUM_SENSORS_PER_ZONE (3)
+#define MT8516_CALIBRATION (165)
+
struct mtk_thermal;
struct mtk_thermal_zone {
@@ -375,6 +381,21 @@
static const int mt7622_vts_index[MT7622_NUM_SENSORS] = { VTS1 };
static const int mt7622_tc_offset[MT7622_NUM_CONTROLLER] = { 0x0, };
+/* MT8516 thermal sensor data */
+static const int mt8516_bank_data[MT8516_NUM_SENSORS] = {
+ 0, 1, 2
+};
+static const int mt8516_msr[MT8516_NUM_SENSORS_PER_ZONE] = {
+ TEMP_MSR0, TEMP_MSR1, TEMP_MSR2
+};
+static const int mt8516_adcpnp[MT8516_NUM_SENSORS_PER_ZONE] = {
+ TEMP_ADCPNP0, TEMP_ADCPNP1, TEMP_ADCPNP2
+};
+static const int mt8516_mux_values[MT8516_NUM_SENSORS] = { 0, 1, 16 };
+static const int mt8516_tc_offset[MT8516_NUM_CONTROLLER] = { 0x0, };
+static const int mt8516_vts_index[MT8516_NUM_SENSORS] = {
+ VTS1, VTS2, VTS3
+};
/*
* The MT8173 thermal controller has four banks. Each bank can read up to
* four temperature sensors simultaneously. The MT8173 has a total of 5
@@ -447,6 +468,27 @@
.sensor_mux_values = mt2701_mux_values,
};
+/* MT8516 has one bank, and three sensors. */
+static const struct mtk_thermal_data mt8516_thermal_data = {
+ .auxadc_channel = MT8516_TEMP_AUXADC_CHANNEL,
+ .num_banks = 1,
+ .num_sensors = MT8516_NUM_SENSORS,
+ .vts_index = mt8516_vts_index,
+ .cali_val = MT8516_CALIBRATION,
+ .num_controller = 1,
+ .controller_offset = mt8516_tc_offset,
+ .need_switch_bank = true,
+ .bank_data = {
+ {
+ .num_sensors = 3,
+ .sensors = mt8516_bank_data,
+ },
+ },
+ .msr = mt8516_msr,
+ .adcpnp = mt8516_adcpnp,
+ .sensor_mux_values = mt8516_mux_values,
+};
+
/*
* The MT2712 thermal controller has one bank, which can read up to
* four temperature sensors simultaneously. The MT2712 has a total of 4
@@ -843,6 +885,15 @@
goto out;
}
+ // MT8516 stores the 3 words of calibration data
+ // at indices 0x184, 0x180, 0x188.
+ // The nvmem APIs give us the values in order that
+ // they are laid out, so we need to swap the first two
+ // words.
+ if (mt->conf == &mt8516_thermal_data) {
+ swap(buf[0], buf[1]);
+ }
+
if (buf[0] & CALIB_BUF0_VALID) {
mt->adc_ge = CALIB_BUF1_ADC_GE(buf[1]);
@@ -907,7 +958,12 @@
{
.compatible = "mediatek,mt8183-thermal",
.data = (void *)&mt8183_thermal_data,
- }, {
+ },
+ {
+ .compatible = "mediatek,mt8516-thermal",
+ .data = (void *)&mt8516_thermal_data,
+ },
+ {
},
};
MODULE_DEVICE_TABLE(of, mtk_thermal_of_match);
@@ -977,9 +1033,11 @@
return -EINVAL;
}
- ret = device_reset(&pdev->dev);
- if (ret)
- return ret;
+ if (mt->conf != &mt8516_thermal_data) {
+ ret = device_reset(&pdev->dev);
+ if (ret)
+ return ret;
+ }
ret = clk_prepare_enable(mt->clk_auxadc);
if (ret) {
@@ -1012,8 +1070,11 @@
tz, (i == 0) ?
&mtk_thermal_ops : &mtk_thermal_sensor_ops);
- if (IS_ERR(tzdev)) {
- if (IS_ERR(tzdev) != -EACCES) {
+ // Thermal framework seems to only allow registering one sensor per zone.
+ // So if we're on any index but 1, don't error out!
+ // See drivers/thermal/of-thermal.c:835 for details.
+ if (IS_ERR(tzdev) && i == 0) {
+ if (PTR_ERR(tzdev) != -EACCES) {
ret = PTR_ERR(tzdev);
goto err_disable_clk_peri_therm;
}
diff --git a/drivers/usb/musb/mediatek.c b/drivers/usb/musb/mediatek.c
index e218dc0..0582041 100644
--- a/drivers/usb/musb/mediatek.c
+++ b/drivers/usb/musb/mediatek.c
@@ -52,6 +52,7 @@
struct clk *univpll;
enum usb_role role;
struct usb_role_switch *role_sw;
+ struct regulator *vbus_supply;
};
static int mtk_musb_clks_get(struct mtk_glue *glue)
@@ -124,10 +125,14 @@
struct musb *musb = glue->musb;
u8 devctl = readb(musb->mregs + MUSB_DEVCTL);
enum usb_role new_role;
+ int ret;
if (role == glue->role)
return 0;
+ if (glue->vbus_supply && regulator_is_enabled(glue->vbus_supply))
+ regulator_disable(glue->vbus_supply);
+
switch (role) {
case USB_ROLE_HOST:
musb->xceiv->otg->state = OTG_STATE_A_WAIT_VRISE;
@@ -138,6 +143,14 @@
devctl |= MUSB_DEVCTL_SESSION;
musb_writeb(musb->mregs, MUSB_DEVCTL, devctl);
+
+ if (glue->vbus_supply) {
+ ret = regulator_enable(glue->vbus_supply);
+ if (ret)
+ dev_warn(glue->dev,
+ "Failed to enable VBUS: %d\n", ret);
+ }
+
MUSB_HST_MODE(musb);
break;
case USB_ROLE_DEVICE:
@@ -526,6 +539,8 @@
goto err_unregister_usb_phy;
}
+ glue->vbus_supply = devm_regulator_get_optional(dev, "vbus");
+
platform_set_drvdata(pdev, glue);
pm_runtime_enable(dev);
pm_runtime_get_sync(dev);
diff --git a/drivers/usb/typec/mt6392.c b/drivers/usb/typec/mt6392.c
index a8fa592..8069441 100644
--- a/drivers/usb/typec/mt6392.c
+++ b/drivers/usb/typec/mt6392.c
@@ -141,7 +141,7 @@
regmap_update_bits(typec->regmap, typec->base_addr + TYPEC_CTRL,
PORT_SUPPORT_ROLE_MASK, PORT_SUPPORT_ROLE_DRP);
regmap_update_bits(typec->regmap, typec->base_addr + TYPEC_CC_SW_CTRL,
- STATE_ENTER_UNATTACHED_SRC, STATE_ENTER_UNATTACHED_SRC);
+ STATE_ENTER_UNATTACHED_SINK, STATE_ENTER_UNATTACHED_SINK);
ret = devm_request_threaded_irq(typec->dev, typec->irq, NULL,
mtk_typec_irq_handler_thread,
