| // SPDX-License-Identifier: GPL-2.0 |
| #include <dt-bindings/clock/tegra186-clock.h> |
| #include <dt-bindings/gpio/tegra186-gpio.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/mailbox/tegra186-hsp.h> |
| #include <dt-bindings/memory/tegra186-mc.h> |
| #include <dt-bindings/power/tegra186-powergate.h> |
| #include <dt-bindings/reset/tegra186-reset.h> |
| #include <dt-bindings/thermal/tegra186-bpmp-thermal.h> |
| |
| / { |
| compatible = "nvidia,tegra186"; |
| interrupt-parent = <&gic>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| misc@100000 { |
| compatible = "nvidia,tegra186-misc"; |
| reg = <0x0 0x00100000 0x0 0xf000>, |
| <0x0 0x0010f000 0x0 0x1000>; |
| }; |
| |
| gpio: gpio@2200000 { |
| compatible = "nvidia,tegra186-gpio"; |
| reg-names = "security", "gpio"; |
| reg = <0x0 0x2200000 0x0 0x10000>, |
| <0x0 0x2210000 0x0 0x10000>; |
| interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| #gpio-cells = <2>; |
| gpio-controller; |
| }; |
| |
| ethernet@2490000 { |
| compatible = "nvidia,tegra186-eqos", |
| "snps,dwc-qos-ethernet-4.10"; |
| reg = <0x0 0x02490000 0x0 0x10000>; |
| interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, /* common */ |
| <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, /* power */ |
| <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, /* rx0 */ |
| <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, /* tx0 */ |
| <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, /* rx1 */ |
| <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, /* tx1 */ |
| <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, /* rx2 */ |
| <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, /* tx2 */ |
| <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, /* rx3 */ |
| <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; /* tx3 */ |
| clocks = <&bpmp TEGRA186_CLK_AXI_CBB>, |
| <&bpmp TEGRA186_CLK_EQOS_AXI>, |
| <&bpmp TEGRA186_CLK_EQOS_RX>, |
| <&bpmp TEGRA186_CLK_EQOS_TX>, |
| <&bpmp TEGRA186_CLK_EQOS_PTP_REF>; |
| clock-names = "master_bus", "slave_bus", "rx", "tx", "ptp_ref"; |
| resets = <&bpmp TEGRA186_RESET_EQOS>; |
| reset-names = "eqos"; |
| status = "disabled"; |
| |
| snps,write-requests = <1>; |
| snps,read-requests = <3>; |
| snps,burst-map = <0x7>; |
| snps,txpbl = <32>; |
| snps,rxpbl = <8>; |
| }; |
| |
| memory-controller@2c00000 { |
| compatible = "nvidia,tegra186-mc"; |
| reg = <0x0 0x02c00000 0x0 0xb0000>; |
| status = "disabled"; |
| }; |
| |
| uarta: serial@3100000 { |
| compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x03100000 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_UARTA>; |
| clock-names = "serial"; |
| resets = <&bpmp TEGRA186_RESET_UARTA>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| uartb: serial@3110000 { |
| compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x03110000 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_UARTB>; |
| clock-names = "serial"; |
| resets = <&bpmp TEGRA186_RESET_UARTB>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| uartd: serial@3130000 { |
| compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x03130000 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_UARTD>; |
| clock-names = "serial"; |
| resets = <&bpmp TEGRA186_RESET_UARTD>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| uarte: serial@3140000 { |
| compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x03140000 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_UARTE>; |
| clock-names = "serial"; |
| resets = <&bpmp TEGRA186_RESET_UARTE>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| uartf: serial@3150000 { |
| compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x03150000 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_UARTF>; |
| clock-names = "serial"; |
| resets = <&bpmp TEGRA186_RESET_UARTF>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| gen1_i2c: i2c@3160000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x03160000 0x0 0x10000>; |
| interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp TEGRA186_CLK_I2C1>; |
| clock-names = "div-clk"; |
| resets = <&bpmp TEGRA186_RESET_I2C1>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| cam_i2c: i2c@3180000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x03180000 0x0 0x10000>; |
| interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp TEGRA186_CLK_I2C3>; |
| clock-names = "div-clk"; |
| resets = <&bpmp TEGRA186_RESET_I2C3>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| /* shares pads with dpaux1 */ |
| dp_aux_ch1_i2c: i2c@3190000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x03190000 0x0 0x10000>; |
| interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp TEGRA186_CLK_I2C4>; |
| clock-names = "div-clk"; |
| resets = <&bpmp TEGRA186_RESET_I2C4>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| /* controlled by BPMP, should not be enabled */ |
| pwr_i2c: i2c@31a0000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x031a0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp TEGRA186_CLK_I2C5>; |
| clock-names = "div-clk"; |
| resets = <&bpmp TEGRA186_RESET_I2C5>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| /* shares pads with dpaux0 */ |
| dp_aux_ch0_i2c: i2c@31b0000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x031b0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp TEGRA186_CLK_I2C6>; |
| clock-names = "div-clk"; |
| resets = <&bpmp TEGRA186_RESET_I2C6>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| gen7_i2c: i2c@31c0000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x031c0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp TEGRA186_CLK_I2C7>; |
| clock-names = "div-clk"; |
| resets = <&bpmp TEGRA186_RESET_I2C7>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| gen9_i2c: i2c@31e0000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x031e0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp TEGRA186_CLK_I2C9>; |
| clock-names = "div-clk"; |
| resets = <&bpmp TEGRA186_RESET_I2C9>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| sdmmc1: sdhci@3400000 { |
| compatible = "nvidia,tegra186-sdhci"; |
| reg = <0x0 0x03400000 0x0 0x10000>; |
| interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_SDMMC1>; |
| clock-names = "sdhci"; |
| resets = <&bpmp TEGRA186_RESET_SDMMC1>; |
| reset-names = "sdhci"; |
| status = "disabled"; |
| }; |
| |
| sdmmc2: sdhci@3420000 { |
| compatible = "nvidia,tegra186-sdhci"; |
| reg = <0x0 0x03420000 0x0 0x10000>; |
| interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_SDMMC2>; |
| clock-names = "sdhci"; |
| resets = <&bpmp TEGRA186_RESET_SDMMC2>; |
| reset-names = "sdhci"; |
| status = "disabled"; |
| }; |
| |
| sdmmc3: sdhci@3440000 { |
| compatible = "nvidia,tegra186-sdhci"; |
| reg = <0x0 0x03440000 0x0 0x10000>; |
| interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_SDMMC3>; |
| clock-names = "sdhci"; |
| resets = <&bpmp TEGRA186_RESET_SDMMC3>; |
| reset-names = "sdhci"; |
| status = "disabled"; |
| }; |
| |
| sdmmc4: sdhci@3460000 { |
| compatible = "nvidia,tegra186-sdhci"; |
| reg = <0x0 0x03460000 0x0 0x10000>; |
| interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_SDMMC4>; |
| clock-names = "sdhci"; |
| resets = <&bpmp TEGRA186_RESET_SDMMC4>; |
| reset-names = "sdhci"; |
| status = "disabled"; |
| }; |
| |
| fuse@3820000 { |
| compatible = "nvidia,tegra186-efuse"; |
| reg = <0x0 0x03820000 0x0 0x10000>; |
| clocks = <&bpmp TEGRA186_CLK_FUSE>; |
| clock-names = "fuse"; |
| }; |
| |
| gic: interrupt-controller@3881000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0x0 0x03881000 0x0 0x1000>, |
| <0x0 0x03882000 0x0 0x2000>; |
| interrupts = <GIC_PPI 9 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; |
| interrupt-parent = <&gic>; |
| }; |
| |
| hsp_top0: hsp@3c00000 { |
| compatible = "nvidia,tegra186-hsp"; |
| reg = <0x0 0x03c00000 0x0 0xa0000>; |
| interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "doorbell"; |
| #mbox-cells = <2>; |
| status = "disabled"; |
| }; |
| |
| gen2_i2c: i2c@c240000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x0c240000 0x0 0x10000>; |
| interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp TEGRA186_CLK_I2C2>; |
| clock-names = "div-clk"; |
| resets = <&bpmp TEGRA186_RESET_I2C2>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| gen8_i2c: i2c@c250000 { |
| compatible = "nvidia,tegra186-i2c", "nvidia,tegra114-i2c"; |
| reg = <0x0 0x0c250000 0x0 0x10000>; |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clocks = <&bpmp TEGRA186_CLK_I2C8>; |
| clock-names = "div-clk"; |
| resets = <&bpmp TEGRA186_RESET_I2C8>; |
| reset-names = "i2c"; |
| status = "disabled"; |
| }; |
| |
| uartc: serial@c280000 { |
| compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x0c280000 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_UARTC>; |
| clock-names = "serial"; |
| resets = <&bpmp TEGRA186_RESET_UARTC>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| uartg: serial@c290000 { |
| compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart"; |
| reg = <0x0 0x0c290000 0x0 0x40>; |
| reg-shift = <2>; |
| interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_UARTG>; |
| clock-names = "serial"; |
| resets = <&bpmp TEGRA186_RESET_UARTG>; |
| reset-names = "serial"; |
| status = "disabled"; |
| }; |
| |
| gpio_aon: gpio@c2f0000 { |
| compatible = "nvidia,tegra186-gpio-aon"; |
| reg-names = "security", "gpio"; |
| reg = <0x0 0xc2f0000 0x0 0x1000>, |
| <0x0 0xc2f1000 0x0 0x1000>; |
| interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| interrupt-controller; |
| #interrupt-cells = <2>; |
| }; |
| |
| pmc@c360000 { |
| compatible = "nvidia,tegra186-pmc"; |
| reg = <0 0x0c360000 0 0x10000>, |
| <0 0x0c370000 0 0x10000>, |
| <0 0x0c380000 0 0x10000>, |
| <0 0x0c390000 0 0x10000>; |
| reg-names = "pmc", "wake", "aotag", "scratch"; |
| }; |
| |
| ccplex@e000000 { |
| compatible = "nvidia,tegra186-ccplex-cluster"; |
| reg = <0x0 0x0e000000 0x0 0x3fffff>; |
| |
| nvidia,bpmp = <&bpmp>; |
| }; |
| |
| pcie@10003000 { |
| compatible = "nvidia,tegra186-pcie"; |
| power-domains = <&bpmp TEGRA186_POWER_DOMAIN_PCX>; |
| device_type = "pci"; |
| reg = <0x0 0x10003000 0x0 0x00000800 /* PADS registers */ |
| 0x0 0x10003800 0x0 0x00000800 /* AFI registers */ |
| 0x0 0x40000000 0x0 0x10000000>; /* configuration space */ |
| reg-names = "pads", "afi", "cs"; |
| |
| interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, /* controller interrupt */ |
| <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; /* MSI interrupt */ |
| interrupt-names = "intr", "msi"; |
| |
| #interrupt-cells = <1>; |
| interrupt-map-mask = <0 0 0 0>; |
| interrupt-map = <0 0 0 0 &gic GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; |
| |
| bus-range = <0x00 0xff>; |
| #address-cells = <3>; |
| #size-cells = <2>; |
| |
| ranges = <0x82000000 0 0x10000000 0x0 0x10000000 0 0x00001000 /* port 0 configuration space */ |
| 0x82000000 0 0x10001000 0x0 0x10001000 0 0x00001000 /* port 1 configuration space */ |
| 0x82000000 0 0x10004000 0x0 0x10004000 0 0x00001000 /* port 2 configuration space */ |
| 0x81000000 0 0x0 0x0 0x50000000 0 0x00010000 /* downstream I/O (64 KiB) */ |
| 0x82000000 0 0x50100000 0x0 0x50100000 0 0x07F00000 /* non-prefetchable memory (127 MiB) */ |
| 0xc2000000 0 0x58000000 0x0 0x58000000 0 0x28000000>; /* prefetchable memory (640 MiB) */ |
| |
| clocks = <&bpmp TEGRA186_CLK_AFI>, |
| <&bpmp TEGRA186_CLK_PCIE>, |
| <&bpmp TEGRA186_CLK_PLLE>; |
| clock-names = "afi", "pex", "pll_e"; |
| |
| resets = <&bpmp TEGRA186_RESET_AFI>, |
| <&bpmp TEGRA186_RESET_PCIE>, |
| <&bpmp TEGRA186_RESET_PCIEXCLK>; |
| reset-names = "afi", "pex", "pcie_x"; |
| |
| status = "disabled"; |
| |
| pci@1,0 { |
| device_type = "pci"; |
| assigned-addresses = <0x82000800 0 0x10000000 0 0x1000>; |
| reg = <0x000800 0 0 0 0>; |
| status = "disabled"; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| |
| nvidia,num-lanes = <2>; |
| }; |
| |
| pci@2,0 { |
| device_type = "pci"; |
| assigned-addresses = <0x82001000 0 0x10001000 0 0x1000>; |
| reg = <0x001000 0 0 0 0>; |
| status = "disabled"; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| |
| nvidia,num-lanes = <1>; |
| }; |
| |
| pci@3,0 { |
| device_type = "pci"; |
| assigned-addresses = <0x82001800 0 0x10004000 0 0x1000>; |
| reg = <0x001800 0 0 0 0>; |
| status = "disabled"; |
| |
| #address-cells = <3>; |
| #size-cells = <2>; |
| ranges; |
| |
| nvidia,num-lanes = <1>; |
| }; |
| }; |
| |
| smmu: iommu@12000000 { |
| compatible = "arm,mmu-500"; |
| reg = <0 0x12000000 0 0x800000>; |
| interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; |
| stream-match-mask = <0x7f80>; |
| #global-interrupts = <1>; |
| #iommu-cells = <1>; |
| }; |
| |
| host1x@13e00000 { |
| compatible = "nvidia,tegra186-host1x", "simple-bus"; |
| reg = <0x0 0x13e00000 0x0 0x10000>, |
| <0x0 0x13e10000 0x0 0x10000>; |
| reg-names = "hypervisor", "vm"; |
| interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 263 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_HOST1X>; |
| clock-names = "host1x"; |
| resets = <&bpmp TEGRA186_RESET_HOST1X>; |
| reset-names = "host1x"; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| ranges = <0x15000000 0x0 0x15000000 0x01000000>; |
| iommus = <&smmu TEGRA186_SID_HOST1X>; |
| |
| dpaux1: dpaux@15040000 { |
| compatible = "nvidia,tegra186-dpaux"; |
| reg = <0x15040000 0x10000>; |
| interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_DPAUX1>, |
| <&bpmp TEGRA186_CLK_PLLDP>; |
| clock-names = "dpaux", "parent"; |
| resets = <&bpmp TEGRA186_RESET_DPAUX1>; |
| reset-names = "dpaux"; |
| status = "disabled"; |
| |
| power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; |
| |
| state_dpaux1_aux: pinmux-aux { |
| groups = "dpaux-io"; |
| function = "aux"; |
| }; |
| |
| state_dpaux1_i2c: pinmux-i2c { |
| groups = "dpaux-io"; |
| function = "i2c"; |
| }; |
| |
| state_dpaux1_off: pinmux-off { |
| groups = "dpaux-io"; |
| function = "off"; |
| }; |
| |
| i2c-bus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| display-hub@15200000 { |
| compatible = "nvidia,tegra186-display", "simple-bus"; |
| resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_MISC>, |
| <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP0>, |
| <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP1>, |
| <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP2>, |
| <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP3>, |
| <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP4>, |
| <&bpmp TEGRA186_RESET_NVDISPLAY0_WGRP5>; |
| reset-names = "misc", "wgrp0", "wgrp1", "wgrp2", |
| "wgrp3", "wgrp4", "wgrp5"; |
| clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_DISP>, |
| <&bpmp TEGRA186_CLK_NVDISPLAY_DSC>, |
| <&bpmp TEGRA186_CLK_NVDISPLAYHUB>; |
| clock-names = "disp", "dsc", "hub"; |
| status = "disabled"; |
| |
| power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; |
| |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| ranges = <0x15200000 0x15200000 0x40000>; |
| |
| display@15200000 { |
| compatible = "nvidia,tegra186-dc"; |
| reg = <0x15200000 0x10000>; |
| interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P0>; |
| clock-names = "dc"; |
| resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD0>; |
| reset-names = "dc"; |
| |
| power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; |
| iommus = <&smmu TEGRA186_SID_NVDISPLAY>; |
| |
| nvidia,outputs = <&dsia &dsib &sor0 &sor1>; |
| nvidia,head = <0>; |
| }; |
| |
| display@15210000 { |
| compatible = "nvidia,tegra186-dc"; |
| reg = <0x15210000 0x10000>; |
| interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P1>; |
| clock-names = "dc"; |
| resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD1>; |
| reset-names = "dc"; |
| |
| power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPB>; |
| iommus = <&smmu TEGRA186_SID_NVDISPLAY>; |
| |
| nvidia,outputs = <&dsia &dsib &sor0 &sor1>; |
| nvidia,head = <1>; |
| }; |
| |
| display@15220000 { |
| compatible = "nvidia,tegra186-dc"; |
| reg = <0x15220000 0x10000>; |
| interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_NVDISPLAY_P2>; |
| clock-names = "dc"; |
| resets = <&bpmp TEGRA186_RESET_NVDISPLAY0_HEAD2>; |
| reset-names = "dc"; |
| |
| power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISPC>; |
| iommus = <&smmu TEGRA186_SID_NVDISPLAY>; |
| |
| nvidia,outputs = <&sor0 &sor1>; |
| nvidia,head = <2>; |
| }; |
| }; |
| |
| dsia: dsi@15300000 { |
| compatible = "nvidia,tegra186-dsi"; |
| reg = <0x15300000 0x10000>; |
| interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_DSI>, |
| <&bpmp TEGRA186_CLK_DSIA_LP>, |
| <&bpmp TEGRA186_CLK_PLLD>; |
| clock-names = "dsi", "lp", "parent"; |
| resets = <&bpmp TEGRA186_RESET_DSI>; |
| reset-names = "dsi"; |
| status = "disabled"; |
| |
| power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; |
| }; |
| |
| vic@15340000 { |
| compatible = "nvidia,tegra186-vic"; |
| reg = <0x15340000 0x40000>; |
| interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_VIC>; |
| clock-names = "vic"; |
| resets = <&bpmp TEGRA186_RESET_VIC>; |
| reset-names = "vic"; |
| |
| power-domains = <&bpmp TEGRA186_POWER_DOMAIN_VIC>; |
| }; |
| |
| dsib: dsi@15400000 { |
| compatible = "nvidia,tegra186-dsi"; |
| reg = <0x15400000 0x10000>; |
| interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_DSIB>, |
| <&bpmp TEGRA186_CLK_DSIB_LP>, |
| <&bpmp TEGRA186_CLK_PLLD>; |
| clock-names = "dsi", "lp", "parent"; |
| resets = <&bpmp TEGRA186_RESET_DSIB>; |
| reset-names = "dsi"; |
| status = "disabled"; |
| |
| power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; |
| }; |
| |
| sor0: sor@15540000 { |
| compatible = "nvidia,tegra186-sor"; |
| reg = <0x15540000 0x10000>; |
| interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_SOR0>, |
| <&bpmp TEGRA186_CLK_SOR0_OUT>, |
| <&bpmp TEGRA186_CLK_PLLD2>, |
| <&bpmp TEGRA186_CLK_PLLDP>, |
| <&bpmp TEGRA186_CLK_SOR_SAFE>, |
| <&bpmp TEGRA186_CLK_SOR0_PAD_CLKOUT>; |
| clock-names = "sor", "out", "parent", "dp", "safe", |
| "pad"; |
| resets = <&bpmp TEGRA186_RESET_SOR0>; |
| reset-names = "sor"; |
| pinctrl-0 = <&state_dpaux_aux>; |
| pinctrl-1 = <&state_dpaux_i2c>; |
| pinctrl-2 = <&state_dpaux_off>; |
| pinctrl-names = "aux", "i2c", "off"; |
| status = "disabled"; |
| |
| power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; |
| nvidia,interface = <0>; |
| }; |
| |
| sor1: sor@15580000 { |
| compatible = "nvidia,tegra186-sor1"; |
| reg = <0x15580000 0x10000>; |
| interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_SOR1>, |
| <&bpmp TEGRA186_CLK_SOR1_OUT>, |
| <&bpmp TEGRA186_CLK_PLLD3>, |
| <&bpmp TEGRA186_CLK_PLLDP>, |
| <&bpmp TEGRA186_CLK_SOR_SAFE>, |
| <&bpmp TEGRA186_CLK_SOR1_PAD_CLKOUT>; |
| clock-names = "sor", "out", "parent", "dp", "safe", |
| "pad"; |
| resets = <&bpmp TEGRA186_RESET_SOR1>; |
| reset-names = "sor"; |
| pinctrl-0 = <&state_dpaux1_aux>; |
| pinctrl-1 = <&state_dpaux1_i2c>; |
| pinctrl-2 = <&state_dpaux1_off>; |
| pinctrl-names = "aux", "i2c", "off"; |
| status = "disabled"; |
| |
| power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; |
| nvidia,interface = <1>; |
| }; |
| |
| dpaux: dpaux@155c0000 { |
| compatible = "nvidia,tegra186-dpaux"; |
| reg = <0x155c0000 0x10000>; |
| interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_DPAUX>, |
| <&bpmp TEGRA186_CLK_PLLDP>; |
| clock-names = "dpaux", "parent"; |
| resets = <&bpmp TEGRA186_RESET_DPAUX>; |
| reset-names = "dpaux"; |
| status = "disabled"; |
| |
| power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; |
| |
| state_dpaux_aux: pinmux-aux { |
| groups = "dpaux-io"; |
| function = "aux"; |
| }; |
| |
| state_dpaux_i2c: pinmux-i2c { |
| groups = "dpaux-io"; |
| function = "i2c"; |
| }; |
| |
| state_dpaux_off: pinmux-off { |
| groups = "dpaux-io"; |
| function = "off"; |
| }; |
| |
| i2c-bus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| }; |
| }; |
| |
| padctl@15880000 { |
| compatible = "nvidia,tegra186-dsi-padctl"; |
| reg = <0x15880000 0x10000>; |
| resets = <&bpmp TEGRA186_RESET_DSI>; |
| reset-names = "dsi"; |
| status = "disabled"; |
| }; |
| |
| dsic: dsi@15900000 { |
| compatible = "nvidia,tegra186-dsi"; |
| reg = <0x15900000 0x10000>; |
| interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_DSIC>, |
| <&bpmp TEGRA186_CLK_DSIC_LP>, |
| <&bpmp TEGRA186_CLK_PLLD>; |
| clock-names = "dsi", "lp", "parent"; |
| resets = <&bpmp TEGRA186_RESET_DSIC>; |
| reset-names = "dsi"; |
| status = "disabled"; |
| |
| power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; |
| }; |
| |
| dsid: dsi@15940000 { |
| compatible = "nvidia,tegra186-dsi"; |
| reg = <0x15940000 0x10000>; |
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&bpmp TEGRA186_CLK_DSID>, |
| <&bpmp TEGRA186_CLK_DSID_LP>, |
| <&bpmp TEGRA186_CLK_PLLD>; |
| clock-names = "dsi", "lp", "parent"; |
| resets = <&bpmp TEGRA186_RESET_DSID>; |
| reset-names = "dsi"; |
| status = "disabled"; |
| |
| power-domains = <&bpmp TEGRA186_POWER_DOMAIN_DISP>; |
| }; |
| }; |
| |
| gpu@17000000 { |
| compatible = "nvidia,gp10b"; |
| reg = <0x0 0x17000000 0x0 0x1000000>, |
| <0x0 0x18000000 0x0 0x1000000>; |
| interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "stall", "nonstall"; |
| |
| clocks = <&bpmp TEGRA186_CLK_GPCCLK>, |
| <&bpmp TEGRA186_CLK_GPU>; |
| clock-names = "gpu", "pwr"; |
| resets = <&bpmp TEGRA186_RESET_GPU>; |
| reset-names = "gpu"; |
| status = "disabled"; |
| |
| power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; |
| }; |
| |
| sysram@30000000 { |
| compatible = "nvidia,tegra186-sysram", "mmio-sram"; |
| reg = <0x0 0x30000000 0x0 0x50000>; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; |
| |
| cpu_bpmp_tx: shmem@4e000 { |
| compatible = "nvidia,tegra186-bpmp-shmem"; |
| reg = <0x0 0x4e000 0x0 0x1000>; |
| label = "cpu-bpmp-tx"; |
| pool; |
| }; |
| |
| cpu_bpmp_rx: shmem@4f000 { |
| compatible = "nvidia,tegra186-bpmp-shmem"; |
| reg = <0x0 0x4f000 0x0 0x1000>; |
| label = "cpu-bpmp-rx"; |
| pool; |
| }; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| compatible = "nvidia,tegra186-denver", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x000>; |
| }; |
| |
| cpu@1 { |
| compatible = "nvidia,tegra186-denver", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x001>; |
| }; |
| |
| cpu@2 { |
| compatible = "arm,cortex-a57", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x100>; |
| }; |
| |
| cpu@3 { |
| compatible = "arm,cortex-a57", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x101>; |
| }; |
| |
| cpu@4 { |
| compatible = "arm,cortex-a57", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x102>; |
| }; |
| |
| cpu@5 { |
| compatible = "arm,cortex-a57", "arm,armv8"; |
| device_type = "cpu"; |
| reg = <0x103>; |
| }; |
| }; |
| |
| bpmp: bpmp { |
| compatible = "nvidia,tegra186-bpmp"; |
| mboxes = <&hsp_top0 TEGRA_HSP_MBOX_TYPE_DB |
| TEGRA_HSP_DB_MASTER_BPMP>; |
| shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; |
| #clock-cells = <1>; |
| #reset-cells = <1>; |
| #power-domain-cells = <1>; |
| |
| bpmp_i2c: i2c { |
| compatible = "nvidia,tegra186-bpmp-i2c"; |
| nvidia,bpmp-bus-id = <5>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| bpmp_thermal: thermal { |
| compatible = "nvidia,tegra186-bpmp-thermal"; |
| #thermal-sensor-cells = <1>; |
| }; |
| }; |
| |
| thermal-zones { |
| a57 { |
| polling-delay = <0>; |
| polling-delay-passive = <1000>; |
| |
| thermal-sensors = |
| <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_CPU>; |
| |
| trips { |
| critical { |
| temperature = <101000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| }; |
| }; |
| |
| denver { |
| polling-delay = <0>; |
| polling-delay-passive = <1000>; |
| |
| thermal-sensors = |
| <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AUX>; |
| |
| trips { |
| critical { |
| temperature = <101000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| }; |
| }; |
| |
| gpu { |
| polling-delay = <0>; |
| polling-delay-passive = <1000>; |
| |
| thermal-sensors = |
| <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_GPU>; |
| |
| trips { |
| critical { |
| temperature = <101000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| }; |
| }; |
| |
| pll { |
| polling-delay = <0>; |
| polling-delay-passive = <1000>; |
| |
| thermal-sensors = |
| <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_PLLX>; |
| |
| trips { |
| critical { |
| temperature = <101000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| }; |
| }; |
| |
| always_on { |
| polling-delay = <0>; |
| polling-delay-passive = <1000>; |
| |
| thermal-sensors = |
| <&bpmp_thermal TEGRA186_BPMP_THERMAL_ZONE_AO>; |
| |
| trips { |
| critical { |
| temperature = <101000>; |
| hysteresis = <0>; |
| type = "critical"; |
| }; |
| }; |
| |
| cooling-maps { |
| }; |
| }; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 |
| (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; |
| interrupt-parent = <&gic>; |
| }; |
| }; |
