dt-bindings: memory: mt8167-larb-port: fix incorrect ports for larb1/2
The definition of the larb ports does not really match the driver, which
meant that we could not enable the MMU correctly for larb1 and larb2.
Fix the definition to match what is done in the iommu driver.
Signed-off-by: Fabien Parent <fparent@baylibre.com>
diff --git a/include/dt-bindings/memory/mt8167-larb-port.h b/include/dt-bindings/memory/mt8167-larb-port.h
index 4e010a7..7cb3325 100644
--- a/include/dt-bindings/memory/mt8167-larb-port.h
+++ b/include/dt-bindings/memory/mt8167-larb-port.h
@@ -14,46 +14,44 @@
#ifndef _DTS_IOMMU_PORT_MT8167_H_
#define _DTS_IOMMU_PORT_MT8167_H_
-#define MT8167_LARB0_PORT_NUM 8
-#define MT8167_LARB1_PORT_NUM 13
-#define MT8167_LARB2_PORT_NUM 7
+#define MTK_M4U_ID(larb, port) (((larb) << 5) | (port))
-#define MT8167_LARB0_PORT(port) (port)
-#define MT8167_LARB1_PORT(port) ((port) + MT8167_LARB0_PORT_NUM)
-#define MT8167_LARB2_PORT(port) ((port) + MT8167_LARB0_PORT_NUM + MT8167_LARB1_PORT_NUM)
+#define M4U_LARB0_ID 0
+#define M4U_LARB1_ID 1
+#define M4U_LARB2_ID 2
/* larb0 */
-#define M4U_PORT_DISP_OVL0 MT8167_LARB0_PORT(0)
-#define M4U_PORT_DISP_RDMA0 MT8167_LARB0_PORT(1)
-#define M4U_PORT_DISP_WDMA0 MT8167_LARB0_PORT(2)
-#define M4U_PORT_DISP_RDMA1 MT8167_LARB0_PORT(3)
-#define M4U_PORT_MDP_RDMA MT8167_LARB0_PORT(4)
-#define M4U_PORT_MDP_WDMA MT8167_LARB0_PORT(5)
-#define M4U_PORT_MDP_WROT MT8167_LARB0_PORT(6)
-#define M4U_PORT_DISP_FAKE MT8167_LARB0_PORT(7)
+#define M4U_PORT_DISP_OVL0 MTK_M4U_ID(M4U_LARB0_ID, 0)
+#define M4U_PORT_DISP_RDMA0 MTK_M4U_ID(M4U_LARB0_ID, 1)
+#define M4U_PORT_DISP_WDMA0 MTK_M4U_ID(M4U_LARB0_ID, 2)
+#define M4U_PORT_DISP_RDMA1 MTK_M4U_ID(M4U_LARB0_ID, 3)
+#define M4U_PORT_MDP_RDMA MTK_M4U_ID(M4U_LARB0_ID, 4)
+#define M4U_PORT_MDP_WDMA MTK_M4U_ID(M4U_LARB0_ID, 5)
+#define M4U_PORT_MDP_WROT MTK_M4U_ID(M4U_LARB0_ID, 6)
+#define M4U_PORT_DISP_FAKE MTK_M4U_ID(M4U_LARB0_ID, 7)
/* IMG larb1*/
-#define M4U_PORT_CAM_IMGO MT8167_LARB1_PORT(0)
-#define M4U_PORT_CAM_IMG2O MT8167_LARB1_PORT(1)
-#define M4U_PORT_CAM_LSCI MT8167_LARB1_PORT(2)
-#define M4U_PORT_CAM_ESFKO MT8167_LARB1_PORT(3)
-#define M4U_PORT_CAM_AAO MT8167_LARB1_PORT(4)
-#define M4U_PORT_VENC_REC MT8167_LARB1_PORT(5)
-#define M4U_PORT_VENC_BSDMA MT8167_LARB1_PORT(6)
-#define M4U_PORT_VENC_RD_COMV MT8167_LARB1_PORT(7)
-#define M4U_PORT_CAM_IMGI MT8167_LARB1_PORT(8)
-#define M4U_PORT_VENC_CUR_LUMA MT8167_LARB1_PORT(9)
-#define M4U_PORT_VENC_CUR_CHROMA MT8167_LARB1_PORT(10)
-#define M4U_PORT_VENC_REF_LUMA MT8167_LARB1_PORT(11)
-#define M4U_PORT_VENC_REF_CHROMA MT8167_LARB1_PORT(12)
+#define M4U_PORT_CAM_IMGO MTK_M4U_ID(M4U_LARB1_ID, 0)
+#define M4U_PORT_CAM_IMG2O MTK_M4U_ID(M4U_LARB1_ID, 1)
+#define M4U_PORT_CAM_LSCI MTK_M4U_ID(M4U_LARB1_ID, 2)
+#define M4U_PORT_CAM_ESFKO MTK_M4U_ID(M4U_LARB1_ID, 3)
+#define M4U_PORT_CAM_AAO MTK_M4U_ID(M4U_LARB1_ID, 4)
+#define M4U_PORT_VENC_REC MTK_M4U_ID(M4U_LARB1_ID, 5)
+#define M4U_PORT_VENC_BSDMA MTK_M4U_ID(M4U_LARB1_ID, 6)
+#define M4U_PORT_VENC_RD_COMV MTK_M4U_ID(M4U_LARB1_ID, 7)
+#define M4U_PORT_CAM_IMGI MTK_M4U_ID(M4U_LARB1_ID, 8)
+#define M4U_PORT_VENC_CUR_LUMA MTK_M4U_ID(M4U_LARB1_ID, 9)
+#define M4U_PORT_VENC_CUR_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 10)
+#define M4U_PORT_VENC_REF_LUMA MTK_M4U_ID(M4U_LARB1_ID, 11)
+#define M4U_PORT_VENC_REF_CHROMA MTK_M4U_ID(M4U_LARB1_ID, 12)
/* VDEC larb2*/
-#define M4U_PORT_HW_VDEC_MC_EXT MT8167_LARB2_PORT(0)
-#define M4U_PORT_HW_VDEC_PP_EXT MT8167_LARB2_PORT(1)
-#define M4U_PORT_HW_VDEC_VLD_EXT MT8167_LARB2_PORT(2)
-#define M4U_PORT_HW_VDEC_AVC_MV_EXT MT8167_LARB2_PORT(3)
-#define M4U_PORT_HW_VDEC_PRED_RD_EXT MT8167_LARB2_PORT(4)
-#define M4U_PORT_HW_VDEC_PRED_WR_EXT MT8167_LARB2_PORT(5)
-#define M4U_PORT_HW_VDEC_PPWRAP_EXT MT8167_LARB2_PORT(6)
+#define M4U_PORT_HW_VDEC_MC_EXT MTK_M4U_ID(M4U_LARB2_ID, 0)
+#define M4U_PORT_HW_VDEC_PP_EXT MTK_M4U_ID(M4U_LARB2_ID, 1)
+#define M4U_PORT_HW_VDEC_VLD_EXT MTK_M4U_ID(M4U_LARB2_ID, 2)
+#define M4U_PORT_HW_VDEC_AVC_MV_EXT MTK_M4U_ID(M4U_LARB2_ID, 3)
+#define M4U_PORT_HW_VDEC_PRED_RD_EXT MTK_M4U_ID(M4U_LARB2_ID, 4)
+#define M4U_PORT_HW_VDEC_PRED_WR_EXT MTK_M4U_ID(M4U_LARB2_ID, 5)
+#define M4U_PORT_HW_VDEC_PPWRAP_EXT MTK_M4U_ID(M4U_LARB2_ID, 6)
#endif
