| STMicroelectronics STi SATA controller |
| |
| This binding describes a SATA device. |
| |
| Required properties: |
| - compatible : Must be "st,ahci" |
| - reg : Physical base addresses and length of register sets |
| - interrupts : Interrupt associated with the SATA device |
| - interrupt-names : Associated name must be; "hostc" |
| - clocks : The phandle for the clock |
| - clock-names : Associated name must be; "ahci_clk" |
| - phys : The phandle for the PHY port |
| - phy-names : Associated name must be; "ahci_phy" |
| |
| Optional properties: |
| - resets : The power-down, soft-reset and power-reset lines of SATA IP |
| - reset-names : Associated names must be; "pwr-dwn", "sw-rst" and "pwr-rst" |
| |
| Example: |
| |
| /* Example for stih407 family silicon */ |
| sata0: sata@9b20000 { |
| compatible = "st,ahci"; |
| reg = <0x9b20000 0x1000>; |
| interrupts = <GIC_SPI 159 IRQ_TYPE_NONE>; |
| interrupt-names = "hostc"; |
| phys = <&phy_port0 PHY_TYPE_SATA>; |
| phy-names = "ahci_phy"; |
| resets = <&powerdown STIH407_SATA0_POWERDOWN>, |
| <&softreset STIH407_SATA0_SOFTRESET>, |
| <&softreset STIH407_SATA0_PWR_SOFTRESET>; |
| reset-names = "pwr-dwn", "sw-rst", "pwr-rst"; |
| clocks = <&clk_s_c0_flexgen CLK_ICN_REG>; |
| clock-names = "ahci_clk"; |
| }; |
