| // SPDX-License-Identifier: GPL-2.0 |
| /* |
| * Device Tree for the ARM Integrator/CP platform |
| */ |
| |
| /dts-v1/; |
| /include/ "integrator.dtsi" |
| |
| / { |
| model = "ARM Integrator/CP"; |
| compatible = "arm,integrator-cp"; |
| |
| chosen { |
| bootargs = "root=/dev/ram0 console=ttyAMA0,38400n8 earlyprintk"; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| /* |
| * Since the board has pluggable CPU modules, we |
| * cannot define a proper compatible here. Let the |
| * boot loader fill in the apropriate compatible |
| * string if necessary. |
| */ |
| /* compatible = "arm,arm920t"; */ |
| reg = <0>; |
| /* |
| * TBD comment. |
| */ |
| /* kHz uV */ |
| operating-points = <50000 0 |
| 48000 0>; |
| clocks = <&cmcore>; |
| clock-names = "cpu"; |
| clock-latency = <1000000>; /* 1 ms */ |
| }; |
| }; |
| |
| /* |
| * The Integrator/CP overall clocking architecture can be found in |
| * ARM DUI 0184B page 7-28 "Integrator/CP922T system clocks" which |
| * appear to illustrate the layout used in most configurations. |
| */ |
| |
| /* The codec chrystal operates at 24.576 MHz */ |
| xtal_codec: xtal24.576@24.576M { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <24576000>; |
| }; |
| |
| /* The chrystal is divided by 2 by the codec for the AACI bit clock */ |
| aaci_bitclk: aaci_bitclk@12.288M { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clock-div = <2>; |
| clock-mult = <1>; |
| clocks = <&xtal_codec>; |
| }; |
| |
| /* This is a 25MHz chrystal on the base board */ |
| xtal25mhz: xtal25mhz@25M { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <25000000>; |
| }; |
| |
| /* The UART clock is 14.74 MHz divided from 25MHz by an ICS525 */ |
| uartclk: uartclk@14.74M { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <14745600>; |
| }; |
| |
| /* Actually sysclk I think */ |
| pclk: pclk@0 { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <0>; |
| }; |
| |
| core-module@10000000 { |
| /* 24 MHz chrystal on the core module */ |
| cm24mhz: cm24mhz@24M { |
| #clock-cells = <0>; |
| compatible = "fixed-clock"; |
| clock-frequency = <24000000>; |
| }; |
| |
| /* Oscillator on the core module, clocks the CPU core */ |
| cmcore: cmosc@24M { |
| compatible = "arm,syscon-icst525-integratorcp-cm-core"; |
| #clock-cells = <0>; |
| lock-offset = <0x14>; |
| vco-offset = <0x08>; |
| clocks = <&cm24mhz>; |
| }; |
| |
| /* Oscillator on the core module, clocks the memory bus */ |
| cmmem: cmosc@24M { |
| compatible = "arm,syscon-icst525-integratorcp-cm-mem"; |
| #clock-cells = <0>; |
| lock-offset = <0x14>; |
| vco-offset = <0x08>; |
| clocks = <&cm24mhz>; |
| }; |
| |
| /* Auxilary oscillator on the core module, clocks the CLCD */ |
| auxosc: auxosc@24M { |
| compatible = "arm,syscon-icst525"; |
| #clock-cells = <0>; |
| lock-offset = <0x14>; |
| vco-offset = <0x1c>; |
| clocks = <&cm24mhz>; |
| }; |
| |
| /* The KMI clock is the 24 MHz oscillator divided to 8MHz */ |
| kmiclk: kmiclk@1M { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clock-div = <3>; |
| clock-mult = <1>; |
| clocks = <&cm24mhz>; |
| }; |
| |
| /* The timer clock is the 24 MHz oscillator divided to 1MHz */ |
| timclk: timclk@1M { |
| #clock-cells = <0>; |
| compatible = "fixed-factor-clock"; |
| clock-div = <24>; |
| clock-mult = <1>; |
| clocks = <&cm24mhz>; |
| }; |
| }; |
| |
| syscon { |
| compatible = "arm,integrator-cp-syscon", "syscon"; |
| reg = <0xcb000000 0x100>; |
| }; |
| |
| timer0: timer@13000000 { |
| /* TIMER0 runs directly on the 25MHz chrystal */ |
| compatible = "arm,integrator-cp-timer"; |
| clocks = <&xtal25mhz>; |
| }; |
| |
| timer1: timer@13000100 { |
| /* TIMER1 runs @ 1MHz */ |
| compatible = "arm,integrator-cp-timer"; |
| clocks = <&timclk>; |
| }; |
| |
| timer2: timer@13000200 { |
| /* TIMER2 runs @ 1MHz */ |
| compatible = "arm,integrator-cp-timer"; |
| clocks = <&timclk>; |
| }; |
| |
| pic: pic@14000000 { |
| valid-mask = <0x1fc003ff>; |
| }; |
| |
| cic: cic@10000040 { |
| compatible = "arm,versatile-fpga-irq"; |
| #interrupt-cells = <1>; |
| interrupt-controller; |
| reg = <0x10000040 0x100>; |
| clear-mask = <0xffffffff>; |
| valid-mask = <0x00000007>; |
| }; |
| |
| /* The SIC is cascaded off IRQ 26 on the PIC */ |
| sic: sic@ca000000 { |
| compatible = "arm,versatile-fpga-irq"; |
| interrupt-parent = <&pic>; |
| interrupts = <26>; |
| #interrupt-cells = <1>; |
| interrupt-controller; |
| reg = <0xca000000 0x100>; |
| clear-mask = <0x00000fff>; |
| valid-mask = <0x00000fff>; |
| }; |
| |
| ethernet@c8000000 { |
| compatible = "smsc,lan91c111"; |
| reg = <0xc8000000 0x10>; |
| interrupt-parent = <&pic>; |
| interrupts = <27>; |
| }; |
| |
| fpga { |
| /* |
| * These PrimeCells are at the same location and using |
| * the same interrupts in all Integrators, but in the CP |
| * slightly newer versions are deployed. |
| */ |
| rtc@15000000 { |
| compatible = "arm,pl031", "arm,primecell"; |
| clocks = <&pclk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| uart@16000000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| clocks = <&uartclk>, <&pclk>; |
| clock-names = "uartclk", "apb_pclk"; |
| }; |
| |
| uart@17000000 { |
| compatible = "arm,pl011", "arm,primecell"; |
| clocks = <&uartclk>, <&pclk>; |
| clock-names = "uartclk", "apb_pclk"; |
| }; |
| |
| kmi@18000000 { |
| compatible = "arm,pl050", "arm,primecell"; |
| clocks = <&kmiclk>, <&pclk>; |
| clock-names = "KMIREFCLK", "apb_pclk"; |
| }; |
| |
| kmi@19000000 { |
| compatible = "arm,pl050", "arm,primecell"; |
| clocks = <&kmiclk>, <&pclk>; |
| clock-names = "KMIREFCLK", "apb_pclk"; |
| }; |
| |
| /* |
| * These PrimeCells are only available on the Integrator/CP |
| */ |
| mmc@1c000000 { |
| compatible = "arm,pl180", "arm,primecell"; |
| reg = <0x1c000000 0x1000>; |
| interrupts = <23 24>; |
| max-frequency = <515633>; |
| clocks = <&uartclk>, <&pclk>; |
| clock-names = "mclk", "apb_pclk"; |
| }; |
| |
| aaci@1d000000 { |
| compatible = "arm,pl041", "arm,primecell"; |
| reg = <0x1d000000 0x1000>; |
| interrupts = <25>; |
| clocks = <&pclk>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| clcd@c0000000 { |
| compatible = "arm,pl110", "arm,primecell"; |
| reg = <0xC0000000 0x1000>; |
| interrupts = <22>; |
| clocks = <&auxosc>, <&pclk>; |
| clock-names = "clcdclk", "apb_pclk"; |
| |
| port { |
| /* |
| * The VGA connected is implemented with a |
| * THS8134A triple DAC that can be run in 24bit |
| * or 16bit RGB mode. |
| */ |
| clcd_pads: endpoint { |
| remote-endpoint = <&clcd_panel>; |
| arm,pl11x,tft-r0g0b0-pads = <1 7 13>; |
| }; |
| }; |
| |
| panel { |
| compatible = "panel-dpi"; |
| |
| port { |
| clcd_panel: endpoint { |
| remote-endpoint = <&clcd_pads>; |
| }; |
| }; |
| |
| /* Standard 640x480 VGA timings */ |
| panel-timing { |
| clock-frequency = <25175000>; |
| hactive = <640>; |
| hback-porch = <48>; |
| hfront-porch = <16>; |
| hsync-len = <96>; |
| vactive = <480>; |
| vback-porch = <33>; |
| vfront-porch = <10>; |
| vsync-len = <2>; |
| }; |
| }; |
| }; |
| }; |
| }; |