| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) 2019 BayLibre, SAS |
| * Copyright (c) 2019 MediaTek, Inc |
| * Author: Fabien Parent <fparent@baylibre.com> |
| */ |
| |
| #ifndef _MT8516_AFE_REGS_H_ |
| #define _MT8516_AFE_REGS_H_ |
| |
| #include <linux/bitops.h> |
| |
| #define AUDIO_TOP_CON0 0x0000 |
| #define AUDIO_TOP_CON1 0x0004 |
| #define AUDIO_TOP_CON3 0x000c |
| #define AFE_DAC_CON0 0x0010 |
| #define AFE_DAC_CON1 0x0014 |
| #define AFE_I2S_CON 0x0018 |
| #define AFE_I2S_CON1 0x0034 |
| #define AFE_I2S_CON2 0x0038 |
| #define AFE_I2S_CON3 0x004c |
| #define AFE_DAIBT_CON0 0x001c |
| #define AFE_MRGIF_CON 0x003c |
| #define AFE_CONN_24BIT 0x006c |
| |
| #define AFE_CONN0 0x0020 |
| #define AFE_CONN1 0x0024 |
| #define AFE_CONN2 0x0028 |
| #define AFE_CONN3 0x002C |
| #define AFE_CONN4 0x0030 |
| #define AFE_CONN5 0x005C |
| |
| /* Memory interface */ |
| #define AFE_DL1_BASE 0x0040 |
| #define AFE_DL1_CUR 0x0044 |
| #define AFE_DL1_END 0x0048 |
| #define AFE_DL2_BASE 0x0050 |
| #define AFE_DL2_CUR 0x0054 |
| #define AFE_DL2_END 0x0058 |
| #define AFE_AWB_BASE 0x0070 |
| #define AFE_AWB_END 0x0078 |
| #define AFE_AWB_CUR 0x007c |
| #define AFE_VUL_BASE 0x0080 |
| #define AFE_VUL_CUR 0x008c |
| #define AFE_VUL_END 0x0088 |
| #define AFE_DAI_BASE 0x0090 |
| #define AFE_DAI_END 0x0098 |
| #define AFE_DAI_CUR 0x009c |
| #define AFE_MOD_PCM_BASE 0x0330 |
| #define AFE_MOD_PCM_END 0x0338 |
| #define AFE_MOD_PCM_CUR 0x033c |
| #define AFE_HDMI_OUT_BASE 0x0374 |
| #define AFE_HDMI_OUT_CUR 0x0378 |
| #define AFE_HDMI_OUT_END 0x037c |
| |
| #define AFE_MEMIF_MSB 0x00cc |
| #define AFE_MEMIF_MON0 0x00d0 |
| #define AFE_MEMIF_MON1 0x00d4 |
| #define AFE_MEMIF_MON2 0x00d8 |
| #define AFE_MEMIF_MON3 0x00dc |
| |
| #define AFE_ADDA_DL_SRC2_CON0 0x0108 |
| #define AFE_ADDA_DL_SRC2_CON1 0x010c |
| #define AFE_ADDA_UL_SRC_CON0 0x0114 |
| #define AFE_ADDA_UL_SRC_CON1 0x0118 |
| #define AFE_ADDA_TOP_CON0 0x0120 |
| #define AFE_ADDA_UL_DL_CON0 0x0124 |
| #define AFE_ADDA_NEWIF_CFG0 0x0138 |
| #define AFE_ADDA_NEWIF_CFG1 0x013c |
| #define AFE_ADDA_PREDIS_CON0 0x0260 |
| #define AFE_ADDA_PREDIS_CON1 0x0264 |
| |
| #define AFE_HDMI_OUT_CON0 0x0370 |
| |
| #define AFE_IRQ_MCU_CON 0x03a0 |
| #define AFE_IRQ_STATUS 0x03a4 |
| #define AFE_IRQ_CLR 0x03a8 |
| #define AFE_IRQ_CNT1 0x03ac |
| #define AFE_IRQ_CNT2 0x03b0 |
| #define AFE_IRQ_MCU_EN 0x03b4 |
| #define AFE_IRQ_CNT5 0x03bc |
| #define AFE_IRQ_CNT7 0x03dc |
| #define AFE_IRQ_CNT13 0x0408 |
| #define AFE_IRQ1_MCU_CNT_MON 0x03c0 |
| #define AFE_IRQ2_MCU_CNT_MON 0x03c4 |
| #define AFE_IRQ_MCU_CON2 0x03f8 |
| |
| #define AFE_MEMIF_PBUF_SIZE 0x03d8 |
| #define AFE_MEMIF_PBUF2_SIZE 0x03ec |
| |
| #define AFE_ASRC_CON0 0x0500 |
| |
| #define AFE_ASRC_CON13 0x0550 |
| #define AFE_ASRC_CON14 0x0554 |
| #define AFE_ASRC_CON15 0x0558 |
| #define AFE_ASRC_CON16 0x055c |
| #define AFE_ASRC_CON17 0x0560 |
| #define AFE_ASRC_CON18 0x0564 |
| #define AFE_ASRC_CON19 0x0568 |
| #define AFE_ASRC_CON20 0x056c |
| #define AFE_ASRC_CON21 0x0570 |
| |
| #define AFE_TDM_CON1 0x0548 |
| #define AFE_TDM_CON2 0x054c |
| |
| #define AFE_TDM_IN_CON1 0x0588 |
| #define AFE_TDM_IN_MON2 0x0594 |
| #define AFE_IRQ_CNT10 0x08dc |
| |
| #define AFE_HDMI_IN_2CH_CON0 0x09c0 |
| #define AFE_HDMI_IN_2CH_BASE 0x09c4 |
| #define AFE_HDMI_IN_2CH_END 0x09c8 |
| #define AFE_HDMI_IN_2CH_CUR 0x09cc |
| |
| #define AFE_MEMIF_MON15 0x0d7c |
| #define ABB_AFE_SDM_TEST 0x0f4c |
| |
| #define AFE_IRQ_STATUS_BITS 0x13ff |
| |
| /* AFE_I2S_CON (0x0018) */ |
| #define AFE_I2S_CON_PHASE_SHIFT_FIX BIT(31) |
| #define AFE_I2S_CON_BCK_INV BIT(29) |
| #define AFE_I2S_CON_FROM_IO_MUX BIT(28) |
| #define AFE_I2S_CON_LOW_JITTER_CLK BIT(12) |
| #define AFE_I2S_CON_LRCK_INV BIT(5) |
| #define AFE_I2S_CON_FORMAT_I2S BIT(3) |
| #define AFE_I2S_CON_SRC_SLAVE BIT(2) |
| #define AFE_I2S_CON_WLEN_32BIT BIT(1) |
| #define AFE_I2S_CON_EN BIT(0) |
| |
| /* AFE_CONN1 (0x0024) */ |
| #define AFE_CONN1_I03_O03_S BIT(19) |
| |
| /* AFE_CONN2 (0x0028) */ |
| #define AFE_CONN2_I04_O04_S BIT(4) |
| #define AFE_CONN2_I03_O04_S BIT(3) |
| |
| /* AFE_I2S_CON1 (0x0034) */ |
| #define AFE_I2S_CON1_I2S2_TO_PAD (1 << 18) |
| #define AFE_I2S_CON1_TDMOUT_TO_PAD (0 << 18) |
| #define AFE_I2S_CON1_TDMOUT_MUX_MASK GENMASK(18, 18) |
| #define AFE_I2S_CON1_LOW_JITTER_CLK BIT(12) |
| #define AFE_I2S_CON1_RATE(x) (((x) & 0xf) << 8) |
| #define AFE_I2S_CON1_FORMAT_I2S BIT(3) |
| #define AFE_I2S_CON1_WLEN_32BIT BIT(1) |
| #define AFE_I2S_CON1_EN BIT(0) |
| |
| /* AFE_I2S_CON2 (0x0038) */ |
| #define AFE_I2S_CON2_LOW_JITTER_CLK BIT(12) |
| #define AFE_I2S_CON2_RATE(x) (((x) & 0xf) << 8) |
| #define AFE_I2S_CON2_FORMAT_I2S BIT(3) |
| #define AFE_I2S_CON2_WLEN_32BIT BIT(1) |
| #define AFE_I2S_CON2_EN BIT(0) |
| |
| /* AFE_I2S_CON3 (0x004C) */ |
| #define AFE_I2S_CON3_LOW_JITTER_CLK BIT(12) |
| #define AFE_I2S_CON3_RATE(x) (((x) & 0xf) << 8) |
| #define AFE_I2S_CON3_FORMAT_I2S BIT(3) |
| #define AFE_I2S_CON3_WLEN_32BIT BIT(1) |
| #define AFE_I2S_CON3_EN BIT(0) |
| |
| /* AFE_CONN_24BIT (0x006c) */ |
| #define AFE_CONN_24BIT_O10 BIT(10) |
| #define AFE_CONN_24BIT_O09 BIT(9) |
| #define AFE_CONN_24BIT_O06 BIT(6) |
| #define AFE_CONN_24BIT_O05 BIT(5) |
| #define AFE_CONN_24BIT_O04 BIT(4) |
| #define AFE_CONN_24BIT_O03 BIT(3) |
| #define AFE_CONN_24BIT_O02 BIT(2) |
| #define AFE_CONN_24BIT_O01 BIT(1) |
| #define AFE_CONN_24BIT_O00 BIT(0) |
| |
| /* AFE_ADDA_UL_SRC_CON0 */ |
| #define AFE_ADDA_UL_RATE_CH1_SHIFT 17 |
| #define AFE_ADDA_UL_RATE_CH1_MASK 0x3 |
| #define AFE_ADDA_UL_RATE_CH2_SHIFT 19 |
| #define AFE_ADDA_UL_RATE_CH2_MASK 0x3 |
| |
| /* AFE_ADDA_DL_SRC2_CON0 (0x0108) */ |
| #define AFE_ADDA_DL_8X_UPSAMPLE (BIT(25) | BIT(24)) |
| #define AFE_ADDA_DL_MUTE_OFF (BIT(12) | BIT(11)) |
| #define AFE_ADDA_DL_VOICE_DATA BIT(5) |
| #define AFE_ADDA_DL_DEGRADE_GAIN BIT(1) |
| #define AFE_ADDA_DL_RATE_SHIFT 28 |
| |
| /* AFE_ASRC_CON0 (0x0500) */ |
| #define AFE_ASRC_CON0_ASM_ON BIT(0) |
| #define AFE_ASRC_CON0_STR_CLR_MASK GENMASK(6, 4) |
| #define AFE_ASRC_CON0_CLR_TX (0x1 << 4) |
| #define AFE_ASRC_CON0_CLR_RX (0x2 << 4) |
| #define AFE_ASRC_CON0_CLR_I2S (0x4 << 4) |
| |
| /* AFE_ASRC_CON13 (0x0550) */ |
| #define AFE_ASRC_CON13_16BIT BIT(19) |
| #define AFE_ASRC_CON13_MONO BIT(16) |
| |
| /* AFE_ASRC_CON16 (0x055c) */ |
| #define AFE_ASRC_CON16_FC2_CYCLE_MASK GENMASK(31, 16) |
| #define AFE_ASRC_CON16_FC2_CYCLE(x) (((x) - 1) << 16) |
| #define AFE_ASRC_CON16_FC2_AUTO_RST BIT(14) |
| #define AFE_ASRC_CON16_TUNE_FREQ5 BIT(12) |
| #define AFE_ASRC_CON16_COMP_FREQ_EN BIT(11) |
| #define AFE_ASRC_CON16_FC2_SEL GENMASK(9, 8) |
| #define AFE_ASRC_CON16_FC2_I2S_IN (0x1 << 8) |
| #define AFE_ASRC_CON16_FC2_DGL_BYPASS BIT(7) |
| #define AFE_ASRC_CON16_FC2_AUTO_RESTART BIT(2) |
| #define AFE_ASRC_CON16_FC2_FREQ BIT(1) |
| #define AFE_ASRC_CON16_FC2_EN BIT(0) |
| |
| /* AFE_ADDA_NEWIF_CFG0 (0x0138) */ |
| #define AFE_ADDA_NEWIF_ADC_VOICE_MODE_SHIFT 10 |
| #define AFE_ADDA_NEWIF_ADC_VOICE_MODE_CLR (0x3 << 10) |
| |
| /* AFE_SPDIF_IN */ |
| #define SPDIFIN_BASE_ADR (0x0994) |
| #define SPDIFIN_CUR_ADR (0x09B8) |
| |
| #endif |
