MALI: dt bindings: update binding for the Mali GPU
This updates the bindings of Mali GPU.
Signed-off-by: Alexandre Bailon <abailon@baylibre.com>
diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
index 18a2cde..3a3cd88 100644
--- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
+++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.txt
@@ -1,56 +1,147 @@
-ARM Mali Midgard GPU
-====================
+#
+# (C) COPYRIGHT 2013-2019 ARM Limited. All rights reserved.
+#
+# This program is free software and is provided to you under the terms of the
+# GNU General Public License version 2 as published by the Free Software
+# Foundation, and any use by you of this program is subject to the terms
+# of such GNU licence.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, you can access it online at
+# http://www.gnu.org/licenses/gpl-2.0.html.
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+#
+
+* ARM Mali Midgard devices
+
Required properties:
-- compatible :
- * Must contain one of the following:
- + "arm,mali-t604"
- + "arm,mali-t624"
- + "arm,mali-t628"
- + "arm,mali-t720"
- + "arm,mali-t760"
- + "arm,mali-t820"
- + "arm,mali-t830"
- + "arm,mali-t860"
- + "arm,mali-t880"
- * which must be preceded by one of the following vendor specifics:
- + "amlogic,meson-gxm-mali"
- + "rockchip,rk3288-mali"
- + "rockchip,rk3399-mali"
-
+- compatible : Should be mali<chip>, replacing digits with x from the back,
+until malit<Major>xx, ending with arm,mali-midgard, the latter not optional.
- reg : Physical base address of the device and length of the register area.
-
-- interrupts : Contains the three IRQ lines required by Mali Midgard devices.
-
+- interrupts : Contains the three IRQ lines required by T-6xx devices
- interrupt-names : Contains the names of IRQ resources in the order they were
- provided in the interrupts property. Must contain: "job", "mmu", "gpu".
+provided in the interrupts property. Must contain: "JOB, "MMU", "GPU".
+Optional:
-Optional properties:
+- clocks : One or more pairs of phandle to clock and clock specifier
+ for the Mali device. The order is important: the first clock
+ shall correspond to the "clk_mali" source, while the second clock
+ (that is optional) shall correspond to the "shadercores" source.
+- clock-names : Shall be set to: "clk_mali", "shadercores".
+- mali-supply : Phandle to the top level regulator for the Mali device.
+ Refer to
+Documentation/devicetree/bindings/regulator/regulator.txt for details.
+- shadercores-supply : Phandle to shader cores regulator for the Mali device.
+ This is optional.
+- operating-points-v2 : Refer to Documentation/devicetree/bindings/power/mali-opp.txt
+for details.
+- quirks_jm : Used to write to the JM_CONFIG register or equivalent.
+ Should be used with care. Options passed here are used to override
+ certain default behavior. Note: This will override 'idvs-group-size'
+ field in devicetree and module param 'corestack_driver_control',
+ therefore if 'quirks_jm' is used then 'idvs-group-size' and
+ 'corestack_driver_control' value should be incorporated into 'quirks_jm'.
+- quirks_sc : Used to write to the SHADER_CONFIG register.
+ Should be used with care. Options passed here are used to override
+ certain default behavior.
+- quirks_tiler : Used to write to the TILER_CONFIG register.
+ Should be used with care. Options passed here are used to
+ disable or override certain default behavior.
+- quirks_mmu : Used to write to the L2_CONFIG register.
+ Should be used with care. Options passed here are used to
+ disable or override certain default behavior.
+- power_model : Sets the power model parameters. Defined power models include:
+ "mali-simple-power-model", "mali-g51-power-model", "mali-g52-power-model",
+ "mali-g52_r1-power-model", "mali-g71-power-model", "mali-g72-power-model",
+ "mali-g76-power-model", "mali-g77-power-model", "mali-tnax-power-model"
+ and "mali-tbex-power-model".
+ - mali-simple-power-model: this model derives the GPU power usage based
+ on the GPU voltage scaled by the system temperature. Note: it was
+ designed for the Juno platform, and may not be suitable for others.
+ - compatible: Should be "arm,mali-simple-power-model"
+ - dynamic-coefficient: Coefficient, in pW/(Hz V^2), which is
+ multiplied by v^2*f to calculate the dynamic power consumption.
+ - static-coefficient: Coefficient, in uW/V^3, which is
+ multiplied by v^3 to calculate the static power consumption.
+ - ts: An array containing coefficients for the temperature
+ scaling factor. This is used to scale the static power by a
+ factor of tsf/1000000,
+ where tsf = ts[3]*T^3 + ts[2]*T^2 + ts[1]*T + ts[0],
+ and T = temperature in degrees.
+ - thermal-zone: A string identifying the thermal zone used for
+ the GPU
+ - temp-poll-interval-ms: the interval at which the system
+ temperature is polled
+ - mali-g*-power-model(s): unless being stated otherwise, these models derive
+ the GPU power usage based on performance counters, so they are more
+ accurate.
+ - compatible: Should be, as examples, "arm,mali-g51-power-model" /
+ "arm,mali-g72-power-model".
+ - scale: the dynamic power calculated by the power model is
+ multiplied by a factor of 'scale'. This value should be
+ chosen to match a particular implementation.
+ - min_sample_cycles: Fall back to the simple power model if the
+ number of GPU cycles for a given counter dump is less than
+ 'min_sample_cycles'. The default value of this should suffice.
+ * Note: when IPA is used, two separate power models (simple and counter-based)
+ are used at different points so care should be taken to configure
+ both power models in the device tree (specifically dynamic-coefficient,
+ static-coefficient and scale) to best match the platform.
+- system-coherency : Sets the coherency protocol to be used for coherent
+ accesses made from the GPU.
+ If not set then no coherency is used.
+ - 0 : ACE-Lite
+ - 1 : ACE
+ - 31 : No coherency
+- ipa-model : Sets the IPA model to be used for power management. GPU probe will fail if the
+ model is not found in the registered models list. If no model is specified here,
+ a gpu-id based model is picked if available, otherwise the default model is used.
+ - mali-simple-power-model: Default model used on mali
+- protected-mode-switcher : Phandle to device implemented protected mode switching functionality.
+Refer to Documentation/devicetree/bindings/arm/smc-protected-mode-switcher.txt for one implementation.
+- idvs-group-size : Override the IDVS group size value. Tasks are sent to
+ cores in groups of N + 1, so i.e. 0xF means 16 tasks.
+ Valid values are between 0 to 0x3F (including).
+- l2-size : Override L2 cache size on GPU that supports it
+- l2-hash : Override L2 hash function on GPU that supports it
-- clocks : Phandle to clock for the Mali Midgard device.
+Example for a Mali GPU with 1 clock and no regulators:
-- mali-supply : Phandle to regulator for the Mali device. Refer to
- Documentation/devicetree/bindings/regulator/regulator.txt for details.
+gpu@0xfc010000 {
+ compatible = "arm,malit602", "arm,malit60x", "arm,malit6xx", "arm,mali-midgard";
+ reg = <0xfc010000 0x4000>;
+ interrupts = <0 36 4>, <0 37 4>, <0 38 4>;
+ interrupt-names = "JOB", "MMU", "GPU";
-- operating-points-v2 : Refer to Documentation/devicetree/bindings/opp/opp.txt
- for details.
-
-
-Example for a Mali-T760:
-
-gpu@ffa30000 {
- compatible = "rockchip,rk3288-mali", "arm,mali-t760";
- reg = <0xffa30000 0x10000>;
- interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
- <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
- interrupt-names = "job", "mmu", "gpu";
- clocks = <&cru ACLK_GPU>;
- mali-supply = <&vdd_gpu>;
+ clocks = <&pclk_mali>;
+ clock-names = "clk_mali";
+ mali-supply = <&vdd_mali>;
operating-points-v2 = <&gpu_opp_table>;
- power-domains = <&power RK3288_PD_GPU>;
+ power_model@0 {
+ compatible = "arm,mali-simple-power-model";
+ static-coefficient = <2427750>;
+ dynamic-coefficient = <4687>;
+ ts = <20000 2000 (-20) 2>;
+ thermal-zone = "gpu";
+ };
+ power_model@1 {
+ compatible = "arm,mali-g71-power-model";
+ scale = <5>;
+ };
+
+ idvs-group-size = <0x7>;
+ l2-size = /bits/ 8 <0x10>;
+ l2-hash = /bits/ 8 <0x04>;
};
gpu_opp_table: opp_table0 {
@@ -85,3 +176,41 @@
opp-microvolt = <912500>;
};
};
+
+Example for a Mali GPU with 2 clocks and 2 regulators:
+
+gpu: gpu@6e000000 {
+ compatible = "arm,mali-midgard";
+ reg = <0x0 0x6e000000 0x0 0x200000>;
+ interrupts = <0 168 4>, <0 168 4>, <0 168 4>;
+ interrupt-names = "JOB", "MMU", "GPU";
+ clocks = <&clk_mali 0>, <&clk_mali 1>;
+ clock-names = "clk_mali", "shadercores";
+ mali-supply = <&supply0_3v3>;
+ shadercores-supply = <&supply1_3v3>;
+ system-coherency = <31>;
+ operating-points-v2 = <&gpu_opp_table>;
+};
+
+gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2", "operating-points-v2-mali";
+
+ opp@0 {
+ opp-hz = /bits/ 64 <50000000>;
+ opp-hz-real = /bits/ 64 <50000000>, /bits/ 64 <45000000>;
+ opp-microvolt = <820000>, <800000>;
+ opp-core-mask = /bits/ 64 <0xf>;
+ };
+ opp@1 {
+ opp-hz = /bits/ 64 <40000000>;
+ opp-hz-real = /bits/ 64 <40000000>, /bits/ 64 <35000000>;
+ opp-microvolt = <720000>, <700000>;
+ opp-core-mask = /bits/ 64 <0x7>;
+ };
+ opp@2 {
+ opp-hz = /bits/ 64 <30000000>;
+ opp-hz-real = /bits/ 64 <30000000>, /bits/ 64 <25000000>;
+ opp-microvolt = <620000>, <700000>;
+ opp-core-mask = /bits/ 64 <0x3>;
+ };
+};
diff --git a/Documentation/devicetree/bindings/power/mali-opp.txt b/Documentation/devicetree/bindings/power/mali-opp.txt
new file mode 100644
index 0000000..49ed773
--- /dev/null
+++ b/Documentation/devicetree/bindings/power/mali-opp.txt
@@ -0,0 +1,202 @@
+#
+# (C) COPYRIGHT 2017, 2019 ARM Limited. All rights reserved.
+#
+# This program is free software and is provided to you under the terms of the
+# GNU General Public License version 2 as published by the Free Software
+# Foundation, and any use by you of this program is subject to the terms
+# of such GNU licence.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, you can access it online at
+# http://www.gnu.org/licenses/gpl-2.0.html.
+#
+# SPDX-License-Identifier: GPL-2.0
+#
+#
+
+* ARM Mali Midgard OPP
+
+* OPP Table Node
+
+This describes the OPPs belonging to a device. This node can have following
+properties:
+
+Required properties:
+- compatible: Allow OPPs to express their compatibility. It should be:
+ "operating-points-v2", "operating-points-v2-mali".
+
+- OPP nodes: One or more OPP nodes describing voltage-current-frequency
+ combinations. Their name isn't significant but their phandle can be used to
+ reference an OPP.
+
+* OPP Node
+
+This defines voltage-current-frequency combinations along with other related
+properties.
+
+Required properties:
+- opp-hz: Nominal frequency in Hz, expressed as a 64-bit big-endian integer.
+ This should be treated as a relative performance measurement, taking both GPU
+ frequency and core mask into account.
+
+Optional properties:
+- opp-hz-real: List of one or two real frequencies in Hz, expressed as 64-bit
+ big-endian integers. They shall correspond to the clocks declared under
+ the Mali device node, and follow the same order.
+
+- opp-core-mask: Shader core mask. If neither this or opp-core-count are present
+ then all shader cores will be used for this OPP.
+
+- opp-core-count: Number of cores to use for this OPP. If this is present then
+ the driver will build a core mask using the available core mask provided by
+ the GPU hardware.
+
+ If neither this nor opp-core-mask are present then all shader cores will be
+ used for this OPP.
+
+ If both this and opp-core-mask are present then opp-core-mask is ignored.
+
+- opp-microvolt: List of one or two voltages in micro Volts. They shall correspond
+ to the regulators declared under the Mali device node, and follow the order:
+ "toplevel", "shadercores".
+
+ A single regulator's voltage is specified with an array of size one or three.
+ Single entry is for target voltage and three entries are for <target min max>
+ voltages.
+
+ Entries for multiple regulators must be present in the same order as
+ regulators are specified in device's DT node.
+
+- opp-microvolt-<name>: Named opp-microvolt property. This is exactly similar to
+ the above opp-microvolt property, but allows multiple voltage ranges to be
+ provided for the same OPP. At runtime, the platform can pick a <name> and
+ matching opp-microvolt-<name> property will be enabled for all OPPs. If the
+ platform doesn't pick a specific <name> or the <name> doesn't match with any
+ opp-microvolt-<name> properties, then opp-microvolt property shall be used, if
+ present.
+
+- opp-microamp: The maximum current drawn by the device in microamperes
+ considering system specific parameters (such as transients, process, aging,
+ maximum operating temperature range etc.) as necessary. This may be used to
+ set the most efficient regulator operating mode.
+
+ Should only be set if opp-microvolt is set for the OPP.
+
+ Entries for multiple regulators must be present in the same order as
+ regulators are specified in device's DT node. If this property isn't required
+ for few regulators, then this should be marked as zero for them. If it isn't
+ required for any regulator, then this property need not be present.
+
+- opp-microamp-<name>: Named opp-microamp property. Similar to
+ opp-microvolt-<name> property, but for microamp instead.
+
+- clock-latency-ns: Specifies the maximum possible transition latency (in
+ nanoseconds) for switching to this OPP from any other OPP.
+
+- turbo-mode: Marks the OPP to be used only for turbo modes. Turbo mode is
+ available on some platforms, where the device can run over its operating
+ frequency for a short duration of time limited by the device's power, current
+ and thermal limits.
+
+- opp-suspend: Marks the OPP to be used during device suspend. Only one OPP in
+ the table should have this.
+
+- opp-mali-errata-1485982: Marks the OPP to be selected for suspend clock.
+ This will be effective only if MALI_HW_ERRATA_1485982_USE_CLOCK_ALTERNATIVE is
+ enabled. It needs to be placed in any OPP that has proper suspend clock for
+ the HW workaround.
+
+- opp-supported-hw: This enables us to select only a subset of OPPs from the
+ larger OPP table, based on what version of the hardware we are running on. We
+ still can't have multiple nodes with the same opp-hz value in OPP table.
+
+ It's an user defined array containing a hierarchy of hardware version numbers,
+ supported by the OPP. For example: a platform with hierarchy of three levels
+ of versions (A, B and C), this field should be like <X Y Z>, where X
+ corresponds to Version hierarchy A, Y corresponds to version hierarchy B and Z
+ corresponds to version hierarchy C.
+
+ Each level of hierarchy is represented by a 32 bit value, and so there can be
+ only 32 different supported version per hierarchy. i.e. 1 bit per version. A
+ value of 0xFFFFFFFF will enable the OPP for all versions for that hierarchy
+ level. And a value of 0x00000000 will disable the OPP completely, and so we
+ never want that to happen.
+
+ If 32 values aren't sufficient for a version hierarchy, than that version
+ hierarchy can be contained in multiple 32 bit values. i.e. <X Y Z1 Z2> in the
+ above example, Z1 & Z2 refer to the version hierarchy Z.
+
+- status: Marks the node enabled/disabled.
+
+Example for a Juno with 1 clock and 1 regulator:
+
+gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2", "operating-points-v2-mali";
+
+ opp@112500000 {
+ opp-hz = /bits/ 64 <112500000>;
+ opp-hz-real = /bits/ 64 <450000000>;
+ opp-microvolt = <820000>;
+ opp-core-mask = /bits/ 64 <0x1>;
+ opp-suspend;
+ opp-mali-errata-1485982;
+ };
+ opp@225000000 {
+ opp-hz = /bits/ 64 <225000000>;
+ opp-hz-real = /bits/ 64 <450000000>;
+ opp-microvolt = <820000>;
+ opp-core-count = <2>;
+ };
+ opp@450000000 {
+ opp-hz = /bits/ 64 <450000000>;
+ opp-hz-real = /bits/ 64 <450000000>;
+ opp-microvolt = <820000>;
+ opp-core-mask = /bits/ 64 <0xf>;
+ };
+ opp@487500000 {
+ opp-hz = /bits/ 64 <487500000>;
+ opp-microvolt = <825000>;
+ };
+ opp@525000000 {
+ opp-hz = /bits/ 64 <525000000>;
+ opp-microvolt = <850000>;
+ };
+ opp@562500000 {
+ opp-hz = /bits/ 64 <562500000>;
+ opp-microvolt = <875000>;
+ };
+ opp@600000000 {
+ opp-hz = /bits/ 64 <600000000>;
+ opp-microvolt = <900000>;
+ };
+};
+
+Example for a Juno with 2 clocks and 2 regulators:
+
+gpu_opp_table: opp_table0 {
+ compatible = "operating-points-v2", "operating-points-v2-mali";
+
+ opp@0 {
+ opp-hz = /bits/ 64 <50000000>;
+ opp-hz-real = /bits/ 64 <50000000>, /bits/ 64 <45000000>;
+ opp-microvolt = <820000>, <800000>;
+ opp-core-mask = /bits/ 64 <0xf>;
+ };
+ opp@1 {
+ opp-hz = /bits/ 64 <40000000>;
+ opp-hz-real = /bits/ 64 <40000000>, /bits/ 64 <35000000>;
+ opp-microvolt = <720000>, <700000>;
+ opp-core-mask = /bits/ 64 <0x7>;
+ };
+ opp@2 {
+ opp-hz = /bits/ 64 <30000000>;
+ opp-hz-real = /bits/ 64 <30000000>, /bits/ 64 <25000000>;
+ opp-microvolt = <620000>, <700000>;
+ opp-core-mask = /bits/ 64 <0x3>;
+ };
+};
