| /* | 
 |  * phyCORE-MPC5200B-tiny (pcm030) board Device Tree Source | 
 |  * | 
 |  * Copyright 2006 Pengutronix | 
 |  * Sascha Hauer <s.hauer@pengutronix.de> | 
 |  * Copyright 2007 Pengutronix | 
 |  * Juergen Beisert <j.beisert@pengutronix.de> | 
 |  * | 
 |  * This program is free software; you can redistribute  it and/or modify it | 
 |  * under  the terms of  the GNU General  Public License as published by the | 
 |  * Free Software Foundation;  either version 2 of the  License, or (at your | 
 |  * option) any later version. | 
 |  */ | 
 |  | 
 | /include/ "mpc5200b.dtsi" | 
 |  | 
 | / { | 
 | 	model = "phytec,pcm030"; | 
 | 	compatible = "phytec,pcm030"; | 
 |  | 
 | 	soc5200@f0000000 { | 
 | 		timer@600 {		// General Purpose Timer | 
 | 			fsl,has-wdt; | 
 | 		}; | 
 |  | 
 | 		gpt2: timer@620 {	// General Purpose Timer in GPIO mode | 
 | 			compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; | 
 | 			gpio-controller; | 
 | 			#gpio-cells = <2>; | 
 | 		}; | 
 |  | 
 | 		gpt3: timer@630 {	// General Purpose Timer in GPIO mode | 
 | 			compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; | 
 | 			gpio-controller; | 
 | 			#gpio-cells = <2>; | 
 | 		}; | 
 |  | 
 | 		gpt4: timer@640 {	// General Purpose Timer in GPIO mode | 
 | 			compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; | 
 | 			gpio-controller; | 
 | 			#gpio-cells = <2>; | 
 | 		}; | 
 |  | 
 | 		gpt5: timer@650 {	// General Purpose Timer in GPIO mode | 
 | 			compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; | 
 | 			gpio-controller; | 
 | 			#gpio-cells = <2>; | 
 | 		}; | 
 |  | 
 | 		gpt6: timer@660 {	// General Purpose Timer in GPIO mode | 
 | 			compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; | 
 | 			gpio-controller; | 
 | 			#gpio-cells = <2>; | 
 | 		}; | 
 |  | 
 | 		gpt7: timer@670 {	// General Purpose Timer in GPIO mode | 
 | 			compatible = "fsl,mpc5200b-gpt-gpio","fsl,mpc5200-gpt-gpio"; | 
 | 			gpio-controller; | 
 | 			#gpio-cells = <2>; | 
 | 		}; | 
 |  | 
 | 		psc@2000 { /* PSC1 in ac97 mode */ | 
 | 			compatible = "mpc5200b-psc-ac97","fsl,mpc5200b-psc-ac97"; | 
 | 			cell-index = <0>; | 
 | 		}; | 
 |  | 
 | 		/* PSC2 port is used by CAN1/2 */ | 
 | 		psc@2200 { | 
 | 			status = "disabled"; | 
 | 		}; | 
 |  | 
 | 		psc@2400 { /* PSC3 in UART mode */ | 
 | 			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; | 
 | 		}; | 
 |  | 
 | 		/* PSC4 is ??? */ | 
 | 		psc@2600 { | 
 | 			status = "disabled"; | 
 | 		}; | 
 |  | 
 | 		/* PSC5 is ??? */ | 
 | 		psc@2800 { | 
 | 			status = "disabled"; | 
 | 		}; | 
 |  | 
 | 		psc@2c00 { /* PSC6 in UART mode */ | 
 | 			compatible = "fsl,mpc5200b-psc-uart","fsl,mpc5200-psc-uart"; | 
 | 		}; | 
 |  | 
 | 		ethernet@3000 { | 
 | 			phy-handle = <&phy0>; | 
 | 		}; | 
 |  | 
 | 		mdio@3000 { | 
 | 			phy0: ethernet-phy@0 { | 
 | 				reg = <0>; | 
 | 			}; | 
 | 		}; | 
 |  | 
 | 		i2c@3d40 { | 
 | 			rtc@51 { | 
 | 				compatible = "nxp,pcf8563"; | 
 | 				reg = <0x51>; | 
 | 			}; | 
 | 			eeprom@52 { | 
 | 				compatible = "catalyst,24c32"; | 
 | 				reg = <0x52>; | 
 | 				pagesize = <32>; | 
 | 			}; | 
 | 		}; | 
 |  | 
 | 		sram@8000 { | 
 | 			compatible = "fsl,mpc5200b-sram","fsl,mpc5200-sram"; | 
 | 			reg = <0x8000 0x4000>; | 
 | 		}; | 
 | 	}; | 
 |  | 
 | 	pci@f0000d00 { | 
 | 		interrupt-map-mask = <0xf800 0 0 7>; | 
 | 		interrupt-map = <0xc000 0 0 1 &mpc5200_pic 0 0 3 // 1st slot | 
 | 				 0xc000 0 0 2 &mpc5200_pic 1 1 3 | 
 | 				 0xc000 0 0 3 &mpc5200_pic 1 2 3 | 
 | 				 0xc000 0 0 4 &mpc5200_pic 1 3 3 | 
 |  | 
 | 				 0xc800 0 0 1 &mpc5200_pic 1 1 3 // 2nd slot | 
 | 				 0xc800 0 0 2 &mpc5200_pic 1 2 3 | 
 | 				 0xc800 0 0 3 &mpc5200_pic 1 3 3 | 
 | 				 0xc800 0 0 4 &mpc5200_pic 0 0 3>; | 
 | 		ranges = <0x42000000 0 0x80000000 0x80000000 0 0x20000000 | 
 | 			  0x02000000 0 0xa0000000 0xa0000000 0 0x10000000 | 
 | 			  0x01000000 0 0x00000000 0xb0000000 0 0x01000000>; | 
 | 	}; | 
 |  | 
 | 	localbus { | 
 | 		status = "disabled"; | 
 | 	}; | 
 | }; |