| /* SPDX-License-Identifier: GPL-2.0 */ |
| /* |
| * Copyright (c) 2019 MediaTek Inc. |
| * Author: Chen Zhong <chen.zhong@mediatek.com> |
| */ |
| |
| #ifndef __MFD_MT6392_CORE_H__ |
| #define __MFD_MT6392_CORE_H__ |
| |
| enum MT6392_IRQ_numbers { |
| MT6392_IRQ_SPKL_AB = 0, |
| MT6392_IRQ_SPKL, |
| MT6392_IRQ_BAT_L, |
| MT6392_IRQ_BAT_H, |
| MT6392_IRQ_WATCHDOG, |
| MT6392_IRQ_PWRKEY, |
| MT6392_IRQ_THR_L, |
| MT6392_IRQ_THR_H, |
| MT6392_IRQ_VBATON_UNDET, |
| MT6392_IRQ_BVALID_DET, |
| MT6392_IRQ_CHRDET, |
| MT6392_IRQ_OV, |
| MT6392_IRQ_LDO = 16, |
| MT6392_IRQ_FCHRKEY, |
| MT6392_IRQ_RELEASE_PWRKEY, |
| MT6392_IRQ_RELEASE_FCHRKEY, |
| MT6392_IRQ_RTC, |
| MT6392_IRQ_VPROC, |
| MT6392_IRQ_VSYS, |
| MT6392_IRQ_VCORE, |
| MT6392_IRQ_TYPE_C_CC, |
| MT6392_IRQ_TYPEC_H_MAX, |
| MT6392_IRQ_TYPEC_H_MIN, |
| MT6392_IRQ_TYPEC_L_MAX, |
| MT6392_IRQ_TYPEC_L_MIN, |
| MT6392_IRQ_THR_MAX, |
| MT6392_IRQ_THR_MIN, |
| MT6392_IRQ_NAG_C_DLTV, |
| MT6392_IRQ_NR, |
| }; |
| |
| #endif /* __MFD_MT6392_CORE_H__ */ |
