drivers/gpu/arm/midgard/mali_base_hwconfig_issues.h

/*
 *
 * (C) COPYRIGHT 2014-2019 ARM Limited. All rights reserved.
 *
 * This program is free software and is provided to you under the terms of the
 * GNU General Public License version 2 as published by the Free Software
 * Foundation, and any use by you of this program is subject to the terms
 * of such GNU licence.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, you can access it online at
 * http://www.gnu.org/licenses/gpl-2.0.html.
 *
 * SPDX-License-Identifier: GPL-2.0
 *
 */

/* AUTOMATICALLY GENERATED FILE. If you want to amend the issues/features,
 * please update base/tools/hwconfig_generator/hwc_{issues,features}.py
 * For more information see base/tools/hwconfig_generator/README
 */

#ifndef _BASE_HWCONFIG_ISSUES_H_
#define _BASE_HWCONFIG_ISSUES_H_

enum base_hw_issue {
	BASE_HW_ISSUE_5736,
	BASE_HW_ISSUE_6367,
	BASE_HW_ISSUE_6398,
	BASE_HW_ISSUE_6402,
	BASE_HW_ISSUE_6787,
	BASE_HW_ISSUE_7027,
	BASE_HW_ISSUE_7144,
	BASE_HW_ISSUE_7304,
	BASE_HW_ISSUE_8073,
	BASE_HW_ISSUE_8186,
	BASE_HW_ISSUE_8215,
	BASE_HW_ISSUE_8245,
	BASE_HW_ISSUE_8250,
	BASE_HW_ISSUE_8260,
	BASE_HW_ISSUE_8280,
	BASE_HW_ISSUE_8316,
	BASE_HW_ISSUE_8381,
	BASE_HW_ISSUE_8394,
	BASE_HW_ISSUE_8401,
	BASE_HW_ISSUE_8408,
	BASE_HW_ISSUE_8443,
	BASE_HW_ISSUE_8456,
	BASE_HW_ISSUE_8564,
	BASE_HW_ISSUE_8634,
	BASE_HW_ISSUE_8778,
	BASE_HW_ISSUE_8791,
	BASE_HW_ISSUE_8833,
	BASE_HW_ISSUE_8879,
	BASE_HW_ISSUE_8896,
	BASE_HW_ISSUE_8975,
	BASE_HW_ISSUE_8986,
	BASE_HW_ISSUE_8987,
	BASE_HW_ISSUE_9010,
	BASE_HW_ISSUE_9418,
	BASE_HW_ISSUE_9423,
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_9510,
	BASE_HW_ISSUE_9566,
	BASE_HW_ISSUE_9630,
	BASE_HW_ISSUE_10127,
	BASE_HW_ISSUE_10327,
	BASE_HW_ISSUE_10410,
	BASE_HW_ISSUE_10471,
	BASE_HW_ISSUE_10472,
	BASE_HW_ISSUE_10487,
	BASE_HW_ISSUE_10607,
	BASE_HW_ISSUE_10632,
	BASE_HW_ISSUE_10649,
	BASE_HW_ISSUE_10676,
	BASE_HW_ISSUE_10682,
	BASE_HW_ISSUE_10684,
	BASE_HW_ISSUE_10797,
	BASE_HW_ISSUE_10817,
	BASE_HW_ISSUE_10821,
	BASE_HW_ISSUE_10883,
	BASE_HW_ISSUE_10931,
	BASE_HW_ISSUE_10946,
	BASE_HW_ISSUE_10959,
	BASE_HW_ISSUE_10969,
	BASE_HW_ISSUE_10984,
	BASE_HW_ISSUE_10995,
	BASE_HW_ISSUE_11012,
	BASE_HW_ISSUE_11035,
	BASE_HW_ISSUE_11042,
	BASE_HW_ISSUE_11051,
	BASE_HW_ISSUE_11054,
	BASE_HW_ISSUE_11056,
	BASE_HW_ISSUE_T720_1386,
	BASE_HW_ISSUE_T76X_26,
	BASE_HW_ISSUE_T76X_1909,
	BASE_HW_ISSUE_T76X_1963,
	BASE_HW_ISSUE_T76X_3086,
	BASE_HW_ISSUE_T76X_3542,
	BASE_HW_ISSUE_T76X_3556,
	BASE_HW_ISSUE_T76X_3700,
	BASE_HW_ISSUE_T76X_3793,
	BASE_HW_ISSUE_T76X_3953,
	BASE_HW_ISSUE_T76X_3960,
	BASE_HW_ISSUE_T76X_3964,
	BASE_HW_ISSUE_T76X_3966,
	BASE_HW_ISSUE_T76X_3979,
	BASE_HW_ISSUE_T83X_817,
	BASE_HW_ISSUE_TMIX_7891,
	BASE_HW_ISSUE_TMIX_7940,
	BASE_HW_ISSUE_TMIX_8042,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TMIX_8138,
	BASE_HW_ISSUE_TMIX_8206,
	BASE_HW_ISSUE_TMIX_8343,
	BASE_HW_ISSUE_TMIX_8463,
	BASE_HW_ISSUE_TMIX_8456,
	GPUCORE_1619,
	BASE_HW_ISSUE_TSIX_1116,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TMIX_8438,
	BASE_HW_ISSUE_TNOX_1194,
	BASE_HW_ISSUE_TGOX_R1_1234,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_TSIX_1792,
	BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
	BASE_HW_ISSUE_TTRX_3076,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_generic[] = {
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tMIx_r0p0_05dev0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_10682,
	BASE_HW_ISSUE_11054,
	BASE_HW_ISSUE_T76X_3953,
	BASE_HW_ISSUE_TMIX_7891,
	BASE_HW_ISSUE_TMIX_8042,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TMIX_8138,
	BASE_HW_ISSUE_TMIX_8206,
	BASE_HW_ISSUE_TMIX_8343,
	BASE_HW_ISSUE_TMIX_8463,
	BASE_HW_ISSUE_TMIX_8456,
	BASE_HW_ISSUE_TMIX_8438,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tMIx_r0p0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_10682,
	BASE_HW_ISSUE_11054,
	BASE_HW_ISSUE_TMIX_7891,
	BASE_HW_ISSUE_TMIX_7940,
	BASE_HW_ISSUE_TMIX_8042,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TMIX_8138,
	BASE_HW_ISSUE_TMIX_8206,
	BASE_HW_ISSUE_TMIX_8343,
	BASE_HW_ISSUE_TMIX_8463,
	BASE_HW_ISSUE_TMIX_8456,
	BASE_HW_ISSUE_TMIX_8438,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tMIx_r0p1[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_10682,
	BASE_HW_ISSUE_11054,
	BASE_HW_ISSUE_TMIX_7891,
	BASE_HW_ISSUE_TMIX_7940,
	BASE_HW_ISSUE_TMIX_8042,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TMIX_8138,
	BASE_HW_ISSUE_TMIX_8206,
	BASE_HW_ISSUE_TMIX_8343,
	BASE_HW_ISSUE_TMIX_8463,
	BASE_HW_ISSUE_TMIX_8456,
	BASE_HW_ISSUE_TMIX_8438,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_model_tMIx[] = {
	BASE_HW_ISSUE_5736,
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TMIX_7891,
	BASE_HW_ISSUE_TMIX_7940,
	BASE_HW_ISSUE_TMIX_8042,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TMIX_8138,
	BASE_HW_ISSUE_TMIX_8206,
	BASE_HW_ISSUE_TMIX_8343,
	BASE_HW_ISSUE_TMIX_8456,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tHEx_r0p0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_10682,
	BASE_HW_ISSUE_11054,
	BASE_HW_ISSUE_TMIX_7891,
	BASE_HW_ISSUE_TMIX_8042,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tHEx_r0p1[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_10682,
	BASE_HW_ISSUE_11054,
	BASE_HW_ISSUE_TMIX_7891,
	BASE_HW_ISSUE_TMIX_8042,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tHEx_r0p2[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_10682,
	BASE_HW_ISSUE_11054,
	BASE_HW_ISSUE_TMIX_7891,
	BASE_HW_ISSUE_TMIX_8042,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tHEx_r0p3[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_10682,
	BASE_HW_ISSUE_TMIX_7891,
	BASE_HW_ISSUE_TMIX_8042,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_model_tHEx[] = {
	BASE_HW_ISSUE_5736,
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TMIX_7891,
	BASE_HW_ISSUE_TMIX_8042,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tSIx_r0p0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_11054,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TSIX_1116,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TSIX_1792,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tSIx_r0p1[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_11054,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TSIX_1116,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TSIX_1792,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tSIx_r1p0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_11054,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TSIX_1116,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tSIx_r1p1[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TSIX_1116,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_model_tSIx[] = {
	BASE_HW_ISSUE_5736,
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TSIX_1116,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tDVx_r0p0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TSIX_1116,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_model_tDVx[] = {
	BASE_HW_ISSUE_5736,
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TSIX_1116,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tNOx_r0p0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TSIX_1116,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TNOX_1194,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_model_tNOx[] = {
	BASE_HW_ISSUE_5736,
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TSIX_1116,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tGOx_r0p0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TSIX_1116,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TNOX_1194,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tGOx_r1p0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TSIX_1116,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TGOX_R1_1234,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_model_tGOx[] = {
	BASE_HW_ISSUE_5736,
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TMIX_8133,
	BASE_HW_ISSUE_TSIX_1116,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tTRx_r0p0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
	BASE_HW_ISSUE_TTRX_3076,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tTRx_r0p1[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
	BASE_HW_ISSUE_TTRX_3076,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_model_tTRx[] = {
	BASE_HW_ISSUE_5736,
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tNAx_r0p0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
	BASE_HW_ISSUE_TTRX_3076,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tNAx_r0p1[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
	BASE_HW_ISSUE_TTRX_3076,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_GPU2017_1336,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_model_tNAx[] = {
	BASE_HW_ISSUE_5736,
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tBEx_r0p0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tBEx_r1p0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_TTRX_2968_TTRX_3162,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_model_tBEx[] = {
	BASE_HW_ISSUE_5736,
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tULx_r0p0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_model_tULx[] = {
	BASE_HW_ISSUE_5736,
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tDUx_r0p0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_TTRX_921,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_model_tDUx[] = {
	BASE_HW_ISSUE_5736,
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tODx_r0p0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_model_tODx[] = {
	BASE_HW_ISSUE_5736,
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tIDx_r0p0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_model_tIDx[] = {
	BASE_HW_ISSUE_5736,
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_tVAx_r0p0[] = {
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_END
};

static const enum base_hw_issue base_hw_issues_model_tVAx[] = {
	BASE_HW_ISSUE_5736,
	BASE_HW_ISSUE_9435,
	BASE_HW_ISSUE_TSIX_2033,
	BASE_HW_ISSUE_TTRX_1337,
	BASE_HW_ISSUE_END
};

#endif /* _BASE_HWCONFIG_ISSUES_H_ */