| // SPDX-License-Identifier: GPL-2.0 | |
| // | |
| // Copyright 2015 Freescale Semiconductor, Inc. | |
| #include <dt-bindings/clock/imx6ul-clock.h> | |
| #include <dt-bindings/gpio/gpio.h> | |
| #include <dt-bindings/input/input.h> | |
| #include <dt-bindings/interrupt-controller/arm-gic.h> | |
| #include "imx6ul-pinfunc.h" | |
| / { | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| /* | |
| * The decompressor and also some bootloaders rely on a | |
| * pre-existing /chosen node to be available to insert the | |
| * command line and merge other ATAGS info. | |
| * Also for U-Boot there must be a pre-existing /memory node. | |
| */ | |
| chosen {}; | |
| memory { device_type = "memory"; }; | |
| aliases { | |
| ethernet0 = &fec1; | |
| ethernet1 = &fec2; | |
| gpio0 = &gpio1; | |
| gpio1 = &gpio2; | |
| gpio2 = &gpio3; | |
| gpio3 = &gpio4; | |
| gpio4 = &gpio5; | |
| i2c0 = &i2c1; | |
| i2c1 = &i2c2; | |
| i2c2 = &i2c3; | |
| i2c3 = &i2c4; | |
| mmc0 = &usdhc1; | |
| mmc1 = &usdhc2; | |
| serial0 = &uart1; | |
| serial1 = &uart2; | |
| serial2 = &uart3; | |
| serial3 = &uart4; | |
| serial4 = &uart5; | |
| serial5 = &uart6; | |
| serial6 = &uart7; | |
| serial7 = &uart8; | |
| sai1 = &sai1; | |
| sai2 = &sai2; | |
| sai3 = &sai3; | |
| spi0 = &ecspi1; | |
| spi1 = &ecspi2; | |
| spi2 = &ecspi3; | |
| spi3 = &ecspi4; | |
| usbphy0 = &usbphy1; | |
| usbphy1 = &usbphy2; | |
| }; | |
| cpus { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| cpu0: cpu@0 { | |
| compatible = "arm,cortex-a7"; | |
| device_type = "cpu"; | |
| reg = <0>; | |
| clock-latency = <61036>; /* two CLK32 periods */ | |
| operating-points = < | |
| /* kHz uV */ | |
| 696000 1275000 | |
| 528000 1175000 | |
| 396000 1025000 | |
| 198000 950000 | |
| >; | |
| fsl,soc-operating-points = < | |
| /* KHz uV */ | |
| 696000 1275000 | |
| 528000 1175000 | |
| 396000 1175000 | |
| 198000 1175000 | |
| >; | |
| clocks = <&clks IMX6UL_CLK_ARM>, | |
| <&clks IMX6UL_CLK_PLL2_BUS>, | |
| <&clks IMX6UL_CLK_PLL2_PFD2>, | |
| <&clks IMX6UL_CA7_SECONDARY_SEL>, | |
| <&clks IMX6UL_CLK_STEP>, | |
| <&clks IMX6UL_CLK_PLL1_SW>, | |
| <&clks IMX6UL_CLK_PLL1_SYS>; | |
| clock-names = "arm", "pll2_bus", "pll2_pfd2_396m", | |
| "secondary_sel", "step", "pll1_sw", | |
| "pll1_sys"; | |
| arm-supply = <®_arm>; | |
| soc-supply = <®_soc>; | |
| }; | |
| }; | |
| intc: interrupt-controller@a01000 { | |
| compatible = "arm,gic-400", "arm,cortex-a7-gic"; | |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; | |
| #interrupt-cells = <3>; | |
| interrupt-controller; | |
| interrupt-parent = <&intc>; | |
| reg = <0x00a01000 0x1000>, | |
| <0x00a02000 0x2000>, | |
| <0x00a04000 0x2000>, | |
| <0x00a06000 0x2000>; | |
| }; | |
| timer { | |
| compatible = "arm,armv7-timer"; | |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, | |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; | |
| interrupt-parent = <&intc>; | |
| status = "disabled"; | |
| }; | |
| ckil: clock-cli { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <32768>; | |
| clock-output-names = "ckil"; | |
| }; | |
| osc: clock-osc { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <24000000>; | |
| clock-output-names = "osc"; | |
| }; | |
| ipp_di0: clock-di0 { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <0>; | |
| clock-output-names = "ipp_di0"; | |
| }; | |
| ipp_di1: clock-di1 { | |
| compatible = "fixed-clock"; | |
| #clock-cells = <0>; | |
| clock-frequency = <0>; | |
| clock-output-names = "ipp_di1"; | |
| }; | |
| tempmon: tempmon { | |
| compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon"; | |
| interrupt-parent = <&gpc>; | |
| interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; | |
| fsl,tempmon = <&anatop>; | |
| nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>; | |
| nvmem-cell-names = "calib", "temp_grade"; | |
| clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>; | |
| }; | |
| pmu { | |
| compatible = "arm,cortex-a7-pmu"; | |
| interrupt-parent = <&gpc>; | |
| interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; | |
| status = "disabled"; | |
| }; | |
| soc { | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| compatible = "simple-bus"; | |
| interrupt-parent = <&gpc>; | |
| ranges; | |
| ocram: sram@900000 { | |
| compatible = "mmio-sram"; | |
| reg = <0x00900000 0x20000>; | |
| }; | |
| dma_apbh: dma-apbh@1804000 { | |
| compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh"; | |
| reg = <0x01804000 0x2000>; | |
| interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
| <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
| <0 13 IRQ_TYPE_LEVEL_HIGH>, | |
| <0 13 IRQ_TYPE_LEVEL_HIGH>; | |
| interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3"; | |
| #dma-cells = <1>; | |
| dma-channels = <4>; | |
| clocks = <&clks IMX6UL_CLK_APBHDMA>; | |
| }; | |
| gpmi: gpmi-nand@1806000 { | |
| compatible = "fsl,imx6q-gpmi-nand"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| reg = <0x01806000 0x2000>, <0x01808000 0x2000>; | |
| reg-names = "gpmi-nand", "bch"; | |
| interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>; | |
| interrupt-names = "bch"; | |
| clocks = <&clks IMX6UL_CLK_GPMI_IO>, | |
| <&clks IMX6UL_CLK_GPMI_APB>, | |
| <&clks IMX6UL_CLK_GPMI_BCH>, | |
| <&clks IMX6UL_CLK_GPMI_BCH_APB>, | |
| <&clks IMX6UL_CLK_PER_BCH>; | |
| clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch", | |
| "gpmi_bch_apb", "per1_bch"; | |
| dmas = <&dma_apbh 0>; | |
| dma-names = "rx-tx"; | |
| status = "disabled"; | |
| }; | |
| aips1: aips-bus@2000000 { | |
| compatible = "fsl,aips-bus", "simple-bus"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| reg = <0x02000000 0x100000>; | |
| ranges; | |
| spba-bus@2000000 { | |
| compatible = "fsl,spba-bus", "simple-bus"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| reg = <0x02000000 0x40000>; | |
| ranges; | |
| ecspi1: ecspi@2008000 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
| reg = <0x02008000 0x4000>; | |
| interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_ECSPI1>, | |
| <&clks IMX6UL_CLK_ECSPI1>; | |
| clock-names = "ipg", "per"; | |
| status = "disabled"; | |
| }; | |
| ecspi2: ecspi@200c000 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
| reg = <0x0200c000 0x4000>; | |
| interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_ECSPI2>, | |
| <&clks IMX6UL_CLK_ECSPI2>; | |
| clock-names = "ipg", "per"; | |
| status = "disabled"; | |
| }; | |
| ecspi3: ecspi@2010000 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
| reg = <0x02010000 0x4000>; | |
| interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_ECSPI3>, | |
| <&clks IMX6UL_CLK_ECSPI3>; | |
| clock-names = "ipg", "per"; | |
| status = "disabled"; | |
| }; | |
| ecspi4: ecspi@2014000 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi"; | |
| reg = <0x02014000 0x4000>; | |
| interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_ECSPI4>, | |
| <&clks IMX6UL_CLK_ECSPI4>; | |
| clock-names = "ipg", "per"; | |
| status = "disabled"; | |
| }; | |
| uart7: serial@2018000 { | |
| compatible = "fsl,imx6ul-uart", | |
| "fsl,imx6q-uart"; | |
| reg = <0x02018000 0x4000>; | |
| interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_UART7_IPG>, | |
| <&clks IMX6UL_CLK_UART7_SERIAL>; | |
| clock-names = "ipg", "per"; | |
| status = "disabled"; | |
| }; | |
| uart1: serial@2020000 { | |
| compatible = "fsl,imx6ul-uart", | |
| "fsl,imx6q-uart"; | |
| reg = <0x02020000 0x4000>; | |
| interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_UART1_IPG>, | |
| <&clks IMX6UL_CLK_UART1_SERIAL>; | |
| clock-names = "ipg", "per"; | |
| status = "disabled"; | |
| }; | |
| uart8: serial@2024000 { | |
| compatible = "fsl,imx6ul-uart", | |
| "fsl,imx6q-uart"; | |
| reg = <0x02024000 0x4000>; | |
| interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_UART8_IPG>, | |
| <&clks IMX6UL_CLK_UART8_SERIAL>; | |
| clock-names = "ipg", "per"; | |
| status = "disabled"; | |
| }; | |
| sai1: sai@2028000 { | |
| #sound-dai-cells = <0>; | |
| compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; | |
| reg = <0x02028000 0x4000>; | |
| interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_SAI1_IPG>, | |
| <&clks IMX6UL_CLK_SAI1>, | |
| <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; | |
| clock-names = "bus", "mclk1", "mclk2", "mclk3"; | |
| dmas = <&sdma 35 24 0>, | |
| <&sdma 36 24 0>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| sai2: sai@202c000 { | |
| #sound-dai-cells = <0>; | |
| compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; | |
| reg = <0x0202c000 0x4000>; | |
| interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_SAI2_IPG>, | |
| <&clks IMX6UL_CLK_SAI2>, | |
| <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; | |
| clock-names = "bus", "mclk1", "mclk2", "mclk3"; | |
| dmas = <&sdma 37 24 0>, | |
| <&sdma 38 24 0>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| sai3: sai@2030000 { | |
| #sound-dai-cells = <0>; | |
| compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai"; | |
| reg = <0x02030000 0x4000>; | |
| interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_SAI3_IPG>, | |
| <&clks IMX6UL_CLK_SAI3>, | |
| <&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>; | |
| clock-names = "bus", "mclk1", "mclk2", "mclk3"; | |
| dmas = <&sdma 39 24 0>, | |
| <&sdma 40 24 0>; | |
| dma-names = "rx", "tx"; | |
| status = "disabled"; | |
| }; | |
| }; | |
| tsc: tsc@2040000 { | |
| compatible = "fsl,imx6ul-tsc"; | |
| reg = <0x02040000 0x4000>, <0x0219c000 0x4000>; | |
| interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_IPG>, | |
| <&clks IMX6UL_CLK_ADC2>; | |
| clock-names = "tsc", "adc"; | |
| status = "disabled"; | |
| }; | |
| pwm1: pwm@2080000 { | |
| compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
| reg = <0x02080000 0x4000>; | |
| interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_PWM1>, | |
| <&clks IMX6UL_CLK_PWM1>; | |
| clock-names = "ipg", "per"; | |
| #pwm-cells = <2>; | |
| status = "disabled"; | |
| }; | |
| pwm2: pwm@2084000 { | |
| compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
| reg = <0x02084000 0x4000>; | |
| interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_PWM2>, | |
| <&clks IMX6UL_CLK_PWM2>; | |
| clock-names = "ipg", "per"; | |
| #pwm-cells = <2>; | |
| status = "disabled"; | |
| }; | |
| pwm3: pwm@2088000 { | |
| compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
| reg = <0x02088000 0x4000>; | |
| interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_PWM3>, | |
| <&clks IMX6UL_CLK_PWM3>; | |
| clock-names = "ipg", "per"; | |
| #pwm-cells = <2>; | |
| status = "disabled"; | |
| }; | |
| pwm4: pwm@208c000 { | |
| compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
| reg = <0x0208c000 0x4000>; | |
| interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_PWM4>, | |
| <&clks IMX6UL_CLK_PWM4>; | |
| clock-names = "ipg", "per"; | |
| #pwm-cells = <2>; | |
| status = "disabled"; | |
| }; | |
| can1: flexcan@2090000 { | |
| compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; | |
| reg = <0x02090000 0x4000>; | |
| interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_CAN1_IPG>, | |
| <&clks IMX6UL_CLK_CAN1_SERIAL>; | |
| clock-names = "ipg", "per"; | |
| status = "disabled"; | |
| }; | |
| can2: flexcan@2094000 { | |
| compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan"; | |
| reg = <0x02094000 0x4000>; | |
| interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_CAN2_IPG>, | |
| <&clks IMX6UL_CLK_CAN2_SERIAL>; | |
| clock-names = "ipg", "per"; | |
| status = "disabled"; | |
| }; | |
| gpt1: gpt@2098000 { | |
| compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; | |
| reg = <0x02098000 0x4000>; | |
| interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_GPT1_BUS>, | |
| <&clks IMX6UL_CLK_GPT1_SERIAL>; | |
| clock-names = "ipg", "per"; | |
| }; | |
| gpio1: gpio@209c000 { | |
| compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
| reg = <0x0209c000 0x4000>; | |
| interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>, | |
| <&iomuxc 16 33 16>; | |
| }; | |
| gpio2: gpio@20a0000 { | |
| compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
| reg = <0x020a0000 0x4000>; | |
| interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>; | |
| }; | |
| gpio3: gpio@20a4000 { | |
| compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
| reg = <0x020a4000 0x4000>; | |
| interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| gpio-ranges = <&iomuxc 0 65 29>; | |
| }; | |
| gpio4: gpio@20a8000 { | |
| compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
| reg = <0x020a8000 0x4000>; | |
| interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>; | |
| }; | |
| gpio5: gpio@20ac000 { | |
| compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio"; | |
| reg = <0x020ac000 0x4000>; | |
| interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; | |
| gpio-controller; | |
| #gpio-cells = <2>; | |
| interrupt-controller; | |
| #interrupt-cells = <2>; | |
| gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>; | |
| }; | |
| fec2: ethernet@20b4000 { | |
| compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; | |
| reg = <0x020b4000 0x4000>; | |
| interrupt-names = "int0", "pps"; | |
| interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_ENET>, | |
| <&clks IMX6UL_CLK_ENET_AHB>, | |
| <&clks IMX6UL_CLK_ENET_PTP>, | |
| <&clks IMX6UL_CLK_ENET2_REF_125M>, | |
| <&clks IMX6UL_CLK_ENET2_REF_125M>; | |
| clock-names = "ipg", "ahb", "ptp", | |
| "enet_clk_ref", "enet_out"; | |
| fsl,num-tx-queues=<1>; | |
| fsl,num-rx-queues=<1>; | |
| status = "disabled"; | |
| }; | |
| kpp: kpp@20b8000 { | |
| compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp"; | |
| reg = <0x020b8000 0x4000>; | |
| interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_KPP>; | |
| status = "disabled"; | |
| }; | |
| wdog1: wdog@20bc000 { | |
| compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; | |
| reg = <0x020bc000 0x4000>; | |
| interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_WDOG1>; | |
| }; | |
| wdog2: wdog@20c0000 { | |
| compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; | |
| reg = <0x020c0000 0x4000>; | |
| interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_WDOG2>; | |
| status = "disabled"; | |
| }; | |
| clks: ccm@20c4000 { | |
| compatible = "fsl,imx6ul-ccm"; | |
| reg = <0x020c4000 0x4000>; | |
| interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>; | |
| #clock-cells = <1>; | |
| clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>; | |
| clock-names = "ckil", "osc", "ipp_di0", "ipp_di1"; | |
| }; | |
| anatop: anatop@20c8000 { | |
| compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop", | |
| "syscon", "simple-bus"; | |
| reg = <0x020c8000 0x1000>; | |
| interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; | |
| reg_3p0: regulator-3p0 { | |
| compatible = "fsl,anatop-regulator"; | |
| regulator-name = "vdd3p0"; | |
| regulator-min-microvolt = <2625000>; | |
| regulator-max-microvolt = <3400000>; | |
| anatop-reg-offset = <0x120>; | |
| anatop-vol-bit-shift = <8>; | |
| anatop-vol-bit-width = <5>; | |
| anatop-min-bit-val = <0>; | |
| anatop-min-voltage = <2625000>; | |
| anatop-max-voltage = <3400000>; | |
| anatop-enable-bit = <0>; | |
| }; | |
| reg_arm: regulator-vddcore { | |
| compatible = "fsl,anatop-regulator"; | |
| regulator-name = "cpu"; | |
| regulator-min-microvolt = <725000>; | |
| regulator-max-microvolt = <1450000>; | |
| regulator-always-on; | |
| anatop-reg-offset = <0x140>; | |
| anatop-vol-bit-shift = <0>; | |
| anatop-vol-bit-width = <5>; | |
| anatop-delay-reg-offset = <0x170>; | |
| anatop-delay-bit-shift = <24>; | |
| anatop-delay-bit-width = <2>; | |
| anatop-min-bit-val = <1>; | |
| anatop-min-voltage = <725000>; | |
| anatop-max-voltage = <1450000>; | |
| }; | |
| reg_soc: regulator-vddsoc { | |
| compatible = "fsl,anatop-regulator"; | |
| regulator-name = "vddsoc"; | |
| regulator-min-microvolt = <725000>; | |
| regulator-max-microvolt = <1450000>; | |
| regulator-always-on; | |
| anatop-reg-offset = <0x140>; | |
| anatop-vol-bit-shift = <18>; | |
| anatop-vol-bit-width = <5>; | |
| anatop-delay-reg-offset = <0x170>; | |
| anatop-delay-bit-shift = <28>; | |
| anatop-delay-bit-width = <2>; | |
| anatop-min-bit-val = <1>; | |
| anatop-min-voltage = <725000>; | |
| anatop-max-voltage = <1450000>; | |
| }; | |
| }; | |
| usbphy1: usbphy@20c9000 { | |
| compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; | |
| reg = <0x020c9000 0x1000>; | |
| interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_USBPHY1>; | |
| phy-3p0-supply = <®_3p0>; | |
| fsl,anatop = <&anatop>; | |
| }; | |
| usbphy2: usbphy@20ca000 { | |
| compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy"; | |
| reg = <0x020ca000 0x1000>; | |
| interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_USBPHY2>; | |
| phy-3p0-supply = <®_3p0>; | |
| fsl,anatop = <&anatop>; | |
| }; | |
| snvs: snvs@20cc000 { | |
| compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd"; | |
| reg = <0x020cc000 0x4000>; | |
| snvs_rtc: snvs-rtc-lp { | |
| compatible = "fsl,sec-v4.0-mon-rtc-lp"; | |
| regmap = <&snvs>; | |
| offset = <0x34>; | |
| interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; | |
| }; | |
| snvs_poweroff: snvs-poweroff { | |
| compatible = "syscon-poweroff"; | |
| regmap = <&snvs>; | |
| offset = <0x38>; | |
| value = <0x60>; | |
| mask = <0x60>; | |
| status = "disabled"; | |
| }; | |
| snvs_pwrkey: snvs-powerkey { | |
| compatible = "fsl,sec-v4.0-pwrkey"; | |
| regmap = <&snvs>; | |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; | |
| linux,keycode = <KEY_POWER>; | |
| wakeup-source; | |
| }; | |
| snvs_lpgpr: snvs-lpgpr { | |
| compatible = "fsl,imx6ul-snvs-lpgpr"; | |
| }; | |
| }; | |
| epit1: epit@20d0000 { | |
| reg = <0x020d0000 0x4000>; | |
| interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; | |
| }; | |
| epit2: epit@20d4000 { | |
| reg = <0x020d4000 0x4000>; | |
| interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; | |
| }; | |
| src: src@20d8000 { | |
| compatible = "fsl,imx6ul-src", "fsl,imx51-src"; | |
| reg = <0x020d8000 0x4000>; | |
| interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; | |
| #reset-cells = <1>; | |
| }; | |
| gpc: gpc@20dc000 { | |
| compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc"; | |
| reg = <0x020dc000 0x4000>; | |
| interrupt-controller; | |
| #interrupt-cells = <3>; | |
| interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>; | |
| interrupt-parent = <&intc>; | |
| }; | |
| iomuxc: iomuxc@20e0000 { | |
| compatible = "fsl,imx6ul-iomuxc"; | |
| reg = <0x020e0000 0x4000>; | |
| }; | |
| gpr: iomuxc-gpr@20e4000 { | |
| compatible = "fsl,imx6ul-iomuxc-gpr", | |
| "fsl,imx6q-iomuxc-gpr", "syscon"; | |
| reg = <0x020e4000 0x4000>; | |
| }; | |
| gpt2: gpt@20e8000 { | |
| compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt"; | |
| reg = <0x020e8000 0x4000>; | |
| interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_GPT2_BUS>, | |
| <&clks IMX6UL_CLK_GPT2_SERIAL>; | |
| clock-names = "ipg", "per"; | |
| }; | |
| sdma: sdma@20ec000 { | |
| compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma", | |
| "fsl,imx35-sdma"; | |
| reg = <0x020ec000 0x4000>; | |
| interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_SDMA>, | |
| <&clks IMX6UL_CLK_SDMA>; | |
| clock-names = "ipg", "ahb"; | |
| #dma-cells = <3>; | |
| fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin"; | |
| }; | |
| pwm5: pwm@20f0000 { | |
| compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
| reg = <0x020f0000 0x4000>; | |
| interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_PWM5>, | |
| <&clks IMX6UL_CLK_PWM5>; | |
| clock-names = "ipg", "per"; | |
| #pwm-cells = <2>; | |
| status = "disabled"; | |
| }; | |
| pwm6: pwm@20f4000 { | |
| compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
| reg = <0x020f4000 0x4000>; | |
| interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_PWM6>, | |
| <&clks IMX6UL_CLK_PWM6>; | |
| clock-names = "ipg", "per"; | |
| #pwm-cells = <2>; | |
| status = "disabled"; | |
| }; | |
| pwm7: pwm@20f8000 { | |
| compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
| reg = <0x020f8000 0x4000>; | |
| interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_PWM7>, | |
| <&clks IMX6UL_CLK_PWM7>; | |
| clock-names = "ipg", "per"; | |
| #pwm-cells = <2>; | |
| status = "disabled"; | |
| }; | |
| pwm8: pwm@20fc000 { | |
| compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm"; | |
| reg = <0x020fc000 0x4000>; | |
| interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_PWM8>, | |
| <&clks IMX6UL_CLK_PWM8>; | |
| clock-names = "ipg", "per"; | |
| #pwm-cells = <2>; | |
| status = "disabled"; | |
| }; | |
| }; | |
| aips2: aips-bus@2100000 { | |
| compatible = "fsl,aips-bus", "simple-bus"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| reg = <0x02100000 0x100000>; | |
| ranges; | |
| crypto: caam@2140000 { | |
| compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0"; | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| reg = <0x2140000 0x3c000>; | |
| ranges = <0 0x2140000 0x3c000>; | |
| interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>, | |
| <&clks IMX6UL_CLK_CAAM_MEM>; | |
| clock-names = "ipg", "aclk", "mem"; | |
| sec_jr0: jr0@1000 { | |
| compatible = "fsl,sec-v4.0-job-ring"; | |
| reg = <0x1000 0x1000>; | |
| interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; | |
| }; | |
| sec_jr1: jr1@2000 { | |
| compatible = "fsl,sec-v4.0-job-ring"; | |
| reg = <0x2000 0x1000>; | |
| interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>; | |
| }; | |
| sec_jr2: jr2@3000 { | |
| compatible = "fsl,sec-v4.0-job-ring"; | |
| reg = <0x3000 0x1000>; | |
| interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; | |
| }; | |
| }; | |
| usbotg1: usb@2184000 { | |
| compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; | |
| reg = <0x02184000 0x200>; | |
| interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_USBOH3>; | |
| fsl,usbphy = <&usbphy1>; | |
| fsl,usbmisc = <&usbmisc 0>; | |
| fsl,anatop = <&anatop>; | |
| ahb-burst-config = <0x0>; | |
| tx-burst-size-dword = <0x10>; | |
| rx-burst-size-dword = <0x10>; | |
| status = "disabled"; | |
| }; | |
| usbotg2: usb@2184200 { | |
| compatible = "fsl,imx6ul-usb", "fsl,imx27-usb"; | |
| reg = <0x02184200 0x200>; | |
| interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_USBOH3>; | |
| fsl,usbphy = <&usbphy2>; | |
| fsl,usbmisc = <&usbmisc 1>; | |
| ahb-burst-config = <0x0>; | |
| tx-burst-size-dword = <0x10>; | |
| rx-burst-size-dword = <0x10>; | |
| status = "disabled"; | |
| }; | |
| usbmisc: usbmisc@2184800 { | |
| #index-cells = <1>; | |
| compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc"; | |
| reg = <0x02184800 0x200>; | |
| }; | |
| fec1: ethernet@2188000 { | |
| compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec"; | |
| reg = <0x02188000 0x4000>; | |
| interrupt-names = "int0", "pps"; | |
| interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, | |
| <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_ENET>, | |
| <&clks IMX6UL_CLK_ENET_AHB>, | |
| <&clks IMX6UL_CLK_ENET_PTP>, | |
| <&clks IMX6UL_CLK_ENET_REF>, | |
| <&clks IMX6UL_CLK_ENET_REF>; | |
| clock-names = "ipg", "ahb", "ptp", | |
| "enet_clk_ref", "enet_out"; | |
| fsl,num-tx-queues=<1>; | |
| fsl,num-rx-queues=<1>; | |
| status = "disabled"; | |
| }; | |
| usdhc1: usdhc@2190000 { | |
| compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; | |
| reg = <0x02190000 0x4000>; | |
| interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_USDHC1>, | |
| <&clks IMX6UL_CLK_USDHC1>, | |
| <&clks IMX6UL_CLK_USDHC1>; | |
| clock-names = "ipg", "ahb", "per"; | |
| bus-width = <4>; | |
| status = "disabled"; | |
| }; | |
| usdhc2: usdhc@2194000 { | |
| compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc"; | |
| reg = <0x02194000 0x4000>; | |
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_USDHC2>, | |
| <&clks IMX6UL_CLK_USDHC2>, | |
| <&clks IMX6UL_CLK_USDHC2>; | |
| clock-names = "ipg", "ahb", "per"; | |
| bus-width = <4>; | |
| status = "disabled"; | |
| }; | |
| adc1: adc@2198000 { | |
| compatible = "fsl,imx6ul-adc", "fsl,vf610-adc"; | |
| reg = <0x02198000 0x4000>; | |
| interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_ADC1>; | |
| num-channels = <2>; | |
| clock-names = "adc"; | |
| fsl,adck-max-frequency = <30000000>, <40000000>, | |
| <20000000>; | |
| status = "disabled"; | |
| }; | |
| i2c1: i2c@21a0000 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; | |
| reg = <0x021a0000 0x4000>; | |
| interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_I2C1>; | |
| status = "disabled"; | |
| }; | |
| i2c2: i2c@21a4000 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; | |
| reg = <0x021a4000 0x4000>; | |
| interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_I2C2>; | |
| status = "disabled"; | |
| }; | |
| i2c3: i2c@21a8000 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; | |
| reg = <0x021a8000 0x4000>; | |
| interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_I2C3>; | |
| status = "disabled"; | |
| }; | |
| mmdc: mmdc@21b0000 { | |
| compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc"; | |
| reg = <0x021b0000 0x4000>; | |
| }; | |
| ocotp: ocotp-ctrl@21bc000 { | |
| #address-cells = <1>; | |
| #size-cells = <1>; | |
| compatible = "fsl,imx6ul-ocotp", "syscon"; | |
| reg = <0x021bc000 0x4000>; | |
| clocks = <&clks IMX6UL_CLK_OCOTP>; | |
| tempmon_calib: calib@38 { | |
| reg = <0x38 4>; | |
| }; | |
| tempmon_temp_grade: temp-grade@20 { | |
| reg = <0x20 4>; | |
| }; | |
| }; | |
| lcdif: lcdif@21c8000 { | |
| compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif"; | |
| reg = <0x021c8000 0x4000>; | |
| interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_LCDIF_PIX>, | |
| <&clks IMX6UL_CLK_LCDIF_APB>, | |
| <&clks IMX6UL_CLK_DUMMY>; | |
| clock-names = "pix", "axi", "disp_axi"; | |
| status = "disabled"; | |
| }; | |
| qspi: qspi@21e0000 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi"; | |
| reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>; | |
| reg-names = "QuadSPI", "QuadSPI-memory"; | |
| interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_QSPI>, | |
| <&clks IMX6UL_CLK_QSPI>; | |
| clock-names = "qspi_en", "qspi"; | |
| status = "disabled"; | |
| }; | |
| wdog3: wdog@21e4000 { | |
| compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt"; | |
| reg = <0x021e4000 0x4000>; | |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_WDOG3>; | |
| status = "disabled"; | |
| }; | |
| uart2: serial@21e8000 { | |
| compatible = "fsl,imx6ul-uart", | |
| "fsl,imx6q-uart"; | |
| reg = <0x021e8000 0x4000>; | |
| interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_UART2_IPG>, | |
| <&clks IMX6UL_CLK_UART2_SERIAL>; | |
| clock-names = "ipg", "per"; | |
| status = "disabled"; | |
| }; | |
| uart3: serial@21ec000 { | |
| compatible = "fsl,imx6ul-uart", | |
| "fsl,imx6q-uart"; | |
| reg = <0x021ec000 0x4000>; | |
| interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_UART3_IPG>, | |
| <&clks IMX6UL_CLK_UART3_SERIAL>; | |
| clock-names = "ipg", "per"; | |
| status = "disabled"; | |
| }; | |
| uart4: serial@21f0000 { | |
| compatible = "fsl,imx6ul-uart", | |
| "fsl,imx6q-uart"; | |
| reg = <0x021f0000 0x4000>; | |
| interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_UART4_IPG>, | |
| <&clks IMX6UL_CLK_UART4_SERIAL>; | |
| clock-names = "ipg", "per"; | |
| status = "disabled"; | |
| }; | |
| uart5: serial@21f4000 { | |
| compatible = "fsl,imx6ul-uart", | |
| "fsl,imx6q-uart"; | |
| reg = <0x021f4000 0x4000>; | |
| interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_UART5_IPG>, | |
| <&clks IMX6UL_CLK_UART5_SERIAL>; | |
| clock-names = "ipg", "per"; | |
| status = "disabled"; | |
| }; | |
| i2c4: i2c@21f8000 { | |
| #address-cells = <1>; | |
| #size-cells = <0>; | |
| compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c"; | |
| reg = <0x021f8000 0x4000>; | |
| interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_I2C4>; | |
| status = "disabled"; | |
| }; | |
| uart6: serial@21fc000 { | |
| compatible = "fsl,imx6ul-uart", | |
| "fsl,imx6q-uart"; | |
| reg = <0x021fc000 0x4000>; | |
| interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; | |
| clocks = <&clks IMX6UL_CLK_UART6_IPG>, | |
| <&clks IMX6UL_CLK_UART6_SERIAL>; | |
| clock-names = "ipg", "per"; | |
| status = "disabled"; | |
| }; | |
| }; | |
| }; | |
| }; |