| [ |
| { |
| "EventCode": "0x24", |
| "UMask": "0x21", |
| "BriefDescription": "Demand Data Read miss L2, no rejects", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", |
| "Errata": "HSD78", |
| "PublicDescription": "Demand data read requests that missed L2, no rejects.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x24", |
| "UMask": "0x22", |
| "BriefDescription": "RFO requests that miss L2 cache", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_RQSTS.RFO_MISS", |
| "PublicDescription": "Counts the number of store RFO requests that miss the L2 cache.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x24", |
| "UMask": "0x24", |
| "BriefDescription": "L2 cache misses when fetching instructions", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_RQSTS.CODE_RD_MISS", |
| "PublicDescription": "Number of instruction fetches that missed the L2 cache.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x24", |
| "UMask": "0x27", |
| "BriefDescription": "Demand requests that miss L2 cache", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_RQSTS.ALL_DEMAND_MISS", |
| "Errata": "HSD78", |
| "PublicDescription": "Demand requests that miss L2 cache.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x24", |
| "UMask": "0x30", |
| "BriefDescription": "L2 prefetch requests that miss L2 cache", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_RQSTS.L2_PF_MISS", |
| "PublicDescription": "Counts all L2 HW prefetcher requests that missed L2.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x24", |
| "UMask": "0x3f", |
| "BriefDescription": "All requests that miss L2 cache", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_RQSTS.MISS", |
| "Errata": "HSD78", |
| "PublicDescription": "All requests that missed L2.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x24", |
| "UMask": "0x41", |
| "BriefDescription": "Demand Data Read requests that hit L2 cache", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", |
| "Errata": "HSD78", |
| "PublicDescription": "Demand data read requests that hit L2 cache.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x24", |
| "UMask": "0x42", |
| "BriefDescription": "RFO requests that hit L2 cache", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_RQSTS.RFO_HIT", |
| "PublicDescription": "Counts the number of store RFO requests that hit the L2 cache.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x24", |
| "UMask": "0x44", |
| "BriefDescription": "L2 cache hits when fetching instructions, code reads.", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_RQSTS.CODE_RD_HIT", |
| "PublicDescription": "Number of instruction fetches that hit the L2 cache.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x24", |
| "UMask": "0x50", |
| "BriefDescription": "L2 prefetch requests that hit L2 cache", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_RQSTS.L2_PF_HIT", |
| "PublicDescription": "Counts all L2 HW prefetcher requests that hit L2.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x24", |
| "UMask": "0xe1", |
| "BriefDescription": "Demand Data Read requests", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", |
| "Errata": "HSD78", |
| "PublicDescription": "Counts any demand and L1 HW prefetch data load requests to L2.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x24", |
| "UMask": "0xe2", |
| "BriefDescription": "RFO requests to L2 cache", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_RQSTS.ALL_RFO", |
| "PublicDescription": "Counts all L2 store RFO requests.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x24", |
| "UMask": "0xe4", |
| "BriefDescription": "L2 code requests", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_RQSTS.ALL_CODE_RD", |
| "PublicDescription": "Counts all L2 code requests.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x24", |
| "UMask": "0xe7", |
| "BriefDescription": "Demand requests to L2 cache", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", |
| "Errata": "HSD78", |
| "PublicDescription": "Demand requests to L2 cache.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x24", |
| "UMask": "0xf8", |
| "BriefDescription": "Requests from L2 hardware prefetchers", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_RQSTS.ALL_PF", |
| "PublicDescription": "Counts all L2 HW prefetcher requests.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x24", |
| "UMask": "0xff", |
| "BriefDescription": "All L2 requests", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_RQSTS.REFERENCES", |
| "Errata": "HSD78", |
| "PublicDescription": "All requests to L2 cache.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x27", |
| "UMask": "0x50", |
| "BriefDescription": "Not rejected writebacks that hit L2 cache", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_DEMAND_RQSTS.WB_HIT", |
| "PublicDescription": "Not rejected writebacks that hit L2 cache.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x2E", |
| "UMask": "0x41", |
| "BriefDescription": "Core-originated cacheable demand requests missed L3", |
| "Counter": "0,1,2,3", |
| "EventName": "LONGEST_LAT_CACHE.MISS", |
| "PublicDescription": "This event counts each cache miss condition for references to the last level cache.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x2E", |
| "UMask": "0x4f", |
| "BriefDescription": "Core-originated cacheable demand requests that refer to L3", |
| "Counter": "0,1,2,3", |
| "EventName": "LONGEST_LAT_CACHE.REFERENCE", |
| "PublicDescription": "This event counts requests originating from the core that reference a cache line in the last level cache.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x48", |
| "UMask": "0x1", |
| "BriefDescription": "L1D miss oustandings duration in cycles", |
| "Counter": "2", |
| "EventName": "L1D_PEND_MISS.PENDING", |
| "PublicDescription": "Increments the number of outstanding L1D misses every cycle. Set Cmask = 1 and Edge =1 to count occurrences.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "2" |
| }, |
| { |
| "EventCode": "0x48", |
| "UMask": "0x1", |
| "BriefDescription": "Cycles with L1D load Misses outstanding.", |
| "Counter": "2", |
| "EventName": "L1D_PEND_MISS.PENDING_CYCLES", |
| "CounterMask": "1", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "2" |
| }, |
| { |
| "EventCode": "0x48", |
| "UMask": "0x1", |
| "BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.", |
| "Counter": "2", |
| "EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY", |
| "AnyThread": "1", |
| "CounterMask": "1", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "2" |
| }, |
| { |
| "EventCode": "0x48", |
| "UMask": "0x2", |
| "BriefDescription": "Number of times a request needed a FB entry but there was no entry available for it. That is the FB unavailability was dominant reason for blocking the request. A request includes cacheable/uncacheable demands that is load, store or SW prefetch. HWP are e.", |
| "Counter": "0,1,2,3", |
| "EventName": "L1D_PEND_MISS.REQUEST_FB_FULL", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x48", |
| "UMask": "0x2", |
| "BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.", |
| "Counter": "0,1,2,3", |
| "EventName": "L1D_PEND_MISS.FB_FULL", |
| "CounterMask": "1", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x51", |
| "UMask": "0x1", |
| "BriefDescription": "L1D data line replacements", |
| "Counter": "0,1,2,3", |
| "EventName": "L1D.REPLACEMENT", |
| "PublicDescription": "This event counts when new data lines are brought into the L1 Data cache, which cause other lines to be evicted from the cache.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x60", |
| "UMask": "0x1", |
| "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD", |
| "Errata": "HSD78, HSD62, HSD61", |
| "PublicDescription": "Offcore outstanding demand data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x60", |
| "UMask": "0x1", |
| "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore.", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD", |
| "CounterMask": "1", |
| "Errata": "HSD78, HSD62, HSD61", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x60", |
| "UMask": "0x1", |
| "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6", |
| "CounterMask": "6", |
| "Errata": "HSD78, HSD62, HSD61", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x60", |
| "UMask": "0x2", |
| "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD", |
| "Errata": "HSD62, HSD61", |
| "PublicDescription": "Offcore outstanding Demand code Read transactions in SQ to uncore. Set Cmask=1 to count cycles.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x60", |
| "UMask": "0x4", |
| "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO", |
| "Errata": "HSD62, HSD61", |
| "PublicDescription": "Offcore outstanding RFO store transactions in SQ to uncore. Set Cmask=1 to count cycles.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x60", |
| "UMask": "0x4", |
| "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle.", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO", |
| "CounterMask": "1", |
| "Errata": "HSD62, HSD61", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x60", |
| "UMask": "0x8", |
| "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD", |
| "Errata": "HSD62, HSD61", |
| "PublicDescription": "Offcore outstanding cacheable data read transactions in SQ to uncore. Set Cmask=1 to count cycles.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x60", |
| "UMask": "0x8", |
| "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD", |
| "CounterMask": "1", |
| "Errata": "HSD62, HSD61", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0x63", |
| "UMask": "0x2", |
| "BriefDescription": "Cycles when L1D is locked", |
| "Counter": "0,1,2,3", |
| "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION", |
| "PublicDescription": "Cycles in which the L1D is locked.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xB0", |
| "UMask": "0x1", |
| "BriefDescription": "Demand Data Read requests sent to uncore", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", |
| "Errata": "HSD78", |
| "PublicDescription": "Demand data read requests sent to uncore.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xB0", |
| "UMask": "0x2", |
| "BriefDescription": "Cacheable and noncachaeble code read requests", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", |
| "PublicDescription": "Demand code read requests sent to uncore.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xB0", |
| "UMask": "0x4", |
| "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_REQUESTS.DEMAND_RFO", |
| "PublicDescription": "Demand RFO read requests sent to uncore, including regular RFOs, locks, ItoM.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xB0", |
| "UMask": "0x8", |
| "BriefDescription": "Demand and prefetch data reads", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", |
| "PublicDescription": "Data read requests sent to uncore (demand and prefetch).", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xb2", |
| "UMask": "0x1", |
| "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD0", |
| "UMask": "0x11", |
| "BriefDescription": "Retired load uops that miss the STLB. (precise Event)", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", |
| "Errata": "HSD29, HSM30", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD0", |
| "UMask": "0x12", |
| "BriefDescription": "Retired store uops that miss the STLB. (precise Event)", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", |
| "Errata": "HSD29, HSM30", |
| "L1_Hit_Indication": "1", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD0", |
| "UMask": "0x21", |
| "BriefDescription": "Retired load uops with locked access. (precise Event)", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS", |
| "Errata": "HSD76, HSD29, HSM30", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD0", |
| "UMask": "0x41", |
| "BriefDescription": "Retired load uops that split across a cacheline boundary. (precise Event)", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", |
| "Errata": "HSD29, HSM30", |
| "PublicDescription": "This event counts load uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD0", |
| "UMask": "0x42", |
| "BriefDescription": "Retired store uops that split across a cacheline boundary. (precise Event)", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES", |
| "Errata": "HSD29, HSM30", |
| "L1_Hit_Indication": "1", |
| "PublicDescription": "This event counts store uops retired which had memory addresses spilt across 2 cache lines. A line split is across 64B cache-lines which may include a page split (4K). This is a precise event.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD0", |
| "UMask": "0x81", |
| "BriefDescription": "All retired load uops. (precise Event)", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_UOPS_RETIRED.ALL_LOADS", |
| "Errata": "HSD29, HSM30", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD0", |
| "UMask": "0x82", |
| "BriefDescription": "All retired store uops. (precise Event)", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_UOPS_RETIRED.ALL_STORES", |
| "Errata": "HSD29, HSM30", |
| "L1_Hit_Indication": "1", |
| "PublicDescription": "This event counts all store uops retired. This is a precise event.", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD1", |
| "UMask": "0x1", |
| "BriefDescription": "Retired load uops with L1 cache hits as data sources.", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", |
| "Errata": "HSD29, HSM30", |
| "SampleAfterValue": "2000003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD1", |
| "UMask": "0x2", |
| "BriefDescription": "Retired load uops with L2 cache hits as data sources.", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", |
| "Errata": "HSD76, HSD29, HSM30", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD1", |
| "UMask": "0x4", |
| "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT", |
| "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", |
| "PublicDescription": "This event counts retired load uops in which data sources were data hits in the L3 cache without snoops required. This does not include hardware prefetches. This is a precise event.", |
| "SampleAfterValue": "50021", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD1", |
| "UMask": "0x8", |
| "BriefDescription": "Retired load uops misses in L1 cache as data sources.", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", |
| "Errata": "HSM30", |
| "PublicDescription": "This event counts retired load uops in which data sources missed in the L1 cache. This does not include hardware prefetches. This is a precise event.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD1", |
| "UMask": "0x10", |
| "BriefDescription": "Retired load uops with L2 cache misses as data sources.", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS", |
| "Errata": "HSD29, HSM30", |
| "SampleAfterValue": "50021", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD1", |
| "UMask": "0x20", |
| "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source.", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", |
| "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD1", |
| "UMask": "0x40", |
| "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready.", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", |
| "Errata": "HSM30", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD2", |
| "UMask": "0x1", |
| "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache.", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", |
| "Errata": "HSD29, HSD25, HSM26, HSM30", |
| "SampleAfterValue": "20011", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD2", |
| "UMask": "0x2", |
| "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. ", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", |
| "Errata": "HSD29, HSD25, HSM26, HSM30", |
| "PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HIT in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.", |
| "SampleAfterValue": "20011", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD2", |
| "UMask": "0x4", |
| "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. ", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", |
| "Errata": "HSD29, HSD25, HSM26, HSM30", |
| "PublicDescription": "This event counts retired load uops that hit in the L3 cache, but required a cross-core snoop which resulted in a HITM (hit modified) in an on-pkg core cache. This does not include hardware prefetches. This is a precise event.", |
| "SampleAfterValue": "20011", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD2", |
| "UMask": "0x8", |
| "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required.", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE", |
| "Errata": "HSD74, HSD29, HSD25, HSM26, HSM30", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD3", |
| "UMask": "0x1", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", |
| "Errata": "HSD74, HSD29, HSD25, HSM30", |
| "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD3", |
| "UMask": "0x4", |
| "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", |
| "Errata": "HSD29, HSM30", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD3", |
| "UMask": "0x10", |
| "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM (Precise Event)", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", |
| "Errata": "HSM30", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xD3", |
| "UMask": "0x20", |
| "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)", |
| "Data_LA": "1", |
| "PEBS": "1", |
| "Counter": "0,1,2,3", |
| "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", |
| "Errata": "HSM30", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "EventCode": "0xf0", |
| "UMask": "0x1", |
| "BriefDescription": "Demand Data Read requests that access L2 cache", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_TRANS.DEMAND_DATA_RD", |
| "PublicDescription": "Demand data read requests that access L2 cache.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xf0", |
| "UMask": "0x2", |
| "BriefDescription": "RFO requests that access L2 cache", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_TRANS.RFO", |
| "PublicDescription": "RFO requests that access L2 cache.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xf0", |
| "UMask": "0x4", |
| "BriefDescription": "L2 cache accesses when fetching instructions", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_TRANS.CODE_RD", |
| "PublicDescription": "L2 cache accesses when fetching instructions.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xf0", |
| "UMask": "0x8", |
| "BriefDescription": "L2 or L3 HW prefetches that access L2 cache", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_TRANS.ALL_PF", |
| "PublicDescription": "Any MLC or L3 HW prefetch accessing L2, including rejects.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xf0", |
| "UMask": "0x10", |
| "BriefDescription": "L1D writebacks that access L2 cache", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_TRANS.L1D_WB", |
| "PublicDescription": "L1D writebacks that access L2 cache.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xf0", |
| "UMask": "0x20", |
| "BriefDescription": "L2 fill requests that access L2 cache", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_TRANS.L2_FILL", |
| "PublicDescription": "L2 fill requests that access L2 cache.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xf0", |
| "UMask": "0x40", |
| "BriefDescription": "L2 writebacks that access L2 cache", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_TRANS.L2_WB", |
| "PublicDescription": "L2 writebacks that access L2 cache.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xf0", |
| "UMask": "0x80", |
| "BriefDescription": "Transactions accessing L2 pipe", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_TRANS.ALL_REQUESTS", |
| "PublicDescription": "Transactions accessing L2 pipe.", |
| "SampleAfterValue": "200003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xF1", |
| "UMask": "0x1", |
| "BriefDescription": "L2 cache lines in I state filling L2", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_LINES_IN.I", |
| "PublicDescription": "L2 cache lines in I state filling L2.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xF1", |
| "UMask": "0x2", |
| "BriefDescription": "L2 cache lines in S state filling L2", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_LINES_IN.S", |
| "PublicDescription": "L2 cache lines in S state filling L2.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xF1", |
| "UMask": "0x4", |
| "BriefDescription": "L2 cache lines in E state filling L2", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_LINES_IN.E", |
| "PublicDescription": "L2 cache lines in E state filling L2.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xF1", |
| "UMask": "0x7", |
| "BriefDescription": "L2 cache lines filling L2", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_LINES_IN.ALL", |
| "PublicDescription": "This event counts the number of L2 cache lines brought into the L2 cache. Lines are filled into the L2 cache when there was an L2 miss.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xF2", |
| "UMask": "0x5", |
| "BriefDescription": "Clean L2 cache lines evicted by demand", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_LINES_OUT.DEMAND_CLEAN", |
| "PublicDescription": "Clean L2 cache lines evicted by demand.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xF2", |
| "UMask": "0x6", |
| "BriefDescription": "Dirty L2 cache lines evicted by demand", |
| "Counter": "0,1,2,3", |
| "EventName": "L2_LINES_OUT.DEMAND_DIRTY", |
| "PublicDescription": "Dirty L2 cache lines evicted by demand.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "EventCode": "0xf4", |
| "UMask": "0x10", |
| "BriefDescription": "Split locks in SQ", |
| "Counter": "0,1,2,3", |
| "EventName": "SQ_MISC.SPLIT_LOCK", |
| "PublicDescription": "", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3,4,5,6,7" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", |
| "MSRValue": "0x04003c0001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts demand data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", |
| "MSRValue": "0x10003c0001", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts demand data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", |
| "MSRValue": "0x04003c0002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", |
| "MSRValue": "0x10003c0002", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts all demand data writes (RFOs) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", |
| "MSRValue": "0x04003c0004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts all demand code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", |
| "MSRValue": "0x10003c0004", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts all demand code reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3", |
| "MSRValue": "0x3f803c0010", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.PF_L2_DATA_RD.LLC_HIT.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts prefetch (that bring data to L2) data reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3", |
| "MSRValue": "0x3f803c0020", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.PF_L2_RFO.LLC_HIT.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts all prefetch (that bring data to L2) RFOs that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3", |
| "MSRValue": "0x3f803c0040", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.PF_L2_CODE_RD.LLC_HIT.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3", |
| "MSRValue": "0x3f803c0080", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.PF_LLC_DATA_RD.LLC_HIT.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3", |
| "MSRValue": "0x3f803c0100", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.PF_LLC_RFO.LLC_HIT.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3", |
| "MSRValue": "0x3f803c0200", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.PF_LLC_CODE_RD.LLC_HIT.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts prefetch (that bring data to LLC only) code reads that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", |
| "MSRValue": "0x04003c0091", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", |
| "MSRValue": "0x10003c0091", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts all demand & prefetch data reads that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", |
| "MSRValue": "0x04003c0122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", |
| "MSRValue": "0x10003c0122", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts all demand & prefetch RFOs that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", |
| "MSRValue": "0x04003c0244", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts all demand & prefetch code reads that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded", |
| "MSRValue": "0x04003c07f7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded", |
| "MSRValue": "0x10003c07f7", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HITM_OTHER_CORE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) that hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| }, |
| { |
| "Offcore": "1", |
| "EventCode": "0xB7, 0xBB", |
| "UMask": "0x1", |
| "BriefDescription": "Counts all requests that hit in the L3", |
| "MSRValue": "0x3f803c8fff", |
| "Counter": "0,1,2,3", |
| "EventName": "OFFCORE_RESPONSE.ALL_REQUESTS.LLC_HIT.ANY_RESPONSE", |
| "MSRIndex": "0x1a6,0x1a7", |
| "PublicDescription": "Counts all requests that hit in the L3 Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.", |
| "SampleAfterValue": "100003", |
| "CounterHTOff": "0,1,2,3" |
| } |
| ] |
