blob: 2005f032c02f0ad3b9628f1f9d7f22023f442dd1 [file] [log] [blame]
Tero Kristo21876ea2013-07-18 15:57:51 +03001/*
2 * OMAP4 Clock init
3 *
4 * Copyright (C) 2013 Texas Instruments, Inc.
5 *
6 * Tero Kristo (t-kristo@ti.com)
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
11 */
12
13#include <linux/kernel.h>
14#include <linux/list.h>
Stephen Boyde3870882015-01-22 15:40:20 -080015#include <linux/clk.h>
Tero Kristo21876ea2013-07-18 15:57:51 +030016#include <linux/clkdev.h>
17#include <linux/clk/ti.h>
Tero Kristo1c881b52017-02-09 11:34:23 +020018#include <dt-bindings/clock/omap4.h>
Tero Kristo21876ea2013-07-18 15:57:51 +030019
Tero Kristoa3314e92015-03-04 21:02:05 +020020#include "clock.h"
21
Tero Kristo21876ea2013-07-18 15:57:51 +030022/*
23 * OMAP4 ABE DPLL default frequency. In OMAP4460 TRM version V, section
24 * "3.6.3.2.3 CM1_ABE Clock Generator" states that the "DPLL_ABE_X2_CLK
25 * must be set to 196.608 MHz" and hence, the DPLL locked frequency is
26 * half of this value.
27 */
28#define OMAP4_DPLL_ABE_DEFFREQ 98304000
29
30/*
31 * OMAP4 USB DPLL default frequency. In OMAP4430 TRM version V, section
32 * "3.6.3.9.5 DPLL_USB Preferred Settings" shows that the preferred
33 * locked frequency for the USB DPLL is 960MHz.
34 */
35#define OMAP4_DPLL_USB_DEFFREQ 960000000
36
Tero Kristo1c881b52017-02-09 11:34:23 +020037static const struct omap_clkctrl_reg_data omap4_mpuss_clkctrl_regs[] __initconst = {
38 { OMAP4_MPU_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_mpu_m2_ck" },
39 { 0 },
40};
41
42static const struct omap_clkctrl_reg_data omap4_tesla_clkctrl_regs[] __initconst = {
43 { OMAP4_DSP_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m4x2_ck" },
44 { 0 },
45};
46
47static const char * const omap4_aess_fclk_parents[] __initconst = {
48 "abe_clk",
49 NULL,
50};
51
52static const struct omap_clkctrl_div_data omap4_aess_fclk_data __initconst = {
53 .max_div = 2,
54};
55
56static const struct omap_clkctrl_bit_data omap4_aess_bit_data[] __initconst = {
57 { 24, TI_CLK_DIVIDER, omap4_aess_fclk_parents, &omap4_aess_fclk_data },
58 { 0 },
59};
60
61static const char * const omap4_func_dmic_abe_gfclk_parents[] __initconst = {
62 "dmic_sync_mux_ck",
63 "pad_clks_ck",
64 "slimbus_clk",
65 NULL,
66};
67
68static const char * const omap4_dmic_sync_mux_ck_parents[] __initconst = {
69 "abe_24m_fclk",
70 "syc_clk_div_ck",
71 "func_24m_clk",
72 NULL,
73};
74
75static const struct omap_clkctrl_bit_data omap4_dmic_bit_data[] __initconst = {
76 { 24, TI_CLK_MUX, omap4_func_dmic_abe_gfclk_parents, NULL },
77 { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
78 { 0 },
79};
80
81static const char * const omap4_func_mcasp_abe_gfclk_parents[] __initconst = {
82 "mcasp_sync_mux_ck",
83 "pad_clks_ck",
84 "slimbus_clk",
85 NULL,
86};
87
88static const struct omap_clkctrl_bit_data omap4_mcasp_bit_data[] __initconst = {
89 { 24, TI_CLK_MUX, omap4_func_mcasp_abe_gfclk_parents, NULL },
90 { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
91 { 0 },
92};
93
94static const char * const omap4_func_mcbsp1_gfclk_parents[] __initconst = {
95 "mcbsp1_sync_mux_ck",
96 "pad_clks_ck",
97 "slimbus_clk",
98 NULL,
99};
100
101static const struct omap_clkctrl_bit_data omap4_mcbsp1_bit_data[] __initconst = {
102 { 24, TI_CLK_MUX, omap4_func_mcbsp1_gfclk_parents, NULL },
103 { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
104 { 0 },
105};
106
107static const char * const omap4_func_mcbsp2_gfclk_parents[] __initconst = {
108 "mcbsp2_sync_mux_ck",
109 "pad_clks_ck",
110 "slimbus_clk",
111 NULL,
112};
113
114static const struct omap_clkctrl_bit_data omap4_mcbsp2_bit_data[] __initconst = {
115 { 24, TI_CLK_MUX, omap4_func_mcbsp2_gfclk_parents, NULL },
116 { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
117 { 0 },
118};
119
120static const char * const omap4_func_mcbsp3_gfclk_parents[] __initconst = {
121 "mcbsp3_sync_mux_ck",
122 "pad_clks_ck",
123 "slimbus_clk",
124 NULL,
125};
126
127static const struct omap_clkctrl_bit_data omap4_mcbsp3_bit_data[] __initconst = {
128 { 24, TI_CLK_MUX, omap4_func_mcbsp3_gfclk_parents, NULL },
129 { 26, TI_CLK_MUX, omap4_dmic_sync_mux_ck_parents, NULL },
130 { 0 },
131};
132
133static const char * const omap4_slimbus1_fclk_0_parents[] __initconst = {
134 "abe_24m_fclk",
135 NULL,
136};
137
138static const char * const omap4_slimbus1_fclk_1_parents[] __initconst = {
139 "func_24m_clk",
140 NULL,
141};
142
143static const char * const omap4_slimbus1_fclk_2_parents[] __initconst = {
144 "pad_clks_ck",
145 NULL,
146};
147
148static const char * const omap4_slimbus1_slimbus_clk_parents[] __initconst = {
149 "slimbus_clk",
150 NULL,
151};
152
153static const struct omap_clkctrl_bit_data omap4_slimbus1_bit_data[] __initconst = {
154 { 8, TI_CLK_GATE, omap4_slimbus1_fclk_0_parents, NULL },
155 { 9, TI_CLK_GATE, omap4_slimbus1_fclk_1_parents, NULL },
156 { 10, TI_CLK_GATE, omap4_slimbus1_fclk_2_parents, NULL },
157 { 11, TI_CLK_GATE, omap4_slimbus1_slimbus_clk_parents, NULL },
158 { 0 },
159};
160
161static const char * const omap4_timer5_sync_mux_parents[] __initconst = {
162 "syc_clk_div_ck",
163 "sys_32k_ck",
164 NULL,
165};
166
167static const struct omap_clkctrl_bit_data omap4_timer5_bit_data[] __initconst = {
168 { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
169 { 0 },
170};
171
172static const struct omap_clkctrl_bit_data omap4_timer6_bit_data[] __initconst = {
173 { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
174 { 0 },
175};
176
177static const struct omap_clkctrl_bit_data omap4_timer7_bit_data[] __initconst = {
178 { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
179 { 0 },
180};
181
182static const struct omap_clkctrl_bit_data omap4_timer8_bit_data[] __initconst = {
183 { 24, TI_CLK_MUX, omap4_timer5_sync_mux_parents, NULL },
184 { 0 },
185};
186
187static const struct omap_clkctrl_reg_data omap4_abe_clkctrl_regs[] __initconst = {
188 { OMAP4_L4_ABE_CLKCTRL, NULL, 0, "ocp_abe_iclk" },
189 { OMAP4_AESS_CLKCTRL, omap4_aess_bit_data, CLKF_SW_SUP, "aess_fclk" },
190 { OMAP4_MCPDM_CLKCTRL, NULL, CLKF_SW_SUP, "pad_clks_ck" },
191 { OMAP4_DMIC_CLKCTRL, omap4_dmic_bit_data, CLKF_SW_SUP, "func_dmic_abe_gfclk" },
192 { OMAP4_MCASP_CLKCTRL, omap4_mcasp_bit_data, CLKF_SW_SUP, "func_mcasp_abe_gfclk" },
193 { OMAP4_MCBSP1_CLKCTRL, omap4_mcbsp1_bit_data, CLKF_SW_SUP, "func_mcbsp1_gfclk" },
194 { OMAP4_MCBSP2_CLKCTRL, omap4_mcbsp2_bit_data, CLKF_SW_SUP, "func_mcbsp2_gfclk" },
195 { OMAP4_MCBSP3_CLKCTRL, omap4_mcbsp3_bit_data, CLKF_SW_SUP, "func_mcbsp3_gfclk" },
196 { OMAP4_SLIMBUS1_CLKCTRL, omap4_slimbus1_bit_data, CLKF_SW_SUP, "slimbus1_fclk_0" },
197 { OMAP4_TIMER5_CLKCTRL, omap4_timer5_bit_data, CLKF_SW_SUP, "timer5_sync_mux" },
198 { OMAP4_TIMER6_CLKCTRL, omap4_timer6_bit_data, CLKF_SW_SUP, "timer6_sync_mux" },
199 { OMAP4_TIMER7_CLKCTRL, omap4_timer7_bit_data, CLKF_SW_SUP, "timer7_sync_mux" },
200 { OMAP4_TIMER8_CLKCTRL, omap4_timer8_bit_data, CLKF_SW_SUP, "timer8_sync_mux" },
201 { OMAP4_WD_TIMER3_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
202 { 0 },
203};
204
205static const struct omap_clkctrl_reg_data omap4_l4_ao_clkctrl_regs[] __initconst = {
206 { OMAP4_SMARTREFLEX_MPU_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
207 { OMAP4_SMARTREFLEX_IVA_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
208 { OMAP4_SMARTREFLEX_CORE_CLKCTRL, NULL, CLKF_SW_SUP, "l4_wkup_clk_mux_ck" },
209 { 0 },
210};
211
212static const struct omap_clkctrl_reg_data omap4_l3_1_clkctrl_regs[] __initconst = {
213 { OMAP4_L3_MAIN_1_CLKCTRL, NULL, 0, "l3_div_ck" },
214 { 0 },
215};
216
217static const struct omap_clkctrl_reg_data omap4_l3_2_clkctrl_regs[] __initconst = {
218 { OMAP4_L3_MAIN_2_CLKCTRL, NULL, 0, "l3_div_ck" },
219 { OMAP4_GPMC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
220 { OMAP4_OCMC_RAM_CLKCTRL, NULL, 0, "l3_div_ck" },
221 { 0 },
222};
223
224static const struct omap_clkctrl_reg_data omap4_ducati_clkctrl_regs[] __initconst = {
225 { OMAP4_IPU_CLKCTRL, NULL, CLKF_HW_SUP, "ducati_clk_mux_ck" },
226 { 0 },
227};
228
229static const struct omap_clkctrl_reg_data omap4_l3_dma_clkctrl_regs[] __initconst = {
230 { OMAP4_DMA_SYSTEM_CLKCTRL, NULL, 0, "l3_div_ck" },
231 { 0 },
232};
233
234static const struct omap_clkctrl_reg_data omap4_l3_emif_clkctrl_regs[] __initconst = {
235 { OMAP4_DMM_CLKCTRL, NULL, 0, "l3_div_ck" },
236 { OMAP4_EMIF1_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
237 { OMAP4_EMIF2_CLKCTRL, NULL, CLKF_HW_SUP, "ddrphy_ck" },
238 { 0 },
239};
240
241static const struct omap_clkctrl_reg_data omap4_d2d_clkctrl_regs[] __initconst = {
242 { OMAP4_C2C_CLKCTRL, NULL, 0, "div_core_ck" },
243 { 0 },
244};
245
246static const struct omap_clkctrl_reg_data omap4_l4_cfg_clkctrl_regs[] __initconst = {
247 { OMAP4_L4_CFG_CLKCTRL, NULL, 0, "l4_div_ck" },
248 { OMAP4_SPINLOCK_CLKCTRL, NULL, 0, "l4_div_ck" },
249 { OMAP4_MAILBOX_CLKCTRL, NULL, 0, "l4_div_ck" },
250 { 0 },
251};
252
253static const struct omap_clkctrl_reg_data omap4_l3_instr_clkctrl_regs[] __initconst = {
254 { OMAP4_L3_MAIN_3_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
255 { OMAP4_L3_INSTR_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
256 { OMAP4_OCP_WP_NOC_CLKCTRL, NULL, CLKF_HW_SUP, "l3_div_ck" },
257 { 0 },
258};
259
260static const struct omap_clkctrl_reg_data omap4_ivahd_clkctrl_regs[] __initconst = {
261 { OMAP4_IVA_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
262 { OMAP4_SL2IF_CLKCTRL, NULL, CLKF_HW_SUP, "dpll_iva_m5x2_ck" },
263 { 0 },
264};
265
266static const char * const omap4_iss_ctrlclk_parents[] __initconst = {
267 "func_96m_fclk",
268 NULL,
269};
270
271static const struct omap_clkctrl_bit_data omap4_iss_bit_data[] __initconst = {
272 { 8, TI_CLK_GATE, omap4_iss_ctrlclk_parents, NULL },
273 { 0 },
274};
275
276static const char * const omap4_fdif_fck_parents[] __initconst = {
277 "dpll_per_m4x2_ck",
278 NULL,
279};
280
281static const struct omap_clkctrl_div_data omap4_fdif_fck_data __initconst = {
282 .max_div = 4,
283};
284
285static const struct omap_clkctrl_bit_data omap4_fdif_bit_data[] __initconst = {
286 { 24, TI_CLK_DIVIDER, omap4_fdif_fck_parents, &omap4_fdif_fck_data },
287 { 0 },
288};
289
290static const struct omap_clkctrl_reg_data omap4_iss_clkctrl_regs[] __initconst = {
291 { OMAP4_ISS_CLKCTRL, omap4_iss_bit_data, CLKF_SW_SUP, "ducati_clk_mux_ck" },
292 { OMAP4_FDIF_CLKCTRL, omap4_fdif_bit_data, CLKF_SW_SUP, "fdif_fck" },
293 { 0 },
294};
295
296static const char * const omap4_dss_dss_clk_parents[] __initconst = {
297 "dpll_per_m5x2_ck",
298 NULL,
299};
300
301static const char * const omap4_dss_48mhz_clk_parents[] __initconst = {
302 "func_48mc_fclk",
303 NULL,
304};
305
306static const char * const omap4_dss_sys_clk_parents[] __initconst = {
307 "syc_clk_div_ck",
308 NULL,
309};
310
311static const char * const omap4_dss_tv_clk_parents[] __initconst = {
312 "extalt_clkin_ck",
313 NULL,
314};
315
316static const struct omap_clkctrl_bit_data omap4_dss_core_bit_data[] __initconst = {
317 { 8, TI_CLK_GATE, omap4_dss_dss_clk_parents, NULL },
318 { 9, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
319 { 10, TI_CLK_GATE, omap4_dss_sys_clk_parents, NULL },
320 { 11, TI_CLK_GATE, omap4_dss_tv_clk_parents, NULL },
321 { 0 },
322};
323
324static const struct omap_clkctrl_reg_data omap4_l3_dss_clkctrl_regs[] __initconst = {
325 { OMAP4_DSS_CORE_CLKCTRL, omap4_dss_core_bit_data, CLKF_SW_SUP, "dss_dss_clk" },
326 { 0 },
327};
328
329static const char * const omap4_sgx_clk_mux_parents[] __initconst = {
330 "dpll_core_m7x2_ck",
331 "dpll_per_m7x2_ck",
332 NULL,
333};
334
335static const struct omap_clkctrl_bit_data omap4_gpu_bit_data[] __initconst = {
336 { 24, TI_CLK_MUX, omap4_sgx_clk_mux_parents, NULL },
337 { 0 },
338};
339
340static const struct omap_clkctrl_reg_data omap4_l3_gfx_clkctrl_regs[] __initconst = {
341 { OMAP4_GPU_CLKCTRL, omap4_gpu_bit_data, CLKF_SW_SUP, "sgx_clk_mux" },
342 { 0 },
343};
344
345static const char * const omap4_hsmmc1_fclk_parents[] __initconst = {
346 "func_64m_fclk",
347 "func_96m_fclk",
348 NULL,
349};
350
351static const struct omap_clkctrl_bit_data omap4_mmc1_bit_data[] __initconst = {
352 { 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
353 { 0 },
354};
355
356static const struct omap_clkctrl_bit_data omap4_mmc2_bit_data[] __initconst = {
357 { 24, TI_CLK_MUX, omap4_hsmmc1_fclk_parents, NULL },
358 { 0 },
359};
360
361static const char * const omap4_hsi_fck_parents[] __initconst = {
362 "dpll_per_m2x2_ck",
363 NULL,
364};
365
366static const struct omap_clkctrl_div_data omap4_hsi_fck_data __initconst = {
367 .max_div = 4,
368};
369
370static const struct omap_clkctrl_bit_data omap4_hsi_bit_data[] __initconst = {
371 { 24, TI_CLK_DIVIDER, omap4_hsi_fck_parents, &omap4_hsi_fck_data },
372 { 0 },
373};
374
375static const char * const omap4_usb_host_hs_utmi_p1_clk_parents[] __initconst = {
376 "utmi_p1_gfclk",
377 NULL,
378};
379
380static const char * const omap4_usb_host_hs_utmi_p2_clk_parents[] __initconst = {
381 "utmi_p2_gfclk",
382 NULL,
383};
384
385static const char * const omap4_usb_host_hs_utmi_p3_clk_parents[] __initconst = {
386 "init_60m_fclk",
387 NULL,
388};
389
390static const char * const omap4_usb_host_hs_hsic480m_p1_clk_parents[] __initconst = {
391 "dpll_usb_m2_ck",
392 NULL,
393};
394
395static const char * const omap4_utmi_p1_gfclk_parents[] __initconst = {
396 "init_60m_fclk",
397 "xclk60mhsp1_ck",
398 NULL,
399};
400
401static const char * const omap4_utmi_p2_gfclk_parents[] __initconst = {
402 "init_60m_fclk",
403 "xclk60mhsp2_ck",
404 NULL,
405};
406
407static const struct omap_clkctrl_bit_data omap4_usb_host_hs_bit_data[] __initconst = {
408 { 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p1_clk_parents, NULL },
409 { 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p2_clk_parents, NULL },
410 { 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
411 { 11, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
412 { 12, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
413 { 13, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
414 { 14, TI_CLK_GATE, omap4_usb_host_hs_hsic480m_p1_clk_parents, NULL },
415 { 15, TI_CLK_GATE, omap4_dss_48mhz_clk_parents, NULL },
416 { 24, TI_CLK_MUX, omap4_utmi_p1_gfclk_parents, NULL },
417 { 25, TI_CLK_MUX, omap4_utmi_p2_gfclk_parents, NULL },
418 { 0 },
419};
420
421static const char * const omap4_usb_otg_hs_xclk_parents[] __initconst = {
422 "otg_60m_gfclk",
423 NULL,
424};
425
426static const char * const omap4_otg_60m_gfclk_parents[] __initconst = {
427 "utmi_phy_clkout_ck",
428 "xclk60motg_ck",
429 NULL,
430};
431
432static const struct omap_clkctrl_bit_data omap4_usb_otg_hs_bit_data[] __initconst = {
433 { 8, TI_CLK_GATE, omap4_usb_otg_hs_xclk_parents, NULL },
434 { 24, TI_CLK_MUX, omap4_otg_60m_gfclk_parents, NULL },
435 { 0 },
436};
437
438static const struct omap_clkctrl_bit_data omap4_usb_tll_hs_bit_data[] __initconst = {
439 { 8, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
440 { 9, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
441 { 10, TI_CLK_GATE, omap4_usb_host_hs_utmi_p3_clk_parents, NULL },
442 { 0 },
443};
444
445static const char * const omap4_ocp2scp_usb_phy_phy_48m_parents[] __initconst = {
446 "func_48m_fclk",
447 NULL,
448};
449
450static const struct omap_clkctrl_bit_data omap4_ocp2scp_usb_phy_bit_data[] __initconst = {
451 { 8, TI_CLK_GATE, omap4_ocp2scp_usb_phy_phy_48m_parents, NULL },
452 { 0 },
453};
454
455static const struct omap_clkctrl_reg_data omap4_l3_init_clkctrl_regs[] __initconst = {
456 { OMAP4_MMC1_CLKCTRL, omap4_mmc1_bit_data, CLKF_SW_SUP, "hsmmc1_fclk" },
457 { OMAP4_MMC2_CLKCTRL, omap4_mmc2_bit_data, CLKF_SW_SUP, "hsmmc2_fclk" },
458 { OMAP4_HSI_CLKCTRL, omap4_hsi_bit_data, CLKF_HW_SUP, "hsi_fck" },
459 { OMAP4_USB_HOST_HS_CLKCTRL, omap4_usb_host_hs_bit_data, CLKF_SW_SUP, "init_60m_fclk" },
460 { OMAP4_USB_OTG_HS_CLKCTRL, omap4_usb_otg_hs_bit_data, CLKF_HW_SUP, "l3_div_ck" },
461 { OMAP4_USB_TLL_HS_CLKCTRL, omap4_usb_tll_hs_bit_data, CLKF_HW_SUP, "l4_div_ck" },
462 { OMAP4_USB_HOST_FS_CLKCTRL, NULL, CLKF_SW_SUP, "func_48mc_fclk" },
463 { OMAP4_OCP2SCP_USB_PHY_CLKCTRL, omap4_ocp2scp_usb_phy_bit_data, CLKF_HW_SUP, "ocp2scp_usb_phy_phy_48m" },
464 { 0 },
465};
466
467static const char * const omap4_cm2_dm10_mux_parents[] __initconst = {
468 "sys_clkin_ck",
469 "sys_32k_ck",
470 NULL,
471};
472
473static const struct omap_clkctrl_bit_data omap4_timer10_bit_data[] __initconst = {
474 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
475 { 0 },
476};
477
478static const struct omap_clkctrl_bit_data omap4_timer11_bit_data[] __initconst = {
479 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
480 { 0 },
481};
482
483static const struct omap_clkctrl_bit_data omap4_timer2_bit_data[] __initconst = {
484 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
485 { 0 },
486};
487
488static const struct omap_clkctrl_bit_data omap4_timer3_bit_data[] __initconst = {
489 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
490 { 0 },
491};
492
493static const struct omap_clkctrl_bit_data omap4_timer4_bit_data[] __initconst = {
494 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
495 { 0 },
496};
497
498static const struct omap_clkctrl_bit_data omap4_timer9_bit_data[] __initconst = {
499 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
500 { 0 },
501};
502
503static const char * const omap4_gpio2_dbclk_parents[] __initconst = {
504 "sys_32k_ck",
505 NULL,
506};
507
508static const struct omap_clkctrl_bit_data omap4_gpio2_bit_data[] __initconst = {
509 { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
510 { 0 },
511};
512
513static const struct omap_clkctrl_bit_data omap4_gpio3_bit_data[] __initconst = {
514 { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
515 { 0 },
516};
517
518static const struct omap_clkctrl_bit_data omap4_gpio4_bit_data[] __initconst = {
519 { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
520 { 0 },
521};
522
523static const struct omap_clkctrl_bit_data omap4_gpio5_bit_data[] __initconst = {
524 { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
525 { 0 },
526};
527
528static const struct omap_clkctrl_bit_data omap4_gpio6_bit_data[] __initconst = {
529 { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
530 { 0 },
531};
532
533static const char * const omap4_per_mcbsp4_gfclk_parents[] __initconst = {
534 "mcbsp4_sync_mux_ck",
535 "pad_clks_ck",
536 NULL,
537};
538
539static const char * const omap4_mcbsp4_sync_mux_ck_parents[] __initconst = {
540 "func_96m_fclk",
541 "per_abe_nc_fclk",
542 NULL,
543};
544
545static const struct omap_clkctrl_bit_data omap4_mcbsp4_bit_data[] __initconst = {
546 { 24, TI_CLK_MUX, omap4_per_mcbsp4_gfclk_parents, NULL },
547 { 25, TI_CLK_MUX, omap4_mcbsp4_sync_mux_ck_parents, NULL },
548 { 0 },
549};
550
551static const char * const omap4_slimbus2_fclk_0_parents[] __initconst = {
552 "func_24mc_fclk",
553 NULL,
554};
555
556static const char * const omap4_slimbus2_fclk_1_parents[] __initconst = {
557 "per_abe_24m_fclk",
558 NULL,
559};
560
561static const char * const omap4_slimbus2_slimbus_clk_parents[] __initconst = {
562 "pad_slimbus_core_clks_ck",
563 NULL,
564};
565
566static const struct omap_clkctrl_bit_data omap4_slimbus2_bit_data[] __initconst = {
567 { 8, TI_CLK_GATE, omap4_slimbus2_fclk_0_parents, NULL },
568 { 9, TI_CLK_GATE, omap4_slimbus2_fclk_1_parents, NULL },
569 { 10, TI_CLK_GATE, omap4_slimbus2_slimbus_clk_parents, NULL },
570 { 0 },
571};
572
573static const struct omap_clkctrl_reg_data omap4_l4_per_clkctrl_regs[] __initconst = {
574 { OMAP4_TIMER10_CLKCTRL, omap4_timer10_bit_data, CLKF_SW_SUP, "cm2_dm10_mux" },
575 { OMAP4_TIMER11_CLKCTRL, omap4_timer11_bit_data, CLKF_SW_SUP, "cm2_dm11_mux" },
576 { OMAP4_TIMER2_CLKCTRL, omap4_timer2_bit_data, CLKF_SW_SUP, "cm2_dm2_mux" },
577 { OMAP4_TIMER3_CLKCTRL, omap4_timer3_bit_data, CLKF_SW_SUP, "cm2_dm3_mux" },
578 { OMAP4_TIMER4_CLKCTRL, omap4_timer4_bit_data, CLKF_SW_SUP, "cm2_dm4_mux" },
579 { OMAP4_TIMER9_CLKCTRL, omap4_timer9_bit_data, CLKF_SW_SUP, "cm2_dm9_mux" },
580 { OMAP4_ELM_CLKCTRL, NULL, 0, "l4_div_ck" },
581 { OMAP4_GPIO2_CLKCTRL, omap4_gpio2_bit_data, CLKF_HW_SUP, "l4_div_ck" },
582 { OMAP4_GPIO3_CLKCTRL, omap4_gpio3_bit_data, CLKF_HW_SUP, "l4_div_ck" },
583 { OMAP4_GPIO4_CLKCTRL, omap4_gpio4_bit_data, CLKF_HW_SUP, "l4_div_ck" },
584 { OMAP4_GPIO5_CLKCTRL, omap4_gpio5_bit_data, CLKF_HW_SUP, "l4_div_ck" },
585 { OMAP4_GPIO6_CLKCTRL, omap4_gpio6_bit_data, CLKF_HW_SUP, "l4_div_ck" },
586 { OMAP4_HDQ1W_CLKCTRL, NULL, CLKF_SW_SUP, "func_12m_fclk" },
587 { OMAP4_I2C1_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
588 { OMAP4_I2C2_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
589 { OMAP4_I2C3_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
590 { OMAP4_I2C4_CLKCTRL, NULL, CLKF_SW_SUP, "func_96m_fclk" },
591 { OMAP4_L4_PER_CLKCTRL, NULL, 0, "l4_div_ck" },
592 { OMAP4_MCBSP4_CLKCTRL, omap4_mcbsp4_bit_data, CLKF_SW_SUP, "per_mcbsp4_gfclk" },
593 { OMAP4_MCSPI1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
594 { OMAP4_MCSPI2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
595 { OMAP4_MCSPI3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
596 { OMAP4_MCSPI4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
597 { OMAP4_MMC3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
598 { OMAP4_MMC4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
599 { OMAP4_SLIMBUS2_CLKCTRL, omap4_slimbus2_bit_data, CLKF_SW_SUP, "slimbus2_fclk_0" },
600 { OMAP4_UART1_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
601 { OMAP4_UART2_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
602 { OMAP4_UART3_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
603 { OMAP4_UART4_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
604 { OMAP4_MMC5_CLKCTRL, NULL, CLKF_SW_SUP, "func_48m_fclk" },
605 { 0 },
606};
607
608static const struct omap_clkctrl_bit_data omap4_gpio1_bit_data[] __initconst = {
609 { 8, TI_CLK_GATE, omap4_gpio2_dbclk_parents, NULL },
610 { 0 },
611};
612
613static const struct omap_clkctrl_bit_data omap4_timer1_bit_data[] __initconst = {
614 { 24, TI_CLK_MUX, omap4_cm2_dm10_mux_parents, NULL },
615 { 0 },
616};
617
618static const struct omap_clkctrl_reg_data omap4_l4_wkup_clkctrl_regs[] __initconst = {
619 { OMAP4_L4_WKUP_CLKCTRL, NULL, 0, "l4_wkup_clk_mux_ck" },
620 { OMAP4_WD_TIMER2_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
621 { OMAP4_GPIO1_CLKCTRL, omap4_gpio1_bit_data, CLKF_HW_SUP, "l4_wkup_clk_mux_ck" },
622 { OMAP4_TIMER1_CLKCTRL, omap4_timer1_bit_data, CLKF_SW_SUP, "dmt1_clk_mux" },
623 { OMAP4_COUNTER_32K_CLKCTRL, NULL, 0, "sys_32k_ck" },
624 { OMAP4_KBD_CLKCTRL, NULL, CLKF_SW_SUP, "sys_32k_ck" },
625 { 0 },
626};
627
628static const char * const omap4_pmd_stm_clock_mux_ck_parents[] __initconst = {
629 "sys_clkin_ck",
630 "dpll_core_m6x2_ck",
631 "tie_low_clock_ck",
632 NULL,
633};
634
635static const char * const omap4_trace_clk_div_div_ck_parents[] __initconst = {
636 "pmd_trace_clk_mux_ck",
637 NULL,
638};
639
640static const int omap4_trace_clk_div_div_ck_divs[] __initconst = {
641 0,
642 1,
643 2,
644 0,
645 4,
646 -1,
647};
648
649static const struct omap_clkctrl_div_data omap4_trace_clk_div_div_ck_data __initconst = {
650 .dividers = omap4_trace_clk_div_div_ck_divs,
651};
652
653static const char * const omap4_stm_clk_div_ck_parents[] __initconst = {
654 "pmd_stm_clock_mux_ck",
655 NULL,
656};
657
658static const struct omap_clkctrl_div_data omap4_stm_clk_div_ck_data __initconst = {
659 .max_div = 64,
660};
661
662static const struct omap_clkctrl_bit_data omap4_debugss_bit_data[] __initconst = {
663 { 20, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
664 { 22, TI_CLK_MUX, omap4_pmd_stm_clock_mux_ck_parents, NULL },
665 { 24, TI_CLK_DIVIDER, omap4_trace_clk_div_div_ck_parents, &omap4_trace_clk_div_div_ck_data },
666 { 27, TI_CLK_DIVIDER, omap4_stm_clk_div_ck_parents, &omap4_stm_clk_div_ck_data },
667 { 0 },
668};
669
670static const struct omap_clkctrl_reg_data omap4_emu_sys_clkctrl_regs[] __initconst = {
671 { OMAP4_DEBUGSS_CLKCTRL, omap4_debugss_bit_data, 0, "trace_clk_div_ck" },
672 { 0 },
673};
674
675const struct omap_clkctrl_data omap4_clkctrl_data[] __initconst = {
676 { 0x4a004320, omap4_mpuss_clkctrl_regs },
677 { 0x4a004420, omap4_tesla_clkctrl_regs },
678 { 0x4a004520, omap4_abe_clkctrl_regs },
679 { 0x4a008620, omap4_l4_ao_clkctrl_regs },
680 { 0x4a008720, omap4_l3_1_clkctrl_regs },
681 { 0x4a008820, omap4_l3_2_clkctrl_regs },
682 { 0x4a008920, omap4_ducati_clkctrl_regs },
683 { 0x4a008a20, omap4_l3_dma_clkctrl_regs },
684 { 0x4a008b20, omap4_l3_emif_clkctrl_regs },
685 { 0x4a008c20, omap4_d2d_clkctrl_regs },
686 { 0x4a008d20, omap4_l4_cfg_clkctrl_regs },
687 { 0x4a008e20, omap4_l3_instr_clkctrl_regs },
688 { 0x4a008f20, omap4_ivahd_clkctrl_regs },
689 { 0x4a009020, omap4_iss_clkctrl_regs },
690 { 0x4a009120, omap4_l3_dss_clkctrl_regs },
691 { 0x4a009220, omap4_l3_gfx_clkctrl_regs },
692 { 0x4a009320, omap4_l3_init_clkctrl_regs },
693 { 0x4a009420, omap4_l4_per_clkctrl_regs },
694 { 0x4a307820, omap4_l4_wkup_clkctrl_regs },
695 { 0x4a307a20, omap4_emu_sys_clkctrl_regs },
696 { 0 },
697};
698
Tero Kristo21876ea2013-07-18 15:57:51 +0300699static struct ti_dt_clk omap44xx_clks[] = {
Tero Kristo21876ea2013-07-18 15:57:51 +0300700 DT_CLK("smp_twd", NULL, "mpu_periphclk"),
Tero Kristo21876ea2013-07-18 15:57:51 +0300701 DT_CLK("omapdss_dss", "ick", "dss_fck"),
Tero Kristo21876ea2013-07-18 15:57:51 +0300702 DT_CLK("usbhs_omap", "fs_fck", "usb_host_fs_fck"),
Tero Kristo21876ea2013-07-18 15:57:51 +0300703 DT_CLK("usbhs_omap", "hs_fck", "usb_host_hs_fck"),
Tero Kristo21876ea2013-07-18 15:57:51 +0300704 DT_CLK("musb-omap2430", "ick", "usb_otg_hs_ick"),
Tero Kristo21876ea2013-07-18 15:57:51 +0300705 DT_CLK("usbhs_omap", "usbtll_ick", "usb_tll_hs_ick"),
706 DT_CLK("usbhs_tll", "usbtll_ick", "usb_tll_hs_ick"),
Tero Kristo21876ea2013-07-18 15:57:51 +0300707 DT_CLK("omap_i2c.1", "ick", "dummy_ck"),
708 DT_CLK("omap_i2c.2", "ick", "dummy_ck"),
709 DT_CLK("omap_i2c.3", "ick", "dummy_ck"),
710 DT_CLK("omap_i2c.4", "ick", "dummy_ck"),
711 DT_CLK(NULL, "mailboxes_ick", "dummy_ck"),
712 DT_CLK("omap_hsmmc.0", "ick", "dummy_ck"),
713 DT_CLK("omap_hsmmc.1", "ick", "dummy_ck"),
714 DT_CLK("omap_hsmmc.2", "ick", "dummy_ck"),
715 DT_CLK("omap_hsmmc.3", "ick", "dummy_ck"),
716 DT_CLK("omap_hsmmc.4", "ick", "dummy_ck"),
717 DT_CLK("omap-mcbsp.1", "ick", "dummy_ck"),
718 DT_CLK("omap-mcbsp.2", "ick", "dummy_ck"),
719 DT_CLK("omap-mcbsp.3", "ick", "dummy_ck"),
720 DT_CLK("omap-mcbsp.4", "ick", "dummy_ck"),
721 DT_CLK("omap2_mcspi.1", "ick", "dummy_ck"),
722 DT_CLK("omap2_mcspi.2", "ick", "dummy_ck"),
723 DT_CLK("omap2_mcspi.3", "ick", "dummy_ck"),
724 DT_CLK("omap2_mcspi.4", "ick", "dummy_ck"),
725 DT_CLK(NULL, "uart1_ick", "dummy_ck"),
726 DT_CLK(NULL, "uart2_ick", "dummy_ck"),
727 DT_CLK(NULL, "uart3_ick", "dummy_ck"),
728 DT_CLK(NULL, "uart4_ick", "dummy_ck"),
729 DT_CLK("usbhs_omap", "usbhost_ick", "dummy_ck"),
730 DT_CLK("usbhs_omap", "usbtll_fck", "dummy_ck"),
731 DT_CLK("usbhs_tll", "usbtll_fck", "dummy_ck"),
732 DT_CLK("omap_wdt", "ick", "dummy_ck"),
733 DT_CLK(NULL, "timer_32k_ck", "sys_32k_ck"),
Tero Kristo21876ea2013-07-18 15:57:51 +0300734 DT_CLK("4a318000.timer", "timer_sys_ck", "sys_clkin_ck"),
735 DT_CLK("48032000.timer", "timer_sys_ck", "sys_clkin_ck"),
736 DT_CLK("48034000.timer", "timer_sys_ck", "sys_clkin_ck"),
737 DT_CLK("48036000.timer", "timer_sys_ck", "sys_clkin_ck"),
738 DT_CLK("4803e000.timer", "timer_sys_ck", "sys_clkin_ck"),
739 DT_CLK("48086000.timer", "timer_sys_ck", "sys_clkin_ck"),
740 DT_CLK("48088000.timer", "timer_sys_ck", "sys_clkin_ck"),
741 DT_CLK("40138000.timer", "timer_sys_ck", "syc_clk_div_ck"),
742 DT_CLK("4013a000.timer", "timer_sys_ck", "syc_clk_div_ck"),
743 DT_CLK("4013c000.timer", "timer_sys_ck", "syc_clk_div_ck"),
744 DT_CLK("4013e000.timer", "timer_sys_ck", "syc_clk_div_ck"),
745 DT_CLK(NULL, "cpufreq_ck", "dpll_mpu_ck"),
Tero Kristo21876ea2013-07-18 15:57:51 +0300746 { .node_name = NULL },
747};
748
749int __init omap4xxx_dt_clk_init(void)
750{
751 int rc;
752 struct clk *abe_dpll_ref, *abe_dpll, *sys_32k_ck, *usb_dpll;
753
754 ti_dt_clocks_register(omap44xx_clks);
755
756 omap2_clk_disable_autoidle_all();
757
Tero Kristob6312da2016-03-22 16:10:55 +0200758 ti_clk_add_aliases();
759
Tero Kristo21876ea2013-07-18 15:57:51 +0300760 /*
761 * Lock USB DPLL on OMAP4 devices so that the L3INIT power
762 * domain can transition to retention state when not in use.
763 */
764 usb_dpll = clk_get_sys(NULL, "dpll_usb_ck");
765 rc = clk_set_rate(usb_dpll, OMAP4_DPLL_USB_DEFFREQ);
766 if (rc)
767 pr_err("%s: failed to configure USB DPLL!\n", __func__);
768
769 /*
770 * On OMAP4460 the ABE DPLL fails to turn on if in idle low-power
771 * state when turning the ABE clock domain. Workaround this by
772 * locking the ABE DPLL on boot.
773 * Lock the ABE DPLL in any case to avoid issues with audio.
774 */
775 abe_dpll_ref = clk_get_sys(NULL, "abe_dpll_refclk_mux_ck");
776 sys_32k_ck = clk_get_sys(NULL, "sys_32k_ck");
777 rc = clk_set_parent(abe_dpll_ref, sys_32k_ck);
778 abe_dpll = clk_get_sys(NULL, "dpll_abe_ck");
779 if (!rc)
780 rc = clk_set_rate(abe_dpll, OMAP4_DPLL_ABE_DEFFREQ);
781 if (rc)
782 pr_err("%s: failed to configure ABE DPLL!\n", __func__);
783
784 return 0;
785}