| /* |
| * Copyright 2017-2018 NXP |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License |
| * as published by the Free Software Foundation; either version 2 |
| * of the License, or (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| #include "fsl-imx8qxp.dtsi" |
| |
| / { |
| model = "Freescale i.MX8QXP MEK"; |
| compatible = "fsl,imx8qxp-mek", "fsl,imx8qxp"; |
| |
| chosen { |
| bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; |
| stdout-path = &lpuart0; |
| }; |
| |
| brcmfmac: brcmfmac { |
| compatible = "cypress,brcmfmac"; |
| pinctrl-names = "init", "idle", "default"; |
| pinctrl-0 = <&pinctrl_wifi_init>; |
| pinctrl-1 = <&pinctrl_wifi_init>; |
| pinctrl-2 = <&pinctrl_wifi>; |
| }; |
| |
| modem_reset: modem-reset { |
| compatible = "gpio-reset"; |
| reset-gpios = <&pca9557_a 1 GPIO_ACTIVE_LOW>; |
| reset-delay-us = <2000>; |
| reset-post-delay-ms = <40>; |
| #reset-cells = <0>; |
| }; |
| |
| regulators { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| reg_can_en: regulator-can-gen { |
| compatible = "regulator-fixed"; |
| regulator-name = "can-en"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_can_stby: regulator-can-stby { |
| compatible = "regulator-fixed"; |
| regulator-name = "can-stby"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| vin-supply = <®_can_en>; |
| }; |
| |
| reg_fec2_supply: fec2_nvcc { |
| compatible = "regulator-fixed"; |
| regulator-name = "fec2_nvcc"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| gpio = <&max7322 0 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_usdhc2_vmmc: usdhc2_vmmc { |
| compatible = "regulator-fixed"; |
| regulator-name = "SD1_SPWR"; |
| regulator-min-microvolt = <3000000>; |
| regulator-max-microvolt = <3000000>; |
| gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; |
| off-on-delay = <3480>; |
| enable-active-high; |
| }; |
| |
| epdev_on: fixedregulator@100 { |
| compatible = "regulator-fixed"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-name = "epdev_on"; |
| gpio = <&pca9557_a 0 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_usb_otg1_vbus: regulator@0 { |
| compatible = "regulator-fixed"; |
| reg = <0>; |
| regulator-name = "usb_otg1_vbus"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| gpio = <&pca9557_b 2 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| }; |
| |
| reg_audio: fixedregulator@2 { |
| compatible = "regulator-fixed"; |
| reg = <2>; |
| regulator-name = "cs42888_supply"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| }; |
| |
| sound: sound { |
| compatible = "fsl,imx7d-evk-wm8960", |
| "fsl,imx-audio-wm8960"; |
| model = "wm8960-audio"; |
| cpu-dai = <&sai1>; |
| audio-codec = <&wm8960>; |
| codec-master; |
| /* |
| * hp-det = <hp-det-pin hp-det-polarity>; |
| * hp-det-pin: JD1 JD2 or JD3 |
| * hp-det-polarity = 0: hp detect high for headphone |
| * hp-det-polarity = 1: hp detect high for speaker |
| */ |
| hp-det = <2 0>; |
| hp-det-gpios = <&gpio1 0 0>; |
| mic-det-gpios = <&gpio1 0 0>; |
| audio-routing = |
| "Headphone Jack", "HP_L", |
| "Headphone Jack", "HP_R", |
| "Ext Spk", "SPK_LP", |
| "Ext Spk", "SPK_LN", |
| "Ext Spk", "SPK_RP", |
| "Ext Spk", "SPK_RN", |
| "LINPUT2", "Mic Jack", |
| "LINPUT3", "Mic Jack", |
| "RINPUT1", "Main MIC", |
| "RINPUT2", "Main MIC", |
| "Mic Jack", "MICB", |
| "Main MIC", "MICB", |
| "CPU-Playback", "ASRC-Playback", |
| "Playback", "CPU-Playback", |
| "ASRC-Capture", "CPU-Capture", |
| "CPU-Capture", "Capture"; |
| }; |
| |
| sound-amix-sai { |
| compatible = "fsl,imx-audio-amix"; |
| model = "amix-audio-sai"; |
| dais = <&sai4>, <&sai5>; |
| amix-controller = <&amix>; |
| }; |
| |
| sound-cs42888 { |
| compatible = "fsl,imx8qm-sabreauto-cs42888", |
| "fsl,imx-audio-cs42888"; |
| model = "imx-cs42888"; |
| esai-controller = <&esai0>; |
| audio-codec = <&cs42888>; |
| asrc-controller = <&asrc0>; |
| status = "okay"; |
| }; |
| |
| lvds_backlight0: lvds_backlight@0 { |
| compatible = "pwm-backlight"; |
| pwms = <&pwm_mipi_lvds0 0 100000 0>; |
| |
| brightness-levels = < 0 1 2 3 4 5 6 7 8 9 |
| 10 11 12 13 14 15 16 17 18 19 |
| 20 21 22 23 24 25 26 27 28 29 |
| 30 31 32 33 34 35 36 37 38 39 |
| 40 41 42 43 44 45 46 47 48 49 |
| 50 51 52 53 54 55 56 57 58 59 |
| 60 61 62 63 64 65 66 67 68 69 |
| 70 71 72 73 74 75 76 77 78 79 |
| 80 81 82 83 84 85 86 87 88 89 |
| 90 91 92 93 94 95 96 97 98 99 |
| 100>; |
| default-brightness-level = <80>; |
| }; |
| |
| lvds_backlight1: lvds_backlight@1 { |
| compatible = "pwm-backlight"; |
| pwms = <&pwm_mipi_lvds1 0 100000 0>; |
| |
| brightness-levels = < 0 1 2 3 4 5 6 7 8 9 |
| 10 11 12 13 14 15 16 17 18 19 |
| 20 21 22 23 24 25 26 27 28 29 |
| 30 31 32 33 34 35 36 37 38 39 |
| 40 41 42 43 44 45 46 47 48 49 |
| 50 51 52 53 54 55 56 57 58 59 |
| 60 61 62 63 64 65 66 67 68 69 |
| 70 71 72 73 74 75 76 77 78 79 |
| 80 81 82 83 84 85 86 87 88 89 |
| 90 91 92 93 94 95 96 97 98 99 |
| 100>; |
| default-brightness-level = <80>; |
| }; |
| |
| lcdif_backlight: lcdif_backlight { |
| compatible = "pwm-backlight"; |
| pwms = <&pwm_adma_lcdif 0 100000 0>; |
| |
| brightness-levels = <0 4 8 16 32 64 128 255>; |
| default-brightness-level = <6>; |
| status = "disabled"; |
| }; |
| |
| }; |
| |
| &acm { |
| status = "okay"; |
| }; |
| |
| &amix { |
| status = "okay"; |
| }; |
| |
| &asrc0 { |
| fsl,asrc-rate = <48000>; |
| status = "okay"; |
| }; |
| |
| &esai0 { |
| compatible = "fsl,imx8qm-esai"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_esai0>; |
| assigned-clocks = <&clk IMX8QXP_ACM_ESAI0_MCLK_SEL>, |
| <&clk IMX8QXP_AUD_PLL0_DIV>, |
| <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, |
| <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, |
| <&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>; |
| assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>; |
| assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; |
| fsl,txm-rxs; |
| status = "okay"; |
| }; |
| |
| &sai4 { |
| assigned-clocks = <&clk IMX8QXP_ACM_SAI4_MCLK_SEL>, |
| <&clk IMX8QXP_AUD_PLL1_DIV>, |
| <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV>, |
| <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV>, |
| <&clk IMX8QXP_AUD_SAI_4_MCLK>; |
| assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>; |
| assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; |
| fsl,sai-asynchronous; |
| fsl,txm-rxs; |
| status = "okay"; |
| }; |
| |
| &sai5 { |
| assigned-clocks = <&clk IMX8QXP_ACM_SAI5_MCLK_SEL>, |
| <&clk IMX8QXP_AUD_PLL1_DIV>, |
| <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_DIV>, |
| <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK1_DIV>, |
| <&clk IMX8QXP_AUD_SAI_5_MCLK>; |
| assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>; |
| assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>; |
| fsl,sai-asynchronous; |
| fsl,txm-rxs; |
| status = "okay"; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog>; |
| |
| imx8qxp-mek { |
| pinctrl_hog: hoggrp { |
| fsl,pins = < |
| SC_P_MCLK_OUT0_ADMA_ACM_MCLK_OUT0 0x0600004c |
| SC_P_COMP_CTL_GPIO_1V8_3V3_GPIORHB_PAD 0x000514a0 |
| >; |
| }; |
| |
| pinctrl_csi0_lpi2c0: csi0lpi2c0grp { |
| fsl,pins = < |
| SC_P_MIPI_CSI0_I2C0_SCL_MIPI_CSI0_I2C0_SCL 0xc2000020 |
| SC_P_MIPI_CSI0_I2C0_SDA_MIPI_CSI0_I2C0_SDA 0xc2000020 |
| >; |
| }; |
| |
| pinctrl_esai0: esai0grp { |
| fsl,pins = < |
| SC_P_ESAI0_FSR_ADMA_ESAI0_FSR 0xc6000040 |
| SC_P_ESAI0_FST_ADMA_ESAI0_FST 0xc6000040 |
| SC_P_ESAI0_SCKR_ADMA_ESAI0_SCKR 0xc6000040 |
| SC_P_ESAI0_SCKT_ADMA_ESAI0_SCKT 0xc6000040 |
| SC_P_ESAI0_TX0_ADMA_ESAI0_TX0 0xc6000040 |
| SC_P_ESAI0_TX1_ADMA_ESAI0_TX1 0xc6000040 |
| SC_P_ESAI0_TX2_RX3_ADMA_ESAI0_TX2_RX3 0xc6000040 |
| SC_P_ESAI0_TX3_RX2_ADMA_ESAI0_TX3_RX2 0xc6000040 |
| SC_P_ESAI0_TX4_RX1_ADMA_ESAI0_TX4_RX1 0xc6000040 |
| SC_P_ESAI0_TX5_RX0_ADMA_ESAI0_TX5_RX0 0xc6000040 |
| >; |
| }; |
| |
| pinctrl_lpuart0: lpuart0grp { |
| fsl,pins = < |
| SC_P_UART0_RX_ADMA_UART0_RX 0x06000020 |
| SC_P_UART0_TX_ADMA_UART0_TX 0x06000020 |
| >; |
| }; |
| |
| pinctrl_lpuart1: lpuart1grp { |
| fsl,pins = < |
| SC_P_UART1_TX_ADMA_UART1_TX 0x06000020 |
| SC_P_UART1_RX_ADMA_UART1_RX 0x06000020 |
| SC_P_UART1_RTS_B_ADMA_UART1_RTS_B 0x06000020 |
| SC_P_UART1_CTS_B_ADMA_UART1_CTS_B 0x06000020 |
| >; |
| }; |
| |
| pinctrl_lpuart2: lpuart2grp { |
| fsl,pins = < |
| SC_P_UART2_TX_ADMA_UART2_TX 0x06000020 |
| SC_P_UART2_RX_ADMA_UART2_RX 0x06000020 |
| >; |
| }; |
| |
| pinctrl_lpuart3: lpuart3grp { |
| fsl,pins = < |
| SC_P_FLEXCAN2_TX_ADMA_UART3_TX 0x06000020 |
| SC_P_FLEXCAN2_RX_ADMA_UART3_RX 0x06000020 |
| >; |
| }; |
| |
| pinctrl_fec1: fec1grp { |
| fsl,pins = < |
| SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB0_PAD 0x000014a0 |
| SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB1_PAD 0x000014a0 |
| SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020 |
| SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020 |
| SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000061 |
| SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000061 |
| SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000061 |
| SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000061 |
| SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000061 |
| SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000061 |
| SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000061 |
| SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000061 |
| SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000061 |
| SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000061 |
| SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000061 |
| SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000061 |
| >; |
| }; |
| |
| pinctrl_fec2: fec2grp { |
| fsl,pins = < |
| SC_P_ESAI0_SCKR_CONN_ENET1_RGMII_TX_CTL 0x00000060 |
| SC_P_ESAI0_FSR_CONN_ENET1_RGMII_TXC 0x00000060 |
| SC_P_ESAI0_TX4_RX1_CONN_ENET1_RGMII_TXD0 0x00000060 |
| SC_P_ESAI0_TX5_RX0_CONN_ENET1_RGMII_TXD1 0x00000060 |
| SC_P_ESAI0_FST_CONN_ENET1_RGMII_TXD2 0x00000060 |
| SC_P_ESAI0_SCKT_CONN_ENET1_RGMII_TXD3 0x00000060 |
| SC_P_ESAI0_TX0_CONN_ENET1_RGMII_RXC 0x00000060 |
| SC_P_SPDIF0_TX_CONN_ENET1_RGMII_RX_CTL 0x00000060 |
| SC_P_SPDIF0_RX_CONN_ENET1_RGMII_RXD0 0x00000060 |
| SC_P_ESAI0_TX3_RX2_CONN_ENET1_RGMII_RXD1 0x00000060 |
| SC_P_ESAI0_TX2_RX3_CONN_ENET1_RGMII_RXD2 0x00000060 |
| SC_P_ESAI0_TX1_CONN_ENET1_RGMII_RXD3 0x00000060 |
| >; |
| }; |
| |
| pinctrl_flexcan1: flexcan0grp { |
| fsl,pins = < |
| SC_P_FLEXCAN0_TX_ADMA_FLEXCAN0_TX 0x21 |
| SC_P_FLEXCAN0_RX_ADMA_FLEXCAN0_RX 0x21 |
| >; |
| }; |
| |
| pinctrl_flexcan2: flexcan1grp { |
| fsl,pins = < |
| SC_P_FLEXCAN1_TX_ADMA_FLEXCAN1_TX 0x21 |
| SC_P_FLEXCAN1_RX_ADMA_FLEXCAN1_RX 0x21 |
| >; |
| }; |
| |
| pinctrl_lcdif: lcdif_grp { |
| fsl,pins = < |
| SC_P_ESAI0_FSR_ADMA_LCDIF_D00 0x00000060 |
| SC_P_ESAI0_FST_ADMA_LCDIF_D01 0x00000060 |
| SC_P_ESAI0_SCKR_ADMA_LCDIF_D02 0x00000060 |
| SC_P_ESAI0_SCKT_ADMA_LCDIF_D03 0x00000060 |
| SC_P_ESAI0_TX0_ADMA_LCDIF_D04 0x00000060 |
| SC_P_ESAI0_TX1_ADMA_LCDIF_D05 0x00000060 |
| SC_P_ESAI0_TX2_RX3_ADMA_LCDIF_D06 0x00000060 |
| SC_P_ESAI0_TX3_RX2_ADMA_LCDIF_D07 0x00000060 |
| SC_P_ESAI0_TX4_RX1_ADMA_LCDIF_D08 0x00000060 |
| SC_P_ESAI0_TX5_RX0_ADMA_LCDIF_D09 0x00000060 |
| SC_P_SPDIF0_RX_ADMA_LCDIF_D10 0x00000060 |
| SC_P_SPDIF0_TX_ADMA_LCDIF_D11 0x00000060 |
| SC_P_SPDIF0_EXT_CLK_ADMA_LCDIF_D12 0x00000060 |
| SC_P_SPI3_SCK_ADMA_LCDIF_D13 0x00000060 |
| SC_P_SPI3_SDO_ADMA_LCDIF_D14 0x00000060 |
| SC_P_SPI3_SDI_ADMA_LCDIF_D15 0x00000060 |
| SC_P_UART1_RTS_B_ADMA_LCDIF_D16 0x00000060 |
| SC_P_UART1_CTS_B_ADMA_LCDIF_D17 0x00000060 |
| SC_P_SAI0_TXD_ADMA_LCDIF_D18 0x00000060 |
| SC_P_SAI0_TXC_ADMA_LCDIF_D19 0x00000060 |
| SC_P_SAI0_RXD_ADMA_LCDIF_D20 0x00000060 |
| SC_P_SAI1_RXD_ADMA_LCDIF_D21 0x00000060 |
| SC_P_SAI1_RXC_ADMA_LCDIF_D22 0x00000060 |
| SC_P_SAI1_RXFS_ADMA_LCDIF_D23 0x00000060 |
| SC_P_SPI3_CS0_ADMA_LCDIF_HSYNC 0x00000060 |
| SC_P_SPI3_CS1_ADMA_LCDIF_RESET 0x00000060 |
| SC_P_MCLK_IN1_ADMA_LCDIF_EN 0x00000060 |
| SC_P_MCLK_IN0_ADMA_LCDIF_VSYNC 0x00000060 |
| SC_P_MCLK_OUT0_ADMA_LCDIF_CLK 0x00000060 |
| >; |
| }; |
| |
| pinctrl_lcdif_pwm: lcdif_pwm_grp { |
| fsl,pins = < |
| SC_P_SPI0_CS1_ADMA_LCD_PWM0_OUT 0x00000060 |
| >; |
| }; |
| |
| pinctrl_flexspi0: flexspi0grp { |
| fsl,pins = < |
| SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x06000021 |
| SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x06000021 |
| SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x06000021 |
| SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x06000021 |
| SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x06000021 |
| SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x06000021 |
| SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x06000021 |
| SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x06000021 |
| SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x06000021 |
| SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x06000021 |
| SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x06000021 |
| SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x06000021 |
| SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x06000021 |
| SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x06000021 |
| SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x06000021 |
| SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x06000021 |
| >; |
| }; |
| |
| pinctrl_cm40_i2c: cm40i2cgrp { |
| fsl,pins = < |
| SC_P_ADC_IN1_M40_I2C0_SDA 0x0600004c |
| SC_P_ADC_IN0_M40_I2C0_SCL 0x0600004c |
| >; |
| }; |
| |
| pinctrl_ioexp_rst: ioexp_rst_grp { |
| fsl,pins = < |
| SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0x06000021 |
| >; |
| }; |
| |
| pinctrl_ioexp_rst_sleep: ioexp_rst_sleep_grp { |
| fsl,pins = < |
| SC_P_SPI2_SDO_LSIO_GPIO1_IO01 0x07800021 |
| >; |
| }; |
| |
| pinctrl_pwm_mipi_lvds0: mipi_lvds0_pwm_grp { |
| fsl,pins = < |
| SC_P_MIPI_DSI0_GPIO0_00_MIPI_DSI0_PWM0_OUT 0x00000020 |
| >; |
| }; |
| |
| pinctrl_i2c0_mipi_lvds0: mipi_lvds0_i2c0_grp { |
| fsl,pins = < |
| SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc6000020 |
| SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc6000020 |
| SC_P_MIPI_DSI0_GPIO0_01_LSIO_GPIO1_IO28 0x00000020 |
| >; |
| }; |
| |
| pinctrl_pwm_mipi_lvds1: mipi_lvds1_pwm_grp { |
| fsl,pins = < |
| SC_P_MIPI_DSI1_GPIO0_00_MIPI_DSI1_PWM0_OUT 0x00000020 |
| >; |
| }; |
| |
| pinctrl_i2c0_mipi_lvds1: mipi_lvds1_i2c0_grp { |
| fsl,pins = < |
| SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc6000020 |
| SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc6000020 |
| SC_P_MIPI_DSI1_GPIO0_01_LSIO_GPIO2_IO00 0x00000020 |
| >; |
| }; |
| |
| pinctrl_isl29023: isl29023grp { |
| fsl,pins = < |
| SC_P_SPI2_SDI_LSIO_GPIO1_IO02 0x00000021 |
| >; |
| }; |
| |
| pinctrl_lpi2c1: lpi1cgrp { |
| fsl,pins = < |
| SC_P_USB_SS3_TC1_ADMA_I2C1_SCL 0x06000021 |
| SC_P_USB_SS3_TC3_ADMA_I2C1_SDA 0x06000021 |
| >; |
| }; |
| |
| pinctrl_sai1: sai1grp { |
| fsl,pins = < |
| SC_P_SAI1_RXD_ADMA_SAI1_RXD 0x06000040 |
| SC_P_SAI1_RXC_ADMA_SAI1_TXC 0x06000040 |
| SC_P_SAI1_RXFS_ADMA_SAI1_TXFS 0x06000040 |
| SC_P_SPI0_CS1_ADMA_SAI1_TXD 0x06000060 |
| SC_P_SPI2_CS0_LSIO_GPIO1_IO00 0x06000040 |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 |
| SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 |
| SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 |
| SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 |
| SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 |
| SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 |
| SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 |
| SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 |
| SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 |
| SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 |
| SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 |
| >; |
| }; |
| |
| pinctrl_typec: typecgrp { |
| fsl,pins = < |
| SC_P_ENET0_REFCLK_125M_25M_LSIO_GPIO5_IO09 0x60 |
| SC_P_SPI2_SCK_LSIO_GPIO1_IO03 0x06000021 |
| >; |
| }; |
| |
| pinctrl_usdhc1_100mhz: usdhc1grp100mhz { |
| fsl,pins = < |
| SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 |
| SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 |
| SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 |
| SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 |
| SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 |
| SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 |
| SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 |
| SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 |
| SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 |
| SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 |
| SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 |
| >; |
| }; |
| |
| pinctrl_usdhc1_200mhz: usdhc1grp200mhz { |
| fsl,pins = < |
| SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 |
| SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 |
| SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 |
| SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 |
| SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 |
| SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 |
| SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 |
| SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 |
| SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 |
| SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 |
| SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041 |
| >; |
| }; |
| |
| pinctrl_usdhc2_gpio: usdhc2gpiogrp { |
| fsl,pins = < |
| SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO19 0x00000021 |
| SC_P_USDHC1_WP_LSIO_GPIO4_IO21 0x00000021 |
| SC_P_USDHC1_CD_B_LSIO_GPIO4_IO22 0x00000021 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 |
| SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 |
| SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 |
| SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 |
| SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 |
| SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 |
| SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2grp100mhz { |
| fsl,pins = < |
| SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 |
| SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 |
| SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 |
| SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 |
| SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 |
| SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 |
| SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2grp200mhz { |
| fsl,pins = < |
| SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 |
| SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 |
| SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 |
| SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 |
| SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 |
| SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 |
| SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 |
| >; |
| }; |
| |
| pinctrl_pcieb: pcieagrp{ |
| fsl,pins = < |
| SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO00 0x06000021 |
| SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO01 0x06000021 |
| SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO02 0x04000021 |
| >; |
| }; |
| |
| pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{ |
| fsl,pins = < |
| SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021 |
| SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021 |
| >; |
| }; |
| |
| pinctrl_gpio3: gpio3grp{ |
| fsl,pins = < |
| SC_P_MIPI_CSI0_GPIO0_01_LSIO_GPIO3_IO07 0xC0000041 |
| SC_P_MIPI_CSI0_GPIO0_00_LSIO_GPIO3_IO08 0xC0000041 |
| >; |
| }; |
| |
| pinctrl_wifi: wifigrp{ |
| fsl,pins = < |
| SC_P_SCU_BOOT_MODE3_SCU_DSC_RTC_CLOCK_OUTPUT_32K 0x20 |
| >; |
| }; |
| |
| pinctrl_wifi_init: wifi_initgrp{ |
| fsl,pins = < |
| SC_P_SCU_BOOT_MODE3_SCU_DSC_BOOT_MODE3 0x20 |
| >; |
| }; |
| |
| pinctrl_parallel_csi: parallelcsigrp { |
| fsl,pins = < |
| SC_P_CSI_D00_CI_PI_D02 0xC0000041 |
| SC_P_CSI_D01_CI_PI_D03 0xC0000041 |
| SC_P_CSI_D02_CI_PI_D04 0xC0000041 |
| SC_P_CSI_D03_CI_PI_D05 0xC0000041 |
| SC_P_CSI_D04_CI_PI_D06 0xC0000041 |
| SC_P_CSI_D05_CI_PI_D07 0xC0000041 |
| SC_P_CSI_D06_CI_PI_D08 0xC0000041 |
| SC_P_CSI_D07_CI_PI_D09 0xC0000041 |
| |
| SC_P_CSI_MCLK_CI_PI_MCLK 0xC0000041 |
| SC_P_CSI_PCLK_CI_PI_PCLK 0xC0000041 |
| SC_P_CSI_HSYNC_CI_PI_HSYNC 0xC0000041 |
| SC_P_CSI_VSYNC_CI_PI_VSYNC 0xC0000041 |
| SC_P_CSI_EN_LSIO_GPIO3_IO02 0xC0000041 |
| SC_P_CSI_RESET_LSIO_GPIO3_IO03 0xC0000041 |
| >; |
| }; |
| }; |
| }; |
| |
| &pd_dma_lpuart0 { |
| debug_console; |
| }; |
| |
| &lpuart0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lpuart0>; |
| status = "okay"; |
| }; |
| |
| &lpuart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lpuart1>; |
| resets = <&modem_reset>; |
| status = "okay"; |
| }; |
| |
| &lpuart2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lpuart2>; |
| status = "okay"; |
| }; |
| |
| &lpuart3 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lpuart3>; |
| status = "okay"; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec1>; |
| phy-mode = "rgmii-txid"; |
| phy-handle = <ðphy0>; |
| fsl,magic-packet; |
| fsl,rgmii_rxc_dly; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <0>; |
| at803x,eee-disabled; |
| at803x,vddio-1p8v; |
| }; |
| |
| ethphy1: ethernet-phy@1 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <1>; |
| at803x,eee-disabled; |
| at803x,vddio-1p8v; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| &fec2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec2>; |
| phy-mode = "rgmii-txid"; |
| phy-handle = <ðphy1>; |
| phy-supply = <®_fec2_supply>; |
| fsl,magic-packet; |
| fsl,rgmii_rxc_dly; |
| status = "disabled"; |
| }; |
| |
| &flexcan1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan1>; |
| xceiver-supply = <®_can_stby>; |
| status = "okay"; |
| }; |
| |
| &flexcan2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan2>; |
| xceiver-supply = <®_can_stby>; |
| status = "okay"; |
| }; |
| |
| &flexspi0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexspi0>; |
| status = "okay"; |
| |
| flash0: mt35xu512aba@0 { |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "micron,mt35xu512aba"; |
| spi-max-frequency = <133000000>; |
| spi-nor,ddr-quad-read-dummy = <8>; |
| }; |
| }; |
| |
| &pd_cm40_intmux { |
| early_power_on; |
| }; |
| |
| &intmux_cm40 { |
| status = "okay"; |
| }; |
| |
| &i2c0_cm40 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_cm40_i2c>; |
| status = "okay"; |
| |
| wm8960: wm8960@1a { |
| compatible = "wlf,wm8960"; |
| reg = <0x1a>; |
| clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; |
| clock-names = "mclk"; |
| wlf,shared-lrclk; |
| power-domains = <&pd_mclk_out0>; |
| assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, |
| <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, |
| <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, |
| <&clk IMX8QXP_AUD_MCLKOUT0>; |
| assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; |
| }; |
| |
| pca6416: gpio@20 { |
| compatible = "ti,tca6416"; |
| reg = <0x20>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| cs42888: cs42888@48 { |
| compatible = "cirrus,cs42888"; |
| reg = <0x48>; |
| clocks = <&clk IMX8QXP_AUD_MCLKOUT0>; |
| clock-names = "mclk"; |
| VA-supply = <®_audio>; |
| VD-supply = <®_audio>; |
| VLS-supply = <®_audio>; |
| VLC-supply = <®_audio>; |
| reset-gpio = <&pca9557_b 1 1>; |
| power-domains = <&pd_mclk_out0>; |
| assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, |
| <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, |
| <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, |
| <&clk IMX8QXP_AUD_MCLKOUT0>; |
| assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; |
| fsl,txs-rxm; |
| status = "okay"; |
| }; |
| |
| ov5640: ov5640@3c { |
| compatible = "ovti,ov5640_v3"; |
| reg = <0x3c>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_parallel_csi>; |
| clocks = <&clk IMX8QXP_PARALLEL_CSI_MISC0_CLK>; |
| clock-names = "csi_mclk"; |
| pwn-gpios = <&gpio3 2 GPIO_ACTIVE_LOW>; |
| rst-gpios = <&gpio3 3 GPIO_ACTIVE_HIGH>; |
| csi_id = <0>; |
| mclk = <24000000>; |
| mclk_source = <0>; |
| status = "okay"; |
| port { |
| ov5640_ep: endpoint { |
| remote-endpoint = <¶llel_csi_ep>; |
| }; |
| }; |
| }; |
| }; |
| |
| &i2c1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-frequency = <100000>; |
| pinctrl-names = "default", "sleep"; |
| pinctrl-0 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst>; |
| pinctrl-1 = <&pinctrl_lpi2c1 &pinctrl_ioexp_rst_sleep>; |
| pinctrl-assert-gpios = <&gpio1 1 GPIO_ACTIVE_HIGH>; |
| status = "okay"; |
| |
| pca9646@71 { |
| compatible = "nxp,pca9646"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0x71>; |
| |
| i2c@0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <0>; |
| |
| max7322: gpio@68 { |
| compatible = "maxim,max7322"; |
| reg = <0x68>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| }; |
| |
| i2c@1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <1>; |
| }; |
| |
| i2c@2 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <2>; |
| |
| fxos8700@1e { |
| compatible = "fsl,fxos8700"; |
| reg = <0x1e>; |
| interrupt-open-drain; |
| }; |
| |
| fxas2100x@21 { |
| compatible = "fsl,fxas2100x"; |
| reg = <0x21>; |
| interrupt-open-drain; |
| }; |
| |
| mpl3115@60 { |
| compatible = "fsl,mpl3115"; |
| reg = <0x60>; |
| interrupt-open-drain; |
| }; |
| }; |
| |
| i2c@3 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| reg = <3>; |
| |
| pca9557_a: gpio@1a { |
| compatible = "nxp,pca9557"; |
| reg = <0x1a>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| pca9557_b: gpio@1d { |
| compatible = "nxp,pca9557"; |
| reg = <0x1d>; |
| gpio-controller; |
| #gpio-cells = <2>; |
| }; |
| |
| isl29023@44 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_isl29023>; |
| compatible = "fsl,isl29023"; |
| reg = <0x44>; |
| rext = <499>; |
| interrupt-parent = <&gpio1>; |
| interrupts = <2 2>; |
| }; |
| }; |
| }; |
| |
| typec_ptn5110: typec@50 { |
| compatible = "usb,tcpci"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_typec>; |
| reg = <0x50>; |
| interrupt-parent = <&gpio1>; |
| interrupts = <3 IRQ_TYPE_LEVEL_LOW>; |
| ss-sel-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; |
| reset-gpios = <&pca9557_a 7 GPIO_ACTIVE_HIGH>; |
| src-pdos = <0x380190c8 0x3803c0c8>; |
| port-type = "drp"; |
| sink-disable; |
| default-role = "source"; |
| status = "okay"; |
| }; |
| }; |
| |
| &sai1 { |
| assigned-clocks = <&clk IMX8QXP_AUD_PLL0_DIV>, |
| <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>, |
| <&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>, |
| <&clk IMX8QXP_AUD_SAI_1_MCLK>; |
| assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sai1>; |
| status = "okay"; |
| }; |
| |
| &usbotg1 { |
| vbus-supply = <®_usb_otg1_vbus>; |
| srp-disable; |
| hnp-disable; |
| adp-disable; |
| power-polarity-active-high; |
| disable-over-current; |
| status = "okay"; |
| }; |
| |
| &usbotg3 { |
| dr_mode = "otg"; |
| extcon = <&typec_ptn5110>; |
| status = "okay"; |
| }; |
| |
| &usbphy1 { |
| fsl,tx-d-cal = <114>; |
| }; |
| |
| &usdhc1 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| pinctrl-1 = <&pinctrl_usdhc1_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc1_200mhz>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; |
| bus-width = <4>; |
| cd-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; |
| wp-gpios = <&gpio4 21 GPIO_ACTIVE_HIGH>; |
| vmmc-supply = <®_usdhc2_vmmc>; |
| status = "okay"; |
| }; |
| |
| &pcieb{ |
| ext_osc = <1>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pcieb>; |
| clkreq-gpio = <&gpio4 1 GPIO_ACTIVE_LOW>; |
| disable-gpio = <&pca9557_a 2 GPIO_ACTIVE_LOW>; |
| reset-gpio = <&gpio4 0 GPIO_ACTIVE_LOW>; |
| epdev_on-supply = <&epdev_on>; |
| status = "okay"; |
| }; |
| |
| &pixel_combiner { |
| status = "okay"; |
| }; |
| |
| &prg1 { |
| status = "okay"; |
| }; |
| |
| &prg2 { |
| status = "okay"; |
| }; |
| |
| &prg3 { |
| status = "okay"; |
| }; |
| |
| &prg4 { |
| status = "okay"; |
| }; |
| |
| &prg5 { |
| status = "okay"; |
| }; |
| |
| &prg6 { |
| status = "okay"; |
| }; |
| |
| &prg7 { |
| status = "okay"; |
| }; |
| |
| &prg8 { |
| status = "okay"; |
| }; |
| |
| &prg9 { |
| status = "okay"; |
| }; |
| |
| &dpr1_channel1 { |
| status = "okay"; |
| }; |
| |
| &dpr1_channel2 { |
| status = "okay"; |
| }; |
| |
| &dpr1_channel3 { |
| status = "okay"; |
| }; |
| |
| &dpr2_channel1 { |
| status = "okay"; |
| }; |
| |
| &dpr2_channel2 { |
| status = "okay"; |
| }; |
| |
| &dpr2_channel3 { |
| status = "okay"; |
| }; |
| |
| &dpu1 { |
| status = "okay"; |
| }; |
| |
| &gpu_3d0 { |
| status = "okay"; |
| }; |
| |
| &imx8_gpu_ss { |
| status = "okay"; |
| }; |
| |
| &mipi_csi_0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| virtual-channel; |
| status = "okay"; |
| |
| /* Camera 0 MIPI CSI-2 (CSIS0) */ |
| port@0 { |
| reg = <0>; |
| mipi_csi0_ep: endpoint { |
| remote-endpoint = <&max9286_0_ep>; |
| data-lanes = <1 2 3 4>; |
| }; |
| }; |
| }; |
| |
| &cameradev { |
| parallel_csi; |
| status = "okay"; |
| }; |
| |
| ¶llel_csi { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "okay"; |
| port@0 { |
| reg = <0>; |
| parallel_csi_ep: endpoint { |
| remote-endpoint = <&ov5640_ep>; |
| }; |
| }; |
| }; |
| |
| &isi_0 { |
| status = "okay"; |
| }; |
| |
| &isi_1 { |
| status = "okay"; |
| }; |
| |
| &isi_2 { |
| status = "okay"; |
| }; |
| |
| &isi_3 { |
| status = "okay"; |
| }; |
| |
| &isi_4 { |
| interface = <6 0 2>; /* INPUT: 6-PARALLEL CSI */ |
| parallel_csi; |
| status = "okay"; |
| }; |
| |
| &gpio3 { |
| pinctrl-name = "default"; |
| pinctrl-0 = <&pinctrl_gpio3>; |
| }; |
| |
| &i2c0_csi0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_csi0_lpi2c0>; |
| clock-frequency = <100000>; |
| status = "okay"; |
| |
| max9286_mipi@6A { |
| compatible = "maxim,max9286_mipi"; |
| reg = <0x6A>; |
| clocks = <&clk IMX8QXP_CLK_DUMMY>; |
| clock-names = "capture_mclk"; |
| mclk = <27000000>; |
| mclk_source = <0>; |
| pwn-gpios = <&gpio3 7 GPIO_ACTIVE_HIGH>; |
| virtual-channel; |
| status = "okay"; |
| port { |
| max9286_0_ep: endpoint { |
| remote-endpoint = <&mipi_csi0_ep>; |
| data-lanes = <1 2 3 4>; |
| }; |
| }; |
| }; |
| }; |
| |
| &vpu { |
| status = "disabled"; |
| }; |
| |
| &vpu_decoder { |
| core_type = <1>; |
| status = "okay"; |
| }; |
| |
| &vpu_encoder { |
| status = "okay"; |
| }; |
| |
| &pwm_mipi_lvds0 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pwm_mipi_lvds0>; |
| status = "okay"; |
| }; |
| |
| /* DSI/LVDS port 0 */ |
| &i2c0_mipi_lvds0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c0_mipi_lvds0>; |
| clock-frequency = <100000>; |
| status = "okay"; |
| |
| lvds-to-hdmi-bridge@4c { |
| compatible = "ite,it6263"; |
| reg = <0x4c>; |
| reset-gpios = <&pca9557_a 6 GPIO_ACTIVE_LOW>; |
| |
| port { |
| it6263_0_in: endpoint { |
| clock-lanes = <4>; |
| data-lanes = <0 1 2 3>; |
| remote-endpoint = <&lvds0_out>; |
| }; |
| }; |
| }; |
| |
| adv_bridge1: adv7535@3d { |
| compatible = "adi,adv7535", "adi,adv7533"; |
| reg = <0x3d>; |
| adi,dsi-lanes = <4>; |
| adi,dsi-channel = <1>; |
| interrupt-parent = <&gpio1>; |
| interrupts = <28 IRQ_TYPE_LEVEL_LOW>; |
| status = "okay"; |
| |
| port { |
| adv7535_1_in: endpoint { |
| remote-endpoint = <&mipi_dsi_bridge1_out>; |
| }; |
| }; |
| }; |
| |
| }; |
| |
| &ldb1_phy { |
| status = "okay"; |
| }; |
| |
| &ldb1 { |
| status = "okay"; |
| |
| lvds-channel@0 { |
| fsl,data-mapping = "jeida"; |
| fsl,data-width = <24>; |
| status = "okay"; |
| |
| port@1 { |
| reg = <1>; |
| |
| lvds0_out: endpoint { |
| remote-endpoint = <&it6263_0_in>; |
| }; |
| }; |
| }; |
| }; |
| |
| &mipi_dsi_phy1 { |
| status = "okay"; |
| }; |
| |
| &mipi_dsi1 { |
| pwr-delay = <10>; |
| status = "okay"; |
| }; |
| |
| &mipi_dsi_bridge1 { |
| status = "okay"; |
| |
| port@1 { |
| mipi_dsi_bridge1_out: endpoint { |
| remote-endpoint = <&adv7535_1_in>; |
| }; |
| }; |
| }; |
| |
| &pwm_mipi_lvds1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pwm_mipi_lvds1>; |
| status = "okay"; |
| }; |
| |
| /* DSI/LVDS port 1 */ |
| &i2c0_mipi_lvds1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c0_mipi_lvds1>; |
| clock-frequency = <100000>; |
| status = "okay"; |
| |
| lvds-to-hdmi-bridge@4c { |
| compatible = "ite,it6263"; |
| reg = <0x4c>; |
| reset-gpios = <&pca9557_b 7 GPIO_ACTIVE_LOW>; |
| |
| port { |
| it6263_1_in: endpoint { |
| clock-lanes = <4>; |
| data-lanes = <0 1 2 3>; |
| remote-endpoint = <&lvds1_out>; |
| }; |
| }; |
| }; |
| |
| adv_bridge2: adv7535@3d { |
| compatible = "adi,adv7535", "adi,adv7533"; |
| reg = <0x3d>; |
| adi,dsi-lanes = <4>; |
| adi,dsi-channel = <1>; |
| interrupt-parent = <&gpio2>; |
| interrupts = <0 IRQ_TYPE_LEVEL_LOW>; |
| status = "okay"; |
| |
| port { |
| adv7535_2_in: endpoint { |
| remote-endpoint = <&mipi_dsi_bridge2_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| &ldb2_phy { |
| status = "okay"; |
| }; |
| |
| &ldb2 { |
| status = "okay"; |
| |
| lvds-channel@0 { |
| fsl,data-mapping = "jeida"; |
| fsl,data-width = <24>; |
| status = "okay"; |
| |
| port@1 { |
| reg = <1>; |
| |
| lvds1_out: endpoint { |
| remote-endpoint = <&it6263_1_in>; |
| }; |
| }; |
| }; |
| }; |
| |
| &mipi_dsi_phy2 { |
| status = "okay"; |
| }; |
| |
| &mipi_dsi2 { |
| pwr-delay = <10>; |
| status = "okay"; |
| }; |
| |
| &mipi_dsi_bridge2 { |
| status = "okay"; |
| |
| port@1 { |
| mipi_dsi_bridge2_out: endpoint { |
| remote-endpoint = <&adv7535_2_in>; |
| }; |
| }; |
| }; |
| |
| &tsens { |
| tsens-num = <3>; |
| }; |
| |
| &thermal_zones { |
| pmic-thermal0 { |
| polling-delay-passive = <250>; |
| polling-delay = <2000>; |
| thermal-sensors = <&tsens 2>; |
| trips { |
| pmic_alert0: trip0 { |
| temperature = <110000>; |
| hysteresis = <2000>; |
| type = "passive"; |
| }; |
| pmic_crit0: trip1 { |
| temperature = <125000>; |
| hysteresis = <2000>; |
| type = "critical"; |
| }; |
| }; |
| cooling-maps { |
| map0 { |
| trip = <&pmic_alert0>; |
| cooling-device = |
| <&A35_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; |
| }; |
| }; |
| }; |
| }; |
