arch/arm64/boot/dts/freescale/fsl-imx8mq-evk-root.dts

/*
 * Copyright 2018 NXP
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License
 * as published by the Free Software Foundation; either version 2
 * of the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 */

#include "fsl-imx8mq-evk.dts"

/ {
	interrupt-parent = <&gic>;
};

/delete-node/ &gpc;

&CPU_SLEEP {
	/* We are not using GPC for now, need set 0 to avoid hang */
	arm,psci-suspend-param = <0x0>;
};

&clk {
	init-on-array = <IMX8MQ_CLK_DRAM_CORE IMX8MQ_CLK_AHB
			 IMX8MQ_CLK_NOC IMX8MQ_CLK_NOC_APB
			 IMX8MQ_CLK_USB_BUS
			 IMX8MQ_CLK_MAIN_AXI IMX8MQ_CLK_A53_CG
			 IMX8MQ_CLK_AUDIO_AHB IMX8MQ_CLK_TMU_ROOT
			 IMX8MQ_CLK_DRAM_APB
			 IMX8MQ_CLK_UART2_ROOT
			 IMX8MQ_CLK_UART2
			 IMX8MQ_CLK_NAND_USDHC_BUS>;
};

&iomuxc {
	imx8mq-evk {
		/*
		 * Used for the 2nd Linux.
		 * TODO: M4 may use these pins.
		 */
		pinctrl_uart2: uart2grp {
			fsl,pins = <
				MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX	0x49
				MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX	0x49
			>;
		};
	};
};

&{/busfreq} {
	/* Disable busfreq, to avoid 1st Linux busfreq crash other inmates */
	status = "disabled";
};

&resmem {
	jh_reserved: jh@0xfdc00000 {
		no-map;
		reg = <0 0xfdc00000 0x0 0x400000>;
	};

	inmate_reserved: inmate@0xc0000000 {
		no-map;
		reg = <0 0xc0000000 0x0 0x3dc00000>;
	};

	loader_reserved: loader@0xbff00000 {
		no-map;
		reg = <0 0xbff00000 0x0 0x00100000>;
	};

	ivshmem_reserved: ivshmem@0xbfe00000 {
		no-map;
		reg = <0 0xbfe00000 0x0 0x00100000>;
	};

	ivshmem2_reserved: ivshmem2@0xbfd00000 {
		no-map;
		reg = <0 0xbfd00000 0x0 0x00100000>;
	};

	pci_reserved: pci@0xbfc00000 {
		no-map;
		reg = <0 0xbfb00000 0x0 0x00200000>;
	};
};

&uart1 {
	/* uart2 is used by the 2nd OS, so configure pin and clk */
	pinctrl-0 = <&pinctrl_uart1>, <&pinctrl_uart2>;
	assigned-clocks = <&clk IMX8MQ_CLK_UART1>,
			<&clk IMX8MQ_CLK_UART2>;
	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>,
			<&clk IMX8MQ_CLK_25M>;
};

&usdhc1 {
	status = "disabled";
};

&usdhc2 {
	/* sdhc1 is used by 2nd linux, configure the pin */
	pinctrl-0 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
	pinctrl-1 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
	pinctrl-2 = <&pinctrl_usdhc1>, <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
};