| /* |
| * Device Tree Source for the r8a7792 SoC |
| * |
| * Copyright (C) 2016 Cogent Embedded Inc. |
| * |
| * This file is licensed under the terms of the GNU General Public License |
| * version 2. This program is licensed "as is" without any warranty of any |
| * kind, whether express or implied. |
| */ |
| |
| #include <dt-bindings/clock/r8a7792-clock.h> |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/power/r8a7792-sysc.h> |
| |
| / { |
| compatible = "renesas,r8a7792"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| aliases { |
| i2c0 = &i2c0; |
| i2c1 = &i2c1; |
| i2c2 = &i2c2; |
| i2c3 = &i2c3; |
| i2c4 = &i2c4; |
| i2c5 = &i2c5; |
| spi0 = &qspi; |
| spi1 = &msiof0; |
| spi2 = &msiof1; |
| vin0 = &vin0; |
| vin1 = &vin1; |
| vin2 = &vin2; |
| vin3 = &vin3; |
| vin4 = &vin4; |
| vin5 = &vin5; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| enable-method = "renesas,apmu"; |
| |
| cpu0: cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <0>; |
| clock-frequency = <1000000000>; |
| clocks = <&z_clk>; |
| power-domains = <&sysc R8A7792_PD_CA15_CPU0>; |
| next-level-cache = <&L2_CA15>; |
| }; |
| |
| cpu1: cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,cortex-a15"; |
| reg = <1>; |
| clock-frequency = <1000000000>; |
| power-domains = <&sysc R8A7792_PD_CA15_CPU1>; |
| next-level-cache = <&L2_CA15>; |
| }; |
| |
| L2_CA15: cache-controller-0 { |
| compatible = "cache"; |
| cache-unified; |
| cache-level = <2>; |
| power-domains = <&sysc R8A7792_PD_CA15_SCU>; |
| }; |
| }; |
| |
| soc { |
| compatible = "simple-bus"; |
| interrupt-parent = <&gic>; |
| |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| apmu@e6152000 { |
| compatible = "renesas,r8a7792-apmu", "renesas,apmu"; |
| reg = <0 0xe6152000 0 0x188>; |
| cpus = <&cpu0 &cpu1>; |
| }; |
| |
| gic: interrupt-controller@f1001000 { |
| compatible = "arm,gic-400"; |
| #interrupt-cells = <3>; |
| interrupt-controller; |
| reg = <0 0xf1001000 0 0x1000>, |
| <0 0xf1002000 0 0x2000>, |
| <0 0xf1004000 0 0x2000>, |
| <0 0xf1006000 0 0x2000>; |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_HIGH)>; |
| clocks = <&mstp4_clks R8A7792_CLK_INTC_SYS>; |
| clock-names = "clk"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| irqc: interrupt-controller@e61c0000 { |
| compatible = "renesas,irqc-r8a7792", "renesas,irqc"; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| reg = <0 0xe61c0000 0 0x200>; |
| interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp4_clks R8A7792_CLK_IRQC>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| timer { |
| compatible = "arm,armv7-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | |
| IRQ_TYPE_LEVEL_LOW)>; |
| }; |
| |
| rst: reset-controller@e6160000 { |
| compatible = "renesas,r8a7792-rst"; |
| reg = <0 0xe6160000 0 0x0100>; |
| }; |
| |
| prr: chipid@ff000044 { |
| compatible = "renesas,prr"; |
| reg = <0 0xff000044 0 4>; |
| }; |
| |
| sysc: system-controller@e6180000 { |
| compatible = "renesas,r8a7792-sysc"; |
| reg = <0 0xe6180000 0 0x0200>; |
| #power-domain-cells = <1>; |
| }; |
| |
| pfc: pin-controller@e6060000 { |
| compatible = "renesas,pfc-r8a7792"; |
| reg = <0 0xe6060000 0 0x144>; |
| }; |
| |
| gpio0: gpio@e6050000 { |
| compatible = "renesas,gpio-r8a7792", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6050000 0 0x50>; |
| interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 0 29>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&mstp9_clks R8A7792_CLK_GPIO0>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| gpio1: gpio@e6051000 { |
| compatible = "renesas,gpio-r8a7792", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6051000 0 0x50>; |
| interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 32 23>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&mstp9_clks R8A7792_CLK_GPIO1>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| gpio2: gpio@e6052000 { |
| compatible = "renesas,gpio-r8a7792", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6052000 0 0x50>; |
| interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 64 32>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&mstp9_clks R8A7792_CLK_GPIO2>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| gpio3: gpio@e6053000 { |
| compatible = "renesas,gpio-r8a7792", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6053000 0 0x50>; |
| interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 96 28>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&mstp9_clks R8A7792_CLK_GPIO3>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| gpio4: gpio@e6054000 { |
| compatible = "renesas,gpio-r8a7792", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6054000 0 0x50>; |
| interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 128 17>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&mstp9_clks R8A7792_CLK_GPIO4>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| gpio5: gpio@e6055000 { |
| compatible = "renesas,gpio-r8a7792", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6055000 0 0x50>; |
| interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 160 17>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&mstp9_clks R8A7792_CLK_GPIO5>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| gpio6: gpio@e6055100 { |
| compatible = "renesas,gpio-r8a7792", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6055100 0 0x50>; |
| interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 192 17>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&mstp9_clks R8A7792_CLK_GPIO6>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| gpio7: gpio@e6055200 { |
| compatible = "renesas,gpio-r8a7792", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6055200 0 0x50>; |
| interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 224 17>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&mstp9_clks R8A7792_CLK_GPIO7>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| gpio8: gpio@e6055300 { |
| compatible = "renesas,gpio-r8a7792", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6055300 0 0x50>; |
| interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 256 17>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&mstp9_clks R8A7792_CLK_GPIO8>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| gpio9: gpio@e6055400 { |
| compatible = "renesas,gpio-r8a7792", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6055400 0 0x50>; |
| interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 288 17>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&mstp9_clks R8A7792_CLK_GPIO9>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| gpio10: gpio@e6055500 { |
| compatible = "renesas,gpio-r8a7792", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6055500 0 0x50>; |
| interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 320 32>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&mstp9_clks R8A7792_CLK_GPIO10>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| gpio11: gpio@e6055600 { |
| compatible = "renesas,gpio-r8a7792", |
| "renesas,gpio-rcar"; |
| reg = <0 0xe6055600 0 0x50>; |
| interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; |
| #gpio-cells = <2>; |
| gpio-controller; |
| gpio-ranges = <&pfc 0 352 30>; |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| clocks = <&mstp9_clks R8A7792_CLK_GPIO11>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| dmac0: dma-controller@e6700000 { |
| compatible = "renesas,dmac-r8a7792", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe6700000 0 0x20000>; |
| interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 210 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14"; |
| clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC0>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| #dma-cells = <1>; |
| dma-channels = <15>; |
| }; |
| |
| dmac1: dma-controller@e6720000 { |
| compatible = "renesas,dmac-r8a7792", |
| "renesas,rcar-dmac"; |
| reg = <0 0xe6720000 0 0x20000>; |
| interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH |
| GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "error", |
| "ch0", "ch1", "ch2", "ch3", |
| "ch4", "ch5", "ch6", "ch7", |
| "ch8", "ch9", "ch10", "ch11", |
| "ch12", "ch13", "ch14"; |
| clocks = <&mstp2_clks R8A7792_CLK_SYS_DMAC1>; |
| clock-names = "fck"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| #dma-cells = <1>; |
| dma-channels = <15>; |
| }; |
| |
| scif0: serial@e6e60000 { |
| compatible = "renesas,scif-r8a7792", |
| "renesas,rcar-gen2-scif", "renesas,scif"; |
| reg = <0 0xe6e60000 0 64>; |
| interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp7_clks R8A7792_CLK_SCIF0>, <&zs_clk>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x29>, <&dmac0 0x2a>, |
| <&dmac1 0x29>, <&dmac1 0x2a>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| scif1: serial@e6e68000 { |
| compatible = "renesas,scif-r8a7792", |
| "renesas,rcar-gen2-scif", "renesas,scif"; |
| reg = <0 0xe6e68000 0 64>; |
| interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp7_clks R8A7792_CLK_SCIF1>, <&zs_clk>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x2d>, <&dmac0 0x2e>, |
| <&dmac1 0x2d>, <&dmac1 0x2e>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| scif2: serial@e6e58000 { |
| compatible = "renesas,scif-r8a7792", |
| "renesas,rcar-gen2-scif", "renesas,scif"; |
| reg = <0 0xe6e58000 0 64>; |
| interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp7_clks R8A7792_CLK_SCIF2>, <&zs_clk>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x2b>, <&dmac0 0x2c>, |
| <&dmac1 0x2b>, <&dmac1 0x2c>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| scif3: serial@e6ea8000 { |
| compatible = "renesas,scif-r8a7792", |
| "renesas,rcar-gen2-scif", "renesas,scif"; |
| reg = <0 0xe6ea8000 0 64>; |
| interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp7_clks R8A7792_CLK_SCIF3>, <&zs_clk>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x2f>, <&dmac0 0x30>, |
| <&dmac1 0x2f>, <&dmac1 0x30>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| hscif0: serial@e62c0000 { |
| compatible = "renesas,hscif-r8a7792", |
| "renesas,rcar-gen2-hscif", "renesas,hscif"; |
| reg = <0 0xe62c0000 0 96>; |
| interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp7_clks R8A7792_CLK_HSCIF0>, <&zs_clk>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x39>, <&dmac0 0x3a>, |
| <&dmac1 0x39>, <&dmac1 0x3a>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| hscif1: serial@e62c8000 { |
| compatible = "renesas,hscif-r8a7792", |
| "renesas,rcar-gen2-hscif", "renesas,hscif"; |
| reg = <0 0xe62c8000 0 96>; |
| interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp7_clks R8A7792_CLK_HSCIF1>, <&zs_clk>, |
| <&scif_clk>; |
| clock-names = "fck", "brg_int", "scif_clk"; |
| dmas = <&dmac0 0x4d>, <&dmac0 0x4e>, |
| <&dmac1 0x4d>, <&dmac1 0x4e>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| icram0: sram@e63a0000 { |
| compatible = "mmio-sram"; |
| reg = <0 0xe63a0000 0 0x12000>; |
| }; |
| |
| icram1: sram@e63c0000 { |
| compatible = "mmio-sram"; |
| reg = <0 0xe63c0000 0 0x1000>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges = <0 0 0xe63c0000 0x1000>; |
| |
| smp-sram@0 { |
| compatible = "renesas,smp-sram"; |
| reg = <0 0x10>; |
| }; |
| }; |
| |
| sdhi0: sd@ee100000 { |
| compatible = "renesas,sdhi-r8a7792"; |
| reg = <0 0xee100000 0 0x328>; |
| interrupts = <0 165 IRQ_TYPE_LEVEL_HIGH>; |
| dmas = <&dmac0 0xcd>, <&dmac0 0xce>, |
| <&dmac1 0xcd>, <&dmac1 0xce>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| clocks = <&mstp3_clks R8A7792_CLK_SDHI0>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| jpu: jpeg-codec@fe980000 { |
| compatible = "renesas,jpu-r8a7792", |
| "renesas,rcar-gen2-jpu"; |
| reg = <0 0xfe980000 0 0x10300>; |
| interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp1_clks R8A7792_CLK_JPU>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| avb: ethernet@e6800000 { |
| compatible = "renesas,etheravb-r8a7792", |
| "renesas,etheravb-rcar-gen2"; |
| reg = <0 0xe6800000 0 0x800>, <0 0xee0e8000 0 0x4000>; |
| interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp8_clks R8A7792_CLK_ETHERAVB>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| /* I2C doesn't need pinmux */ |
| i2c0: i2c@e6508000 { |
| compatible = "renesas,i2c-r8a7792", |
| "renesas,rcar-gen2-i2c"; |
| reg = <0 0xe6508000 0 0x40>; |
| interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp9_clks R8A7792_CLK_I2C0>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| i2c-scl-internal-delay-ns = <6>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c1: i2c@e6518000 { |
| compatible = "renesas,i2c-r8a7792", |
| "renesas,rcar-gen2-i2c"; |
| reg = <0 0xe6518000 0 0x40>; |
| interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp9_clks R8A7792_CLK_I2C1>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| i2c-scl-internal-delay-ns = <6>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c2: i2c@e6530000 { |
| compatible = "renesas,i2c-r8a7792", |
| "renesas,rcar-gen2-i2c"; |
| reg = <0 0xe6530000 0 0x40>; |
| interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp9_clks R8A7792_CLK_I2C2>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| i2c-scl-internal-delay-ns = <6>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c3: i2c@e6540000 { |
| compatible = "renesas,i2c-r8a7792", |
| "renesas,rcar-gen2-i2c"; |
| reg = <0 0xe6540000 0 0x40>; |
| interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp9_clks R8A7792_CLK_I2C3>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| i2c-scl-internal-delay-ns = <6>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@e6520000 { |
| compatible = "renesas,i2c-r8a7792", |
| "renesas,rcar-gen2-i2c"; |
| reg = <0 0xe6520000 0 0x40>; |
| interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp9_clks R8A7792_CLK_I2C4>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| i2c-scl-internal-delay-ns = <6>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| i2c5: i2c@e6528000 { |
| compatible = "renesas,i2c-r8a7792", |
| "renesas,rcar-gen2-i2c"; |
| reg = <0 0xe6528000 0 0x40>; |
| interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp9_clks R8A7792_CLK_I2C5>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| i2c-scl-internal-delay-ns = <110>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| qspi: spi@e6b10000 { |
| compatible = "renesas,qspi-r8a7792", "renesas,qspi"; |
| reg = <0 0xe6b10000 0 0x2c>; |
| interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp9_clks R8A7792_CLK_QSPI_MOD>; |
| dmas = <&dmac0 0x17>, <&dmac0 0x18>, |
| <&dmac1 0x17>, <&dmac1 0x18>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| num-cs = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| msiof0: spi@e6e20000 { |
| compatible = "renesas,msiof-r8a7792", |
| "renesas,rcar-gen2-msiof"; |
| reg = <0 0xe6e20000 0 0x0064>; |
| interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp0_clks R8A7792_CLK_MSIOF0>; |
| dmas = <&dmac0 0x51>, <&dmac0 0x52>, |
| <&dmac1 0x51>, <&dmac1 0x52>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| msiof1: spi@e6e10000 { |
| compatible = "renesas,msiof-r8a7792", |
| "renesas,rcar-gen2-msiof"; |
| reg = <0 0xe6e10000 0 0x0064>; |
| interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp2_clks R8A7792_CLK_MSIOF1>; |
| dmas = <&dmac0 0x55>, <&dmac0 0x56>, |
| <&dmac1 0x55>, <&dmac1 0x56>; |
| dma-names = "tx", "rx", "tx", "rx"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "disabled"; |
| }; |
| |
| du: display@feb00000 { |
| compatible = "renesas,du-r8a7792"; |
| reg = <0 0xfeb00000 0 0x40000>; |
| reg-names = "du"; |
| interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp7_clks R8A7792_CLK_DU0>, |
| <&mstp7_clks R8A7792_CLK_DU1>; |
| clock-names = "du.0", "du.1"; |
| status = "disabled"; |
| |
| ports { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| du_out_rgb0: endpoint { |
| }; |
| }; |
| port@1 { |
| reg = <1>; |
| du_out_rgb1: endpoint { |
| }; |
| }; |
| }; |
| }; |
| |
| can0: can@e6e80000 { |
| compatible = "renesas,can-r8a7792", |
| "renesas,rcar-gen2-can"; |
| reg = <0 0xe6e80000 0 0x1000>; |
| interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp9_clks R8A7792_CLK_CAN0>, |
| <&rcan_clk>, <&can_clk>; |
| clock-names = "clkp1", "clkp2", "can_clk"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| can1: can@e6e88000 { |
| compatible = "renesas,can-r8a7792", |
| "renesas,rcar-gen2-can"; |
| reg = <0 0xe6e88000 0 0x1000>; |
| interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp9_clks R8A7792_CLK_CAN1>, |
| <&rcan_clk>, <&can_clk>; |
| clock-names = "clkp1", "clkp2", "can_clk"; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| vin0: video@e6ef0000 { |
| compatible = "renesas,vin-r8a7792", |
| "renesas,rcar-gen2-vin"; |
| reg = <0 0xe6ef0000 0 0x1000>; |
| interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp8_clks R8A7792_CLK_VIN0>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| vin1: video@e6ef1000 { |
| compatible = "renesas,vin-r8a7792", |
| "renesas,rcar-gen2-vin"; |
| reg = <0 0xe6ef1000 0 0x1000>; |
| interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp8_clks R8A7792_CLK_VIN1>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| vin2: video@e6ef2000 { |
| compatible = "renesas,vin-r8a7792", |
| "renesas,rcar-gen2-vin"; |
| reg = <0 0xe6ef2000 0 0x1000>; |
| interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp8_clks R8A7792_CLK_VIN2>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| vin3: video@e6ef3000 { |
| compatible = "renesas,vin-r8a7792", |
| "renesas,rcar-gen2-vin"; |
| reg = <0 0xe6ef3000 0 0x1000>; |
| interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp8_clks R8A7792_CLK_VIN3>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| vin4: video@e6ef4000 { |
| compatible = "renesas,vin-r8a7792", |
| "renesas,rcar-gen2-vin"; |
| reg = <0 0xe6ef4000 0 0x1000>; |
| interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp8_clks R8A7792_CLK_VIN4>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| vin5: video@e6ef5000 { |
| compatible = "renesas,vin-r8a7792", |
| "renesas,rcar-gen2-vin"; |
| reg = <0 0xe6ef5000 0 0x1000>; |
| interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp8_clks R8A7792_CLK_VIN5>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| status = "disabled"; |
| }; |
| |
| vsp1@fe928000 { |
| compatible = "renesas,vsp1"; |
| reg = <0 0xfe928000 0 0x8000>; |
| interrupts = <GIC_SPI 267 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp1_clks R8A7792_CLK_VSP1_SY>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| vsp1@fe930000 { |
| compatible = "renesas,vsp1"; |
| reg = <0 0xfe930000 0 0x8000>; |
| interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp1_clks R8A7792_CLK_VSP1DU0>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| vsp1@fe938000 { |
| compatible = "renesas,vsp1"; |
| reg = <0 0xfe938000 0 0x8000>; |
| interrupts = <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&mstp1_clks R8A7792_CLK_VSP1DU1>; |
| power-domains = <&sysc R8A7792_PD_ALWAYS_ON>; |
| }; |
| |
| /* Special CPG clocks */ |
| cpg_clocks: cpg_clocks@e6150000 { |
| compatible = "renesas,r8a7792-cpg-clocks", |
| "renesas,rcar-gen2-cpg-clocks"; |
| reg = <0 0xe6150000 0 0x1000>; |
| clocks = <&extal_clk>; |
| #clock-cells = <1>; |
| clock-output-names = "main", "pll0", "pll1", "pll3", |
| "lb", "qspi"; |
| #power-domain-cells = <0>; |
| }; |
| |
| /* Fixed factor clocks */ |
| pll1_div2_clk: pll1_div2 { |
| compatible = "fixed-factor-clock"; |
| clocks = <&cpg_clocks R8A7792_CLK_PLL1>; |
| #clock-cells = <0>; |
| clock-div = <2>; |
| clock-mult = <1>; |
| }; |
| z_clk: z { |
| compatible = "fixed-factor-clock"; |
| clocks = <&cpg_clocks R8A7792_CLK_PLL0>; |
| #clock-cells = <0>; |
| clock-div = <1>; |
| clock-mult = <1>; |
| }; |
| zx_clk: zx { |
| compatible = "fixed-factor-clock"; |
| clocks = <&cpg_clocks R8A7792_CLK_PLL1>; |
| #clock-cells = <0>; |
| clock-div = <3>; |
| clock-mult = <1>; |
| }; |
| zs_clk: zs { |
| compatible = "fixed-factor-clock"; |
| clocks = <&cpg_clocks R8A7792_CLK_PLL1>; |
| #clock-cells = <0>; |
| clock-div = <6>; |
| clock-mult = <1>; |
| }; |
| hp_clk: hp { |
| compatible = "fixed-factor-clock"; |
| clocks = <&cpg_clocks R8A7792_CLK_PLL1>; |
| #clock-cells = <0>; |
| clock-div = <12>; |
| clock-mult = <1>; |
| }; |
| p_clk: p { |
| compatible = "fixed-factor-clock"; |
| clocks = <&cpg_clocks R8A7792_CLK_PLL1>; |
| #clock-cells = <0>; |
| clock-div = <24>; |
| clock-mult = <1>; |
| }; |
| cp_clk: cp { |
| compatible = "fixed-factor-clock"; |
| clocks = <&cpg_clocks R8A7792_CLK_PLL1>; |
| #clock-cells = <0>; |
| clock-div = <48>; |
| clock-mult = <1>; |
| }; |
| mp_clk: mp { |
| compatible = "fixed-factor-clock"; |
| clocks = <&pll1_div2_clk>; |
| #clock-cells = <0>; |
| clock-div = <15>; |
| clock-mult = <1>; |
| }; |
| m2_clk: m2 { |
| compatible = "fixed-factor-clock"; |
| clocks = <&cpg_clocks R8A7792_CLK_PLL1>; |
| #clock-cells = <0>; |
| clock-div = <8>; |
| clock-mult = <1>; |
| }; |
| sd_clk: sd { |
| compatible = "fixed-factor-clock"; |
| clocks = <&pll1_div2_clk>; |
| #clock-cells = <0>; |
| clock-div = <8>; |
| clock-mult = <1>; |
| }; |
| rcan_clk: rcan { |
| compatible = "fixed-factor-clock"; |
| clocks = <&pll1_div2_clk>; |
| #clock-cells = <0>; |
| clock-div = <49>; |
| clock-mult = <1>; |
| }; |
| zg_clk: zg { |
| compatible = "fixed-factor-clock"; |
| clocks = <&cpg_clocks R8A7792_CLK_PLL1>; |
| #clock-cells = <0>; |
| clock-div = <5>; |
| clock-mult = <1>; |
| }; |
| |
| /* Gate clocks */ |
| mstp0_clks: mstp0_clks@e6150130 { |
| compatible = "renesas,r8a7792-mstp-clocks", |
| "renesas,cpg-mstp-clocks"; |
| reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>; |
| clocks = <&mp_clk>; |
| #clock-cells = <1>; |
| clock-indices = <R8A7792_CLK_MSIOF0>; |
| clock-output-names = "msiof0"; |
| }; |
| mstp1_clks: mstp1_clks@e6150134 { |
| compatible = "renesas,r8a7792-mstp-clocks", |
| "renesas,cpg-mstp-clocks"; |
| reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>; |
| clocks = <&m2_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>; |
| #clock-cells = <1>; |
| clock-indices = < |
| R8A7792_CLK_JPU |
| R8A7792_CLK_VSP1DU1 R8A7792_CLK_VSP1DU0 |
| R8A7792_CLK_VSP1_SY |
| >; |
| clock-output-names = "jpu", "vsp1du1", "vsp1du0", |
| "vsp1-sy"; |
| }; |
| mstp2_clks: mstp2_clks@e6150138 { |
| compatible = "renesas,r8a7792-mstp-clocks", |
| "renesas,cpg-mstp-clocks"; |
| reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>; |
| clocks = <&mp_clk>, <&zs_clk>, <&zs_clk>; |
| #clock-cells = <1>; |
| clock-indices = < |
| R8A7792_CLK_MSIOF1 |
| R8A7792_CLK_SYS_DMAC1 R8A7792_CLK_SYS_DMAC0 |
| >; |
| clock-output-names = "msiof1", "sys-dmac1", "sys-dmac0"; |
| }; |
| mstp3_clks: mstp3_clks@e615013c { |
| compatible = "renesas,r8a7792-mstp-clocks", |
| "renesas,cpg-mstp-clocks"; |
| reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; |
| clocks = <&sd_clk>; |
| #clock-cells = <1>; |
| renesas,clock-indices = <R8A7792_CLK_SDHI0>; |
| clock-output-names = "sdhi0"; |
| }; |
| mstp4_clks: mstp4_clks@e6150140 { |
| compatible = "renesas,r8a7792-mstp-clocks", |
| "renesas,cpg-mstp-clocks"; |
| reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>; |
| clocks = <&cp_clk>, <&zs_clk>; |
| #clock-cells = <1>; |
| clock-indices = < |
| R8A7792_CLK_IRQC R8A7792_CLK_INTC_SYS |
| >; |
| clock-output-names = "irqc", "intc-sys"; |
| }; |
| mstp7_clks: mstp7_clks@e615014c { |
| compatible = "renesas,r8a7792-mstp-clocks", |
| "renesas,cpg-mstp-clocks"; |
| reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>; |
| clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&p_clk>, |
| <&p_clk>, <&p_clk>, <&zx_clk>, <&zx_clk>; |
| #clock-cells = <1>; |
| clock-indices = < |
| R8A7792_CLK_HSCIF1 R8A7792_CLK_HSCIF0 |
| R8A7792_CLK_SCIF3 R8A7792_CLK_SCIF2 |
| R8A7792_CLK_SCIF1 R8A7792_CLK_SCIF0 |
| R8A7792_CLK_DU1 R8A7792_CLK_DU0 |
| >; |
| clock-output-names = "hscif1", "hscif0", "scif3", |
| "scif2", "scif1", "scif0", |
| "du1", "du0"; |
| }; |
| mstp8_clks: mstp8_clks@e6150990 { |
| compatible = "renesas,r8a7792-mstp-clocks", |
| "renesas,cpg-mstp-clocks"; |
| reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>; |
| clocks = <&zg_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>, |
| <&zg_clk>, <&zg_clk>, <&hp_clk>; |
| #clock-cells = <1>; |
| clock-indices = < |
| R8A7792_CLK_VIN5 R8A7792_CLK_VIN4 |
| R8A7792_CLK_VIN3 R8A7792_CLK_VIN2 |
| R8A7792_CLK_VIN1 R8A7792_CLK_VIN0 |
| R8A7792_CLK_ETHERAVB |
| >; |
| clock-output-names = "vin5", "vin4", "vin3", "vin2", |
| "vin1", "vin0", "etheravb"; |
| }; |
| mstp9_clks: mstp9_clks@e6150994 { |
| compatible = "renesas,r8a7792-mstp-clocks", |
| "renesas,cpg-mstp-clocks"; |
| reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; |
| clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, |
| <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, |
| <&cp_clk>, <&cp_clk>, <&p_clk>, <&p_clk>, |
| <&cpg_clocks R8A7792_CLK_QSPI>, |
| <&cp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>, |
| <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; |
| #clock-cells = <1>; |
| clock-indices = < |
| R8A7792_CLK_GPIO7 R8A7792_CLK_GPIO6 |
| R8A7792_CLK_GPIO5 R8A7792_CLK_GPIO4 |
| R8A7792_CLK_GPIO3 R8A7792_CLK_GPIO2 |
| R8A7792_CLK_GPIO1 R8A7792_CLK_GPIO0 |
| R8A7792_CLK_GPIO11 R8A7792_CLK_GPIO10 |
| R8A7792_CLK_CAN1 R8A7792_CLK_CAN0 |
| R8A7792_CLK_QSPI_MOD |
| R8A7792_CLK_GPIO9 R8A7792_CLK_GPIO8 |
| R8A7792_CLK_I2C5 R8A7792_CLK_I2C4 |
| R8A7792_CLK_I2C3 R8A7792_CLK_I2C2 |
| R8A7792_CLK_I2C1 R8A7792_CLK_I2C0 |
| >; |
| clock-output-names = |
| "gpio7", "gpio6", "gpio5", "gpio4", |
| "gpio3", "gpio2", "gpio1", "gpio0", |
| "gpio11", "gpio10", "can1", "can0", |
| "qspi_mod", "gpio9", "gpio8", |
| "i2c5", "i2c4", "i2c3", "i2c2", |
| "i2c1", "i2c0"; |
| }; |
| }; |
| |
| /* External root clock */ |
| extal_clk: extal { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board. */ |
| clock-frequency = <0>; |
| }; |
| |
| /* External SCIF clock */ |
| scif_clk: scif { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board. */ |
| clock-frequency = <0>; |
| }; |
| |
| /* External CAN clock */ |
| can_clk: can { |
| compatible = "fixed-clock"; |
| #clock-cells = <0>; |
| /* This value must be overridden by the board. */ |
| clock-frequency = <0>; |
| }; |
| }; |
