| |
| /* |
| * Copyright 2013-2015 Freescale Semiconductor, Inc. |
| * Copyright 2018 NXP |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| * |
| */ |
| |
| #include <dt-bindings/interrupt-controller/irq.h> |
| #include "imx6dl-pinfunc.h" |
| #include "imx6qdl.dtsi" |
| |
| / { |
| aliases { |
| i2c3 = &i2c4; |
| }; |
| |
| cpus { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| cpu@0 { |
| compatible = "arm,cortex-a9"; |
| device_type = "cpu"; |
| reg = <0>; |
| next-level-cache = <&L2>; |
| operating-points = < |
| /* kHz uV */ |
| 996000 1250000 |
| 792000 1175000 |
| 396000 1150000 |
| >; |
| fsl,soc-operating-points = < |
| /* ARM kHz SOC-PU uV */ |
| 996000 1175000 |
| 792000 1175000 |
| 396000 1175000 |
| >; |
| clock-latency = <61036>; /* two CLK32 periods */ |
| clocks = <&clks IMX6QDL_CLK_ARM>, |
| <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, |
| <&clks IMX6QDL_CLK_STEP>, |
| <&clks IMX6QDL_CLK_PLL1_SW>, |
| <&clks IMX6QDL_CLK_PLL1_SYS>, |
| <&clks IMX6QDL_CLK_PLL1>, |
| <&clks IMX6QDL_PLL1_BYPASS>, |
| <&clks IMX6QDL_PLL1_BYPASS_SRC>; |
| clock-names = "arm", "pll2_pfd2_396m", "step", |
| "pll1_sw", "pll1_sys", "pll1", |
| "pll1_bypass", "pll1_bypass_src"; |
| arm-supply = <®_arm>; |
| pu-supply = <®_pu>; |
| soc-supply = <®_soc>; |
| }; |
| |
| cpu@1 { |
| compatible = "arm,cortex-a9"; |
| device_type = "cpu"; |
| reg = <1>; |
| next-level-cache = <&L2>; |
| }; |
| }; |
| |
| reserved-memory { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| /* global autoconfigured region for contiguous allocations */ |
| linux,cma { |
| compatible = "shared-dma-pool"; |
| reusable; |
| size = <0x14000000>; |
| linux,cma-default; |
| }; |
| }; |
| |
| soc { |
| busfreq { |
| compatible = "fsl,imx_busfreq"; |
| clocks = <&clks IMX6QDL_CLK_PLL2_BUS>, <&clks IMX6QDL_CLK_PLL2_PFD2_396M>, |
| <&clks IMX6QDL_CLK_PLL2_198M>, <&clks IMX6QDL_CLK_ARM>, |
| <&clks IMX6QDL_CLK_PLL3_USB_OTG>, <&clks IMX6QDL_CLK_PERIPH>, |
| <&clks IMX6QDL_CLK_PERIPH_PRE>, <&clks IMX6QDL_CLK_PERIPH_CLK2>, |
| <&clks IMX6QDL_CLK_PERIPH_CLK2_SEL>, <&clks IMX6QDL_CLK_OSC>, |
| <&clks IMX6QDL_CLK_AXI_ALT_SEL>, <&clks IMX6QDL_CLK_AXI_SEL> , |
| <&clks IMX6QDL_CLK_PLL3_PFD1_540M>; |
| clock-names = "pll2_bus", "pll2_pfd2_396m", "pll2_198m", "arm", "pll3_usb_otg", "periph", |
| "periph_pre", "periph_clk2", "periph_clk2_sel", "osc", "axi_alt_sel", "axi_sel", "pll3_pfd1_540m"; |
| interrupts = <0 107 0x04>, <0 112 0x4>; |
| interrupt-names = "irq_busfreq_0", "irq_busfreq_1"; |
| fsl,max_ddr_freq = <400000000>; |
| }; |
| |
| gpu: gpu@00130000 { |
| compatible = "fsl,imx6dl-gpu", "fsl,imx6q-gpu"; |
| reg = <0x00130000 0x4000>, <0x00134000 0x4000>, |
| <0x10000000 0x0>, <0x0 0x8000000>; |
| reg-names = "iobase_3d", "iobase_2d", |
| "phys_baseaddr", "contiguous_mem"; |
| interrupts = <0 9 IRQ_TYPE_LEVEL_HIGH>, |
| <0 10 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "irq_3d", "irq_2d"; |
| clocks = <&clks IMX6QDL_CLK_OPENVG_AXI>, <&clks IMX6QDL_CLK_GPU3D_AXI>, |
| <&clks IMX6QDL_CLK_GPU2D_CORE>, <&clks IMX6QDL_CLK_GPU3D_CORE>, |
| <&clks IMX6QDL_CLK_DUMMY>; |
| clock-names = "gpu2d_axi_clk", "gpu3d_axi_clk", |
| "gpu2d_clk", "gpu3d_clk", |
| "gpu3d_shader_clk"; |
| resets = <&src 0>, <&src 3>; |
| reset-names = "gpu3d", "gpu2d"; |
| power-domains = <&pd_pu>; |
| }; |
| |
| ocram: sram@00905000 { |
| compatible = "mmio-sram"; |
| reg = <0x00905000 0x1B000>; |
| clocks = <&clks IMX6QDL_CLK_OCRAM>; |
| }; |
| |
| ocram_optee: sram@00918000 { |
| compatible = "fsl,optee-lpm-sram"; |
| reg = <0x00918000 0x8000>; |
| overw_reg = <&ocram 0x00905000 0x13000>; |
| }; |
| |
| aips1: aips-bus@02000000 { |
| iomuxc: iomuxc@020e0000 { |
| compatible = "fsl,imx6dl-iomuxc"; |
| }; |
| |
| dcic2: dcic@020e8000 { |
| clocks = <&clks IMX6QDL_CLK_DCIC1 >, |
| <&clks IMX6QDL_CLK_DCIC2>; /* DCIC2 depend on DCIC1 clock in imx6dl*/ |
| clock-names = "dcic", "disp-axi"; |
| }; |
| |
| pxp: pxp@020f0000 { |
| compatible = "fsl,imx6dl-pxp-dma"; |
| reg = <0x020f0000 0x4000>; |
| interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_DUMMY>; |
| clock-names = "pxp-axi", "disp-axi"; |
| status = "disabled"; |
| }; |
| |
| epdc: epdc@020f4000 { |
| compatible = "fsl,imx6dl-epdc"; |
| reg = <0x020f4000 0x4000>; |
| interrupts = <0 97 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6QDL_CLK_IPU2>, <&clks IMX6QDL_CLK_IPU2_DI1>; |
| clock-names = "epdc_axi", "epdc_pix"; |
| }; |
| |
| lcdif: lcdif@020f8000 { |
| reg = <0x020f8000 0x4000>; |
| interrupts = <0 39 IRQ_TYPE_LEVEL_HIGH>; |
| }; |
| }; |
| |
| aips2: aips-bus@02100000 { |
| mipi_dsi: mipi@021e0000 { |
| compatible = "fsl,imx6dl-mipi-dsi"; |
| reg = <0x021e0000 0x4000>; |
| interrupts = <0 102 0x04>; |
| gpr = <&gpr>; |
| clocks = <&clks IMX6QDL_CLK_HSI_TX>, <&clks IMX6QDL_CLK_VIDEO_27M>; |
| clock-names = "mipi_pllref_clk", "mipi_cfg_clk"; |
| status = "disabled"; |
| }; |
| |
| i2c4: i2c@021f8000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c"; |
| reg = <0x021f8000 0x4000>; |
| interrupts = <0 35 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clks IMX6DL_CLK_I2C4>; |
| status = "disabled"; |
| }; |
| }; |
| }; |
| |
| capture-subsystem { |
| compatible = "fsl,imx-capture-subsystem"; |
| ports = <&ipu1_csi0>, <&ipu1_csi1>; |
| }; |
| |
| display-subsystem { |
| compatible = "fsl,imx-display-subsystem"; |
| ports = <&ipu1_di0>, <&ipu1_di1>; |
| }; |
| |
| gpu-subsystem { |
| compatible = "fsl,imx-gpu-subsystem"; |
| cores = <&gpu_2d>, <&gpu_3d>; |
| }; |
| }; |
| |
| &gpio1 { |
| gpio-ranges = <&iomuxc 0 131 2>, <&iomuxc 2 137 8>, <&iomuxc 10 189 2>, |
| <&iomuxc 12 194 1>, <&iomuxc 13 193 1>, <&iomuxc 14 192 1>, |
| <&iomuxc 15 191 1>, <&iomuxc 16 185 2>, <&iomuxc 18 184 1>, |
| <&iomuxc 19 187 1>, <&iomuxc 20 183 1>, <&iomuxc 21 188 1>, |
| <&iomuxc 22 123 3>, <&iomuxc 25 121 1>, <&iomuxc 26 127 1>, |
| <&iomuxc 27 126 1>, <&iomuxc 28 128 1>, <&iomuxc 29 130 1>, |
| <&iomuxc 30 129 1>, <&iomuxc 31 122 1>; |
| }; |
| |
| &gpio2 { |
| gpio-ranges = <&iomuxc 0 161 8>, <&iomuxc 8 208 8>, <&iomuxc 16 74 1>, |
| <&iomuxc 17 73 1>, <&iomuxc 18 72 1>, <&iomuxc 19 71 1>, |
| <&iomuxc 20 70 1>, <&iomuxc 21 69 1>, <&iomuxc 22 68 1>, |
| <&iomuxc 23 79 2>, <&iomuxc 25 118 2>, <&iomuxc 27 117 1>, |
| <&iomuxc 28 113 4>; |
| }; |
| |
| &gpio3 { |
| gpio-ranges = <&iomuxc 0 97 2>, <&iomuxc 2 105 8>, <&iomuxc 10 99 6>, |
| <&iomuxc 16 81 16>; |
| }; |
| |
| &gpio4 { |
| gpio-ranges = <&iomuxc 5 136 1>, <&iomuxc 6 145 1>, <&iomuxc 7 150 1>, |
| <&iomuxc 8 146 1>, <&iomuxc 9 151 1>, <&iomuxc 10 147 1>, |
| <&iomuxc 11 152 1>, <&iomuxc 12 148 1>, <&iomuxc 13 153 1>, |
| <&iomuxc 14 149 1>, <&iomuxc 15 154 1>, <&iomuxc 16 39 7>, |
| <&iomuxc 23 56 1>, <&iomuxc 24 61 7>, <&iomuxc 31 46 1>; |
| }; |
| |
| &gpio5 { |
| gpio-ranges = <&iomuxc 0 120 1>, <&iomuxc 2 77 1>, <&iomuxc 4 76 1>, |
| <&iomuxc 5 47 9>, <&iomuxc 14 57 4>, <&iomuxc 18 37 1>, |
| <&iomuxc 19 36 1>, <&iomuxc 20 35 1>, <&iomuxc 21 38 1>, |
| <&iomuxc 22 29 6>, <&iomuxc 28 19 4>; |
| }; |
| |
| &gpio6 { |
| gpio-ranges = <&iomuxc 0 23 6>, <&iomuxc 6 75 1>, <&iomuxc 7 156 1>, |
| <&iomuxc 8 155 1>, <&iomuxc 9 170 1>, <&iomuxc 10 169 1>, |
| <&iomuxc 11 157 1>, <&iomuxc 14 158 3>, <&iomuxc 17 204 1>, |
| <&iomuxc 18 203 1>, <&iomuxc 19 182 1>, <&iomuxc 20 177 4>, |
| <&iomuxc 24 175 1>, <&iomuxc 25 171 1>, <&iomuxc 26 181 1>, |
| <&iomuxc 27 172 3>, <&iomuxc 30 176 1>, <&iomuxc 31 78 1>; |
| }; |
| |
| &gpio7 { |
| gpio-ranges = <&iomuxc 0 202 1>, <&iomuxc 1 201 1>, <&iomuxc 2 196 1>, |
| <&iomuxc 3 195 1>, <&iomuxc 4 197 4>, <&iomuxc 8 205 1>, |
| <&iomuxc 9 207 1>, <&iomuxc 10 206 1>, <&iomuxc 11 133 3>; |
| }; |
| |
| &gpr { |
| ipu1_csi0_mux: ipu1_csi0_mux@34 { |
| compatible = "video-mux"; |
| mux-controls = <&mux 0>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| |
| ipu1_csi0_mux_from_mipi_vc0: endpoint { |
| remote-endpoint = <&mipi_vc0_to_ipu1_csi0_mux>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| |
| ipu1_csi0_mux_from_mipi_vc1: endpoint { |
| remote-endpoint = <&mipi_vc1_to_ipu1_csi0_mux>; |
| }; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| |
| ipu1_csi0_mux_from_mipi_vc2: endpoint { |
| remote-endpoint = <&mipi_vc2_to_ipu1_csi0_mux>; |
| }; |
| }; |
| |
| port@3 { |
| reg = <3>; |
| |
| ipu1_csi0_mux_from_mipi_vc3: endpoint { |
| remote-endpoint = <&mipi_vc3_to_ipu1_csi0_mux>; |
| }; |
| }; |
| |
| port@4 { |
| reg = <4>; |
| |
| ipu1_csi0_mux_from_parallel_sensor: endpoint { |
| }; |
| }; |
| |
| port@5 { |
| reg = <5>; |
| |
| ipu1_csi0_mux_to_ipu1_csi0: endpoint { |
| remote-endpoint = <&ipu1_csi0_from_ipu1_csi0_mux>; |
| }; |
| }; |
| }; |
| |
| ipu1_csi1_mux: ipu1_csi1_mux@34 { |
| compatible = "video-mux"; |
| mux-controls = <&mux 1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| port@0 { |
| reg = <0>; |
| |
| ipu1_csi1_mux_from_mipi_vc0: endpoint { |
| remote-endpoint = <&mipi_vc0_to_ipu1_csi1_mux>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| |
| ipu1_csi1_mux_from_mipi_vc1: endpoint { |
| remote-endpoint = <&mipi_vc1_to_ipu1_csi1_mux>; |
| }; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| |
| ipu1_csi1_mux_from_mipi_vc2: endpoint { |
| remote-endpoint = <&mipi_vc2_to_ipu1_csi1_mux>; |
| }; |
| }; |
| |
| port@3 { |
| reg = <3>; |
| |
| ipu1_csi1_mux_from_mipi_vc3: endpoint { |
| remote-endpoint = <&mipi_vc3_to_ipu1_csi1_mux>; |
| }; |
| }; |
| |
| port@4 { |
| reg = <4>; |
| |
| ipu1_csi1_mux_from_parallel_sensor: endpoint { |
| }; |
| }; |
| |
| port@5 { |
| reg = <5>; |
| |
| ipu1_csi1_mux_to_ipu1_csi1: endpoint { |
| remote-endpoint = <&ipu1_csi1_from_ipu1_csi1_mux>; |
| }; |
| }; |
| }; |
| }; |
| |
| &gpt { |
| compatible = "fsl,imx6dl-gpt"; |
| }; |
| |
| &hdmi { |
| compatible = "fsl,imx6dl-hdmi"; |
| }; |
| |
| &ipu1_csi1 { |
| ipu1_csi1_from_ipu1_csi1_mux: endpoint { |
| remote-endpoint = <&ipu1_csi1_mux_to_ipu1_csi1>; |
| }; |
| }; |
| |
| &ldb { |
| compatible = "fsl,imx6dl-ldb", "fsl,imx53-ldb"; |
| clocks = <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>, |
| <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>, |
| <&clks IMX6QDL_CLK_IPU2_DI0_SEL>, |
| <&clks IMX6QDL_CLK_LDB_DI0_DIV_3_5>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_3_5>, |
| <&clks IMX6QDL_CLK_LDB_DI0_DIV_7>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_7>, |
| <&clks IMX6QDL_CLK_LDB_DI0_DIV_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_DIV_SEL>; |
| clock-names = "ldb_di0", "ldb_di1", |
| "di0_sel", "di1_sel", |
| "di2_sel", |
| "ldb_di0_div_3_5", "ldb_di1_div_3_5", |
| "ldb_di0_div_7", "ldb_di1_div_7", |
| "ldb_di0_div_sel", "ldb_di1_div_sel"; |
| }; |
| |
| &mipi_csi { |
| port@1 { |
| reg = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| mipi_vc0_to_ipu1_csi0_mux: endpoint@0 { |
| remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc0>; |
| }; |
| |
| mipi_vc0_to_ipu1_csi1_mux: endpoint@1 { |
| remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc0>; |
| }; |
| }; |
| |
| port@2 { |
| reg = <2>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| mipi_vc1_to_ipu1_csi0_mux: endpoint@0 { |
| remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc1>; |
| }; |
| |
| mipi_vc1_to_ipu1_csi1_mux: endpoint@1 { |
| remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc1>; |
| }; |
| }; |
| |
| port@3 { |
| reg = <3>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| mipi_vc2_to_ipu1_csi0_mux: endpoint@0 { |
| remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc2>; |
| }; |
| |
| mipi_vc2_to_ipu1_csi1_mux: endpoint@1 { |
| remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc2>; |
| }; |
| }; |
| |
| port@4 { |
| reg = <4>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| mipi_vc3_to_ipu1_csi0_mux: endpoint@0 { |
| remote-endpoint = <&ipu1_csi0_mux_from_mipi_vc3>; |
| }; |
| |
| mipi_vc3_to_ipu1_csi1_mux: endpoint@1 { |
| remote-endpoint = <&ipu1_csi1_mux_from_mipi_vc3>; |
| }; |
| }; |
| }; |
| |
| &mux { |
| mux-reg-masks = <0x34 0x00000007>, /* IPU_CSI0_MUX */ |
| <0x34 0x00000038>, /* IPU_CSI1_MUX */ |
| <0x0c 0x0000000c>, /* HDMI_MUX_CTL */ |
| <0x0c 0x000000c0>, /* LVDS0_MUX_CTL */ |
| <0x0c 0x00000300>, /* LVDS1_MUX_CTL */ |
| <0x28 0x00000003>, /* DCIC1_MUX_CTL */ |
| <0x28 0x0000000c>; /* DCIC2_MUX_CTL */ |
| }; |
| |
| &vpu { |
| compatible = "fsl,imx6dl-vpu", "cnm,coda960"; |
| }; |
| |
| &vpu_fsl { |
| iramsize = <0>; |
| }; |
