| /* | |
| * Copyright (c) 2013 Samsung Electronics Co., Ltd. | |
| * http://www.samsung.com/ | |
| * | |
| * EXYNOS4 BUS header | |
| * | |
| * This program is free software; you can redistribute it and/or modify | |
| * it under the terms of the GNU General Public License version 2 as | |
| * published by the Free Software Foundation. | |
| */ | |
| #ifndef __DEVFREQ_EXYNOS4_BUS_H | |
| #define __DEVFREQ_EXYNOS4_BUS_H __FILE__ | |
| #include <mach/map.h> | |
| #define EXYNOS4_CLKDIV_LEFTBUS (S5P_VA_CMU + 0x04500) | |
| #define EXYNOS4_CLKDIV_STAT_LEFTBUS (S5P_VA_CMU + 0x04600) | |
| #define EXYNOS4_CLKDIV_RIGHTBUS (S5P_VA_CMU + 0x08500) | |
| #define EXYNOS4_CLKDIV_STAT_RIGHTBUS (S5P_VA_CMU + 0x08600) | |
| #define EXYNOS4_CLKDIV_TOP (S5P_VA_CMU + 0x0C510) | |
| #define EXYNOS4_CLKDIV_CAM (S5P_VA_CMU + 0x0C520) | |
| #define EXYNOS4_CLKDIV_MFC (S5P_VA_CMU + 0x0C528) | |
| #define EXYNOS4_CLKDIV_STAT_TOP (S5P_VA_CMU + 0x0C610) | |
| #define EXYNOS4_CLKDIV_STAT_MFC (S5P_VA_CMU + 0x0C628) | |
| #define EXYNOS4210_CLKGATE_IP_IMAGE (S5P_VA_CMU + 0x0C930) | |
| #define EXYNOS4212_CLKGATE_IP_IMAGE (S5P_VA_CMU + 0x04930) | |
| #define EXYNOS4_CLKDIV_DMC0 (S5P_VA_CMU + 0x10500) | |
| #define EXYNOS4_CLKDIV_DMC1 (S5P_VA_CMU + 0x10504) | |
| #define EXYNOS4_CLKDIV_STAT_DMC0 (S5P_VA_CMU + 0x10600) | |
| #define EXYNOS4_CLKDIV_STAT_DMC1 (S5P_VA_CMU + 0x10604) | |
| #define EXYNOS4_DMC_PAUSE_CTRL (S5P_VA_CMU + 0x11094) | |
| #define EXYNOS4_DMC_PAUSE_ENABLE (1 << 0) | |
| #define EXYNOS4_CLKDIV_DMC0_ACP_SHIFT (0) | |
| #define EXYNOS4_CLKDIV_DMC0_ACP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACP_SHIFT) | |
| #define EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT (4) | |
| #define EXYNOS4_CLKDIV_DMC0_ACPPCLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_ACPPCLK_SHIFT) | |
| #define EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT (8) | |
| #define EXYNOS4_CLKDIV_DMC0_DPHY_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DPHY_SHIFT) | |
| #define EXYNOS4_CLKDIV_DMC0_DMC_SHIFT (12) | |
| #define EXYNOS4_CLKDIV_DMC0_DMC_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMC_SHIFT) | |
| #define EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT (16) | |
| #define EXYNOS4_CLKDIV_DMC0_DMCD_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCD_SHIFT) | |
| #define EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT (20) | |
| #define EXYNOS4_CLKDIV_DMC0_DMCP_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_DMCP_SHIFT) | |
| #define EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT (24) | |
| #define EXYNOS4_CLKDIV_DMC0_COPY2_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_COPY2_SHIFT) | |
| #define EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT (28) | |
| #define EXYNOS4_CLKDIV_DMC0_CORETI_MASK (0x7 << EXYNOS4_CLKDIV_DMC0_CORETI_SHIFT) | |
| #define EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT (0) | |
| #define EXYNOS4_CLKDIV_DMC1_G2D_ACP_MASK (0xf << EXYNOS4_CLKDIV_DMC1_G2D_ACP_SHIFT) | |
| #define EXYNOS4_CLKDIV_DMC1_C2C_SHIFT (4) | |
| #define EXYNOS4_CLKDIV_DMC1_C2C_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2C_SHIFT) | |
| #define EXYNOS4_CLKDIV_DMC1_PWI_SHIFT (8) | |
| #define EXYNOS4_CLKDIV_DMC1_PWI_MASK (0xf << EXYNOS4_CLKDIV_DMC1_PWI_SHIFT) | |
| #define EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT (12) | |
| #define EXYNOS4_CLKDIV_DMC1_C2CACLK_MASK (0x7 << EXYNOS4_CLKDIV_DMC1_C2CACLK_SHIFT) | |
| #define EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT (16) | |
| #define EXYNOS4_CLKDIV_DMC1_DVSEM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DVSEM_SHIFT) | |
| #define EXYNOS4_CLKDIV_DMC1_DPM_SHIFT (24) | |
| #define EXYNOS4_CLKDIV_DMC1_DPM_MASK (0x7f << EXYNOS4_CLKDIV_DMC1_DPM_SHIFT) | |
| #define EXYNOS4_CLKDIV_MFC_SHIFT (0) | |
| #define EXYNOS4_CLKDIV_MFC_MASK (0x7 << EXYNOS4_CLKDIV_MFC_SHIFT) | |
| #define EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT (0) | |
| #define EXYNOS4_CLKDIV_TOP_ACLK200_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK200_SHIFT) | |
| #define EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT (4) | |
| #define EXYNOS4_CLKDIV_TOP_ACLK100_MASK (0xF << EXYNOS4_CLKDIV_TOP_ACLK100_SHIFT) | |
| #define EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT (8) | |
| #define EXYNOS4_CLKDIV_TOP_ACLK160_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK160_SHIFT) | |
| #define EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT (12) | |
| #define EXYNOS4_CLKDIV_TOP_ACLK133_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK133_SHIFT) | |
| #define EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT (16) | |
| #define EXYNOS4_CLKDIV_TOP_ONENAND_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ONENAND_SHIFT) | |
| #define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT (20) | |
| #define EXYNOS4_CLKDIV_TOP_ACLK266_GPS_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK266_GPS_SHIFT) | |
| #define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT (24) | |
| #define EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_MASK (0x7 << EXYNOS4_CLKDIV_TOP_ACLK400_MCUISP_SHIFT) | |
| #define EXYNOS4_CLKDIV_BUS_GDLR_SHIFT (0) | |
| #define EXYNOS4_CLKDIV_BUS_GDLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GDLR_SHIFT) | |
| #define EXYNOS4_CLKDIV_BUS_GPLR_SHIFT (4) | |
| #define EXYNOS4_CLKDIV_BUS_GPLR_MASK (0x7 << EXYNOS4_CLKDIV_BUS_GPLR_SHIFT) | |
| #define EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT (0) | |
| #define EXYNOS4_CLKDIV_CAM_FIMC0_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC0_SHIFT) | |
| #define EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT (4) | |
| #define EXYNOS4_CLKDIV_CAM_FIMC1_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC1_SHIFT) | |
| #define EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT (8) | |
| #define EXYNOS4_CLKDIV_CAM_FIMC2_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC2_SHIFT) | |
| #define EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT (12) | |
| #define EXYNOS4_CLKDIV_CAM_FIMC3_MASK (0xf << EXYNOS4_CLKDIV_CAM_FIMC3_SHIFT) | |
| #define EXYNOS4_CLKDIV_CAM1 (S5P_VA_CMU + 0x0C568) | |
| #define EXYNOS4_CLKDIV_STAT_CAM1 (S5P_VA_CMU + 0x0C668) | |
| #define EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT (0) | |
| #define EXYNOS4_CLKDIV_CAM1_JPEG_MASK (0xf << EXYNOS4_CLKDIV_CAM1_JPEG_SHIFT) | |
| #endif /* __DEVFREQ_EXYNOS4_BUS_H */ |