| /dts-v1/; |
| |
| #include <dt-bindings/input/input.h> |
| #include "tegra124.dtsi" |
| |
| / { |
| model = "NVIDIA Tegra124 Venice2"; |
| compatible = "nvidia,venice2", "nvidia,tegra124"; |
| |
| aliases { |
| rtc0 = "/i2c@0,7000d000/pmic@40"; |
| rtc1 = "/rtc@0,7000e000"; |
| }; |
| |
| memory { |
| reg = <0x0 0x80000000 0x0 0x80000000>; |
| }; |
| |
| host1x@0,50000000 { |
| hdmi@0,54280000 { |
| status = "okay"; |
| |
| vdd-supply = <&vdd_3v3_hdmi>; |
| pll-supply = <&vdd_hdmi_pll>; |
| hdmi-supply = <&vdd_5v0_hdmi>; |
| |
| nvidia,ddc-i2c-bus = <&hdmi_ddc>; |
| nvidia,hpd-gpio = |
| <&gpio TEGRA_GPIO(N, 7) GPIO_ACTIVE_HIGH>; |
| }; |
| |
| sor@0,54540000 { |
| status = "okay"; |
| |
| nvidia,dpaux = <&dpaux>; |
| nvidia,panel = <&panel>; |
| }; |
| |
| dpaux@0,545c0000 { |
| vdd-supply = <&vdd_3v3_panel>; |
| status = "okay"; |
| }; |
| }; |
| |
| pinmux: pinmux@0,70000868 { |
| pinctrl-names = "boot"; |
| pinctrl-0 = <&pinmux_boot>; |
| |
| pinmux_boot: common { |
| dap_mclk1_pw4 { |
| nvidia,pins = "dap_mclk1_pw4"; |
| nvidia,function = "extperiph1"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| dap1_din_pn1 { |
| nvidia,pins = "dap1_din_pn1"; |
| nvidia,function = "i2s0"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| }; |
| dap1_dout_pn2 { |
| nvidia,pins = "dap1_dout_pn2", |
| "dap1_fs_pn0", |
| "dap1_sclk_pn3"; |
| nvidia,function = "i2s0"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| }; |
| dap2_din_pa4 { |
| nvidia,pins = "dap2_din_pa4"; |
| nvidia,function = "i2s1"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| dap2_dout_pa5 { |
| nvidia,pins = "dap2_dout_pa5", |
| "dap2_fs_pa2", |
| "dap2_sclk_pa3"; |
| nvidia,function = "i2s1"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| dvfs_pwm_px0 { |
| nvidia,pins = "dvfs_pwm_px0", |
| "dvfs_clk_px2"; |
| nvidia,function = "cldvfs"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| ulpi_clk_py0 { |
| nvidia,pins = "ulpi_clk_py0", |
| "ulpi_nxt_py2", |
| "ulpi_stp_py3"; |
| nvidia,function = "spi1"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| ulpi_dir_py1 { |
| nvidia,pins = "ulpi_dir_py1"; |
| nvidia,function = "spi1"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| cam_i2c_scl_pbb1 { |
| nvidia,pins = "cam_i2c_scl_pbb1", |
| "cam_i2c_sda_pbb2"; |
| nvidia,function = "i2c3"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,lock = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| }; |
| gen2_i2c_scl_pt5 { |
| nvidia,pins = "gen2_i2c_scl_pt5", |
| "gen2_i2c_sda_pt6"; |
| nvidia,function = "i2c2"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,lock = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| }; |
| pg4 { |
| nvidia,pins = "pg4", |
| "pg5", |
| "pg6", |
| "pi3"; |
| nvidia,function = "spi4"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| pg7 { |
| nvidia,pins = "pg7"; |
| nvidia,function = "spi4"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| ph1 { |
| nvidia,pins = "ph1"; |
| nvidia,function = "pwm1"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| pk0 { |
| nvidia,pins = "pk0", |
| "kb_row15_ps7", |
| "clk_32k_out_pa0"; |
| nvidia,function = "soc"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| }; |
| sdmmc1_clk_pz0 { |
| nvidia,pins = "sdmmc1_clk_pz0"; |
| nvidia,function = "sdmmc1"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc1_cmd_pz1 { |
| nvidia,pins = "sdmmc1_cmd_pz1", |
| "sdmmc1_dat0_py7", |
| "sdmmc1_dat1_py6", |
| "sdmmc1_dat2_py5", |
| "sdmmc1_dat3_py4"; |
| nvidia,function = "sdmmc1"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc3_clk_pa6 { |
| nvidia,pins = "sdmmc3_clk_pa6"; |
| nvidia,function = "sdmmc3"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc3_cmd_pa7 { |
| nvidia,pins = "sdmmc3_cmd_pa7", |
| "sdmmc3_dat0_pb7", |
| "sdmmc3_dat1_pb6", |
| "sdmmc3_dat2_pb5", |
| "sdmmc3_dat3_pb4", |
| "sdmmc3_clk_lb_out_pee4", |
| "sdmmc3_clk_lb_in_pee5"; |
| nvidia,function = "sdmmc3"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc4_clk_pcc4 { |
| nvidia,pins = "sdmmc4_clk_pcc4"; |
| nvidia,function = "sdmmc4"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| sdmmc4_cmd_pt7 { |
| nvidia,pins = "sdmmc4_cmd_pt7", |
| "sdmmc4_dat0_paa0", |
| "sdmmc4_dat1_paa1", |
| "sdmmc4_dat2_paa2", |
| "sdmmc4_dat3_paa3", |
| "sdmmc4_dat4_paa4", |
| "sdmmc4_dat5_paa5", |
| "sdmmc4_dat6_paa6", |
| "sdmmc4_dat7_paa7"; |
| nvidia,function = "sdmmc4"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| pwr_i2c_scl_pz6 { |
| nvidia,pins = "pwr_i2c_scl_pz6", |
| "pwr_i2c_sda_pz7"; |
| nvidia,function = "i2cpwr"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,lock = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| }; |
| jtag_rtck { |
| nvidia,pins = "jtag_rtck"; |
| nvidia,function = "rtck"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| clk_32k_in { |
| nvidia,pins = "clk_32k_in"; |
| nvidia,function = "clk"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| core_pwr_req { |
| nvidia,pins = "core_pwr_req"; |
| nvidia,function = "pwron"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| cpu_pwr_req { |
| nvidia,pins = "cpu_pwr_req"; |
| nvidia,function = "cpu"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| pwr_int_n { |
| nvidia,pins = "pwr_int_n"; |
| nvidia,function = "pmi"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| reset_out_n { |
| nvidia,pins = "reset_out_n"; |
| nvidia,function = "reset_out_n"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| clk3_out_pee0 { |
| nvidia,pins = "clk3_out_pee0"; |
| nvidia,function = "extperiph3"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| dap4_din_pp5 { |
| nvidia,pins = "dap4_din_pp5"; |
| nvidia,function = "i2s3"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| }; |
| dap4_dout_pp6 { |
| nvidia,pins = "dap4_dout_pp6", |
| "dap4_fs_pp4", |
| "dap4_sclk_pp7"; |
| nvidia,function = "i2s3"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| }; |
| gen1_i2c_sda_pc5 { |
| nvidia,pins = "gen1_i2c_sda_pc5", |
| "gen1_i2c_scl_pc4"; |
| nvidia,function = "i2c1"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,lock = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| }; |
| uart2_cts_n_pj5 { |
| nvidia,pins = "uart2_cts_n_pj5"; |
| nvidia,function = "uartb"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| uart2_rts_n_pj6 { |
| nvidia,pins = "uart2_rts_n_pj6"; |
| nvidia,function = "uartb"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| uart2_rxd_pc3 { |
| nvidia,pins = "uart2_rxd_pc3"; |
| nvidia,function = "irda"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| uart2_txd_pc2 { |
| nvidia,pins = "uart2_txd_pc2"; |
| nvidia,function = "irda"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| uart3_cts_n_pa1 { |
| nvidia,pins = "uart3_cts_n_pa1", |
| "uart3_rxd_pw7"; |
| nvidia,function = "uartc"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| uart3_rts_n_pc0 { |
| nvidia,pins = "uart3_rts_n_pc0", |
| "uart3_txd_pw6"; |
| nvidia,function = "uartc"; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| hdmi_cec_pee3 { |
| nvidia,pins = "hdmi_cec_pee3"; |
| nvidia,function = "cec"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,lock = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_DISABLE>; |
| }; |
| hdmi_int_pn7 { |
| nvidia,pins = "hdmi_int_pn7"; |
| nvidia,function = "rsvd1"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| }; |
| ddc_scl_pv4 { |
| nvidia,pins = "ddc_scl_pv4", |
| "ddc_sda_pv5"; |
| nvidia,function = "i2c4"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,lock = <TEGRA_PIN_DISABLE>; |
| nvidia,rcv-sel = <TEGRA_PIN_ENABLE>; |
| }; |
| pj7 { |
| nvidia,pins = "pj7", |
| "pk7"; |
| nvidia,function = "uartd"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| }; |
| pb0 { |
| nvidia,pins = "pb0", |
| "pb1"; |
| nvidia,function = "uartd"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| }; |
| ph0 { |
| nvidia,pins = "ph0"; |
| nvidia,function = "pwm0"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| }; |
| kb_row10_ps2 { |
| nvidia,pins = "kb_row10_ps2"; |
| nvidia,function = "uarta"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| }; |
| kb_row9_ps1 { |
| nvidia,pins = "kb_row9_ps1"; |
| nvidia,function = "uarta"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| }; |
| kb_row6_pr6 { |
| nvidia,pins = "kb_row6_pr6"; |
| nvidia,function = "displaya_alt"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| }; |
| usb_vbus_en0_pn4 { |
| nvidia,pins = "usb_vbus_en0_pn4", |
| "usb_vbus_en1_pn5"; |
| nvidia,function = "usb"; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,lock = <TEGRA_PIN_DISABLE>; |
| nvidia,open-drain = <TEGRA_PIN_ENABLE>; |
| }; |
| drive_sdio1 { |
| nvidia,pins = "drive_sdio1"; |
| nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
| nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| nvidia,pull-down-strength = <32>; |
| nvidia,pull-up-strength = <42>; |
| nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| }; |
| drive_sdio3 { |
| nvidia,pins = "drive_sdio3"; |
| nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
| nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| nvidia,pull-down-strength = <20>; |
| nvidia,pull-up-strength = <36>; |
| nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| }; |
| drive_gma { |
| nvidia,pins = "drive_gma"; |
| nvidia,high-speed-mode = <TEGRA_PIN_ENABLE>; |
| nvidia,schmitt = <TEGRA_PIN_DISABLE>; |
| nvidia,low-power-mode = <TEGRA_PIN_LP_DRIVE_DIV_1>; |
| nvidia,pull-down-strength = <1>; |
| nvidia,pull-up-strength = <2>; |
| nvidia,slew-rate-rising = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| nvidia,slew-rate-falling = <TEGRA_PIN_SLEW_RATE_FASTEST>; |
| nvidia,drive-type = <1>; |
| }; |
| als_irq_l { |
| nvidia,pins = "gpio_x3_aud_px3"; |
| nvidia,function = "gmi"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| }; |
| codec_irq_l { |
| nvidia,pins = "ph4"; |
| nvidia,function = "gmi"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| }; |
| lcd_bl_en { |
| nvidia,pins = "ph2"; |
| nvidia,function = "gmi"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| }; |
| touch_irq_l { |
| nvidia,pins = "gpio_w3_aud_pw3"; |
| nvidia,function = "spi6"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| }; |
| tpm_davint_l { |
| nvidia,pins = "ph6"; |
| nvidia,function = "gmi"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| }; |
| ts_irq_l { |
| nvidia,pins = "pk2"; |
| nvidia,function = "gmi"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| }; |
| ts_reset_l { |
| nvidia,pins = "pk4"; |
| nvidia,function = "gmi"; |
| nvidia,pull = <TEGRA_PIN_PULL_DOWN>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| }; |
| ts_shdn_l { |
| nvidia,pins = "pk1"; |
| nvidia,function = "gmi"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| }; |
| ph7 { |
| nvidia,pins = "ph7"; |
| nvidia,function = "gmi"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| }; |
| kb_col0_ap { |
| nvidia,pins = "kb_col0_pq0"; |
| nvidia,function = "rsvd4"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| }; |
| lid_open { |
| nvidia,pins = "kb_row4_pr4"; |
| nvidia,function = "rsvd3"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| }; |
| en_vdd_sd { |
| nvidia,pins = "kb_row0_pr0"; |
| nvidia,function = "rsvd4"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| }; |
| ac_ok { |
| nvidia,pins = "pj0"; |
| nvidia,function = "gmi"; |
| nvidia,pull = <TEGRA_PIN_PULL_UP>; |
| nvidia,tristate = <TEGRA_PIN_ENABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| }; |
| sensor_irq_l { |
| nvidia,pins = "pi6"; |
| nvidia,function = "gmi"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| }; |
| wifi_en { |
| nvidia,pins = "gpio_x7_aud_px7"; |
| nvidia,function = "rsvd4"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_DISABLE>; |
| }; |
| wifi_rst_l { |
| nvidia,pins = "clk2_req_pcc5"; |
| nvidia,function = "dap"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| }; |
| hp_det_l { |
| nvidia,pins = "ulpi_data1_po2"; |
| nvidia,function = "spi3"; |
| nvidia,pull = <TEGRA_PIN_PULL_NONE>; |
| nvidia,tristate = <TEGRA_PIN_DISABLE>; |
| nvidia,enable-input = <TEGRA_PIN_ENABLE>; |
| }; |
| }; |
| }; |
| |
| serial@0,70006000 { |
| status = "okay"; |
| }; |
| |
| pwm@0,7000a000 { |
| status = "okay"; |
| }; |
| |
| i2c@0,7000c000 { |
| status = "okay"; |
| clock-frequency = <100000>; |
| |
| acodec: audio-codec@10 { |
| compatible = "maxim,max98090"; |
| reg = <0x10>; |
| interrupt-parent = <&gpio>; |
| interrupts = <TEGRA_GPIO(H, 4) GPIO_ACTIVE_HIGH>; |
| }; |
| }; |
| |
| i2c@0,7000c400 { |
| status = "okay"; |
| clock-frequency = <100000>; |
| |
| trackpad@4b { |
| compatible = "atmel,maxtouch"; |
| reg = <0x4b>; |
| interrupt-parent = <&gpio>; |
| interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_LOW>; |
| linux,gpio-keymap = <0 0 0 BTN_LEFT>; |
| }; |
| }; |
| |
| i2c@0,7000c500 { |
| status = "okay"; |
| clock-frequency = <100000>; |
| }; |
| |
| hdmi_ddc: i2c@0,7000c700 { |
| status = "okay"; |
| clock-frequency = <100000>; |
| }; |
| |
| i2c@0,7000d000 { |
| status = "okay"; |
| clock-frequency = <400000>; |
| |
| pmic: pmic@40 { |
| compatible = "ams,as3722"; |
| reg = <0x40>; |
| interrupts = <0 86 IRQ_TYPE_LEVEL_HIGH>; |
| |
| ams,system-power-controller; |
| |
| #interrupt-cells = <2>; |
| interrupt-controller; |
| |
| gpio-controller; |
| #gpio-cells = <2>; |
| |
| pinctrl-names = "default"; |
| pinctrl-0 = <&as3722_default>; |
| |
| as3722_default: pinmux { |
| gpio0 { |
| pins = "gpio0"; |
| function = "gpio"; |
| bias-pull-down; |
| }; |
| |
| gpio1_2_4_7 { |
| pins = "gpio1", "gpio2", "gpio4", "gpio7"; |
| function = "gpio"; |
| bias-pull-up; |
| }; |
| |
| gpio3_6 { |
| pins = "gpio3", "gpio6"; |
| bias-high-impedance; |
| }; |
| |
| gpio5 { |
| pins = "gpio5"; |
| function = "clk32k-out"; |
| }; |
| }; |
| |
| regulators { |
| vsup-sd2-supply = <&vdd_5v0_sys>; |
| vsup-sd3-supply = <&vdd_5v0_sys>; |
| vsup-sd4-supply = <&vdd_5v0_sys>; |
| vsup-sd5-supply = <&vdd_5v0_sys>; |
| vin-ldo0-supply = <&vdd_1v35_lp0>; |
| vin-ldo1-6-supply = <&vdd_3v3_run>; |
| vin-ldo2-5-7-supply = <&vddio_1v8>; |
| vin-ldo3-4-supply = <&vdd_3v3_sys>; |
| vin-ldo9-10-supply = <&vdd_5v0_sys>; |
| vin-ldo11-supply = <&vdd_3v3_run>; |
| |
| sd0 { |
| regulator-name = "+VDD_CPU_AP"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1400000>; |
| regulator-min-microamp = <3500000>; |
| regulator-max-microamp = <3500000>; |
| regulator-always-on; |
| regulator-boot-on; |
| ams,ext-control = <2>; |
| }; |
| |
| sd1 { |
| regulator-name = "+VDD_CORE"; |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1350000>; |
| regulator-min-microamp = <2500000>; |
| regulator-max-microamp = <2500000>; |
| regulator-always-on; |
| regulator-boot-on; |
| ams,ext-control = <1>; |
| }; |
| |
| vdd_1v35_lp0: sd2 { |
| regulator-name = "+1.35V_LP0(sd2)"; |
| regulator-min-microvolt = <1350000>; |
| regulator-max-microvolt = <1350000>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| sd3 { |
| regulator-name = "+1.35V_LP0(sd3)"; |
| regulator-min-microvolt = <1350000>; |
| regulator-max-microvolt = <1350000>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| vdd_1v05_run: sd4 { |
| regulator-name = "+1.05V_RUN"; |
| regulator-min-microvolt = <1050000>; |
| regulator-max-microvolt = <1050000>; |
| }; |
| |
| vddio_1v8: sd5 { |
| regulator-name = "+1.8V_VDDIO"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| sd6 { |
| regulator-name = "+VDD_GPU_AP"; |
| regulator-min-microvolt = <650000>; |
| regulator-max-microvolt = <1200000>; |
| regulator-min-microamp = <3500000>; |
| regulator-max-microamp = <3500000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo0 { |
| regulator-name = "+1.05V_RUN_AVDD"; |
| regulator-min-microvolt = <1050000>; |
| regulator-max-microvolt = <1050000>; |
| regulator-boot-on; |
| regulator-always-on; |
| ams,ext-control = <1>; |
| }; |
| |
| ldo1 { |
| regulator-name = "+1.8V_RUN_CAM"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| }; |
| |
| ldo2 { |
| regulator-name = "+1.2V_GEN_AVDD"; |
| regulator-min-microvolt = <1200000>; |
| regulator-max-microvolt = <1200000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| ldo3 { |
| regulator-name = "+1.00V_LP0_VDD_RTC"; |
| regulator-min-microvolt = <1000000>; |
| regulator-max-microvolt = <1000000>; |
| regulator-boot-on; |
| regulator-always-on; |
| ams,enable-tracking; |
| }; |
| |
| vdd_run_cam: ldo4 { |
| regulator-name = "+3.3V_RUN_CAM"; |
| regulator-min-microvolt = <2800000>; |
| regulator-max-microvolt = <2800000>; |
| }; |
| |
| ldo5 { |
| regulator-name = "+1.2V_RUN_CAM_FRONT"; |
| regulator-min-microvolt = <1200000>; |
| regulator-max-microvolt = <1200000>; |
| }; |
| |
| vddio_sdmmc3: ldo6 { |
| regulator-name = "+VDDIO_SDMMC3"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| |
| ldo7 { |
| regulator-name = "+1.05V_RUN_CAM_REAR"; |
| regulator-min-microvolt = <1050000>; |
| regulator-max-microvolt = <1050000>; |
| }; |
| |
| ldo9 { |
| regulator-name = "+2.8V_RUN_TOUCH"; |
| regulator-min-microvolt = <2800000>; |
| regulator-max-microvolt = <2800000>; |
| }; |
| |
| ldo10 { |
| regulator-name = "+2.8V_RUN_CAM_AF"; |
| regulator-min-microvolt = <2800000>; |
| regulator-max-microvolt = <2800000>; |
| }; |
| |
| ldo11 { |
| regulator-name = "+1.8V_RUN_VPP_FUSE"; |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <1800000>; |
| }; |
| }; |
| }; |
| }; |
| |
| spi@0,7000d400 { |
| status = "okay"; |
| |
| cros_ec: cros-ec@0 { |
| compatible = "google,cros-ec-spi"; |
| spi-max-frequency = <4000000>; |
| interrupt-parent = <&gpio>; |
| interrupts = <TEGRA_GPIO(C, 7) IRQ_TYPE_LEVEL_LOW>; |
| reg = <0>; |
| |
| google,cros-ec-spi-msg-delay = <2000>; |
| |
| i2c-tunnel { |
| compatible = "google,cros-ec-i2c-tunnel"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| google,remote-bus = <0>; |
| |
| charger: bq24735@9 { |
| compatible = "ti,bq24735"; |
| reg = <0x9>; |
| interrupt-parent = <&gpio>; |
| interrupts = <TEGRA_GPIO(J, 0) |
| GPIO_ACTIVE_HIGH>; |
| ti,ac-detect-gpios = <&gpio |
| TEGRA_GPIO(J, 0) |
| GPIO_ACTIVE_HIGH>; |
| }; |
| |
| battery: sbs-battery@b { |
| compatible = "sbs,sbs-battery"; |
| reg = <0xb>; |
| sbs,i2c-retry-count = <2>; |
| sbs,poll-retry-count = <1>; |
| }; |
| }; |
| }; |
| }; |
| |
| spi@0,7000da00 { |
| status = "okay"; |
| spi-max-frequency = <25000000>; |
| spi-flash@0 { |
| compatible = "winbond,w25q32dw"; |
| reg = <0>; |
| spi-max-frequency = <20000000>; |
| }; |
| }; |
| |
| pmc@0,7000e400 { |
| nvidia,invert-interrupt; |
| nvidia,suspend-mode = <1>; |
| nvidia,cpu-pwr-good-time = <500>; |
| nvidia,cpu-pwr-off-time = <300>; |
| nvidia,core-pwr-good-time = <641 3845>; |
| nvidia,core-pwr-off-time = <61036>; |
| nvidia,core-power-req-active-high; |
| nvidia,sys-clock-req-active-high; |
| }; |
| |
| hda@0,70030000 { |
| status = "okay"; |
| }; |
| |
| sdhci@0,700b0400 { |
| cd-gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_HIGH>; |
| power-gpios = <&gpio TEGRA_GPIO(R, 0) GPIO_ACTIVE_HIGH>; |
| wp-gpios = <&gpio TEGRA_GPIO(Q, 4) GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| bus-width = <4>; |
| vqmmc-supply = <&vddio_sdmmc3>; |
| }; |
| |
| sdhci@0,700b0600 { |
| status = "okay"; |
| bus-width = <8>; |
| }; |
| |
| ahub@0,70300000 { |
| i2s@0,70301100 { |
| status = "okay"; |
| }; |
| }; |
| |
| usb@0,7d000000 { |
| status = "okay"; |
| }; |
| |
| usb-phy@0,7d000000 { |
| status = "okay"; |
| vbus-supply = <&vdd_usb1_vbus>; |
| }; |
| |
| usb@0,7d004000 { |
| status = "okay"; |
| }; |
| |
| usb-phy@0,7d004000 { |
| status = "okay"; |
| vbus-supply = <&vdd_run_cam>; |
| }; |
| |
| usb@0,7d008000 { |
| status = "okay"; |
| }; |
| |
| usb-phy@0,7d008000 { |
| status = "okay"; |
| vbus-supply = <&vdd_usb3_vbus>; |
| }; |
| |
| backlight: backlight { |
| compatible = "pwm-backlight"; |
| |
| enable-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_HIGH>; |
| power-supply = <&vdd_led>; |
| pwms = <&pwm 1 1000000>; |
| |
| brightness-levels = <0 4 8 16 32 64 128 255>; |
| default-brightness-level = <6>; |
| }; |
| |
| clocks { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| clk32k_in: clock@0 { |
| compatible = "fixed-clock"; |
| reg = <0>; |
| #clock-cells = <0>; |
| clock-frequency = <32768>; |
| }; |
| }; |
| |
| gpio-keys { |
| compatible = "gpio-keys"; |
| |
| power { |
| label = "Power"; |
| gpios = <&gpio TEGRA_GPIO(Q, 0) GPIO_ACTIVE_LOW>; |
| linux,code = <KEY_POWER>; |
| debounce-interval = <10>; |
| gpio-key,wakeup; |
| }; |
| }; |
| |
| panel: panel { |
| compatible = "lg,lp129qe", "simple-panel"; |
| |
| backlight = <&backlight>; |
| ddc-i2c-bus = <&dpaux>; |
| }; |
| |
| regulators { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| vdd_mux: regulator@0 { |
| compatible = "regulator-fixed"; |
| reg = <0>; |
| regulator-name = "+VDD_MUX"; |
| regulator-min-microvolt = <12000000>; |
| regulator-max-microvolt = <12000000>; |
| regulator-always-on; |
| regulator-boot-on; |
| }; |
| |
| vdd_5v0_sys: regulator@1 { |
| compatible = "regulator-fixed"; |
| reg = <1>; |
| regulator-name = "+5V_SYS"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| regulator-always-on; |
| regulator-boot-on; |
| vin-supply = <&vdd_mux>; |
| }; |
| |
| vdd_3v3_sys: regulator@2 { |
| compatible = "regulator-fixed"; |
| reg = <2>; |
| regulator-name = "+3.3V_SYS"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| regulator-boot-on; |
| vin-supply = <&vdd_mux>; |
| }; |
| |
| vdd_3v3_run: regulator@3 { |
| compatible = "regulator-fixed"; |
| reg = <3>; |
| regulator-name = "+3.3V_RUN"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| regulator-boot-on; |
| gpio = <&pmic 1 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| vin-supply = <&vdd_3v3_sys>; |
| }; |
| |
| vdd_3v3_hdmi: regulator@4 { |
| compatible = "regulator-fixed"; |
| reg = <4>; |
| regulator-name = "+3.3V_AVDD_HDMI_AP_GATED"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| vin-supply = <&vdd_3v3_run>; |
| }; |
| |
| vdd_led: regulator@5 { |
| compatible = "regulator-fixed"; |
| reg = <5>; |
| regulator-name = "+VDD_LED"; |
| gpio = <&gpio TEGRA_GPIO(P, 2) GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| vin-supply = <&vdd_mux>; |
| }; |
| |
| vdd_5v0_ts: regulator@6 { |
| compatible = "regulator-fixed"; |
| reg = <6>; |
| regulator-name = "+5V_VDD_TS_SW"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| regulator-boot-on; |
| gpio = <&gpio TEGRA_GPIO(K, 1) GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| vin-supply = <&vdd_5v0_sys>; |
| }; |
| |
| vdd_usb1_vbus: regulator@7 { |
| compatible = "regulator-fixed"; |
| reg = <7>; |
| regulator-name = "+5V_USB_HS"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| gpio = <&gpio TEGRA_GPIO(N, 4) GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| gpio-open-drain; |
| vin-supply = <&vdd_5v0_sys>; |
| }; |
| |
| vdd_usb3_vbus: regulator@8 { |
| compatible = "regulator-fixed"; |
| reg = <8>; |
| regulator-name = "+5V_USB_SS"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| gpio = <&gpio TEGRA_GPIO(N, 5) GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| gpio-open-drain; |
| vin-supply = <&vdd_5v0_sys>; |
| }; |
| |
| vdd_3v3_panel: regulator@9 { |
| compatible = "regulator-fixed"; |
| reg = <9>; |
| regulator-name = "+3.3V_PANEL"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&pmic 4 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| vin-supply = <&vdd_3v3_run>; |
| }; |
| |
| vdd_3v3_lp0: regulator@10 { |
| compatible = "regulator-fixed"; |
| reg = <10>; |
| regulator-name = "+3.3V_LP0"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| /* |
| * TODO: find a way to wire this up with the USB EHCI |
| * controllers so that it can be enabled on demand. |
| */ |
| regulator-always-on; |
| gpio = <&pmic 2 GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| vin-supply = <&vdd_3v3_sys>; |
| }; |
| |
| vdd_hdmi_pll: regulator@11 { |
| compatible = "regulator-fixed"; |
| reg = <11>; |
| regulator-name = "+1.05V_RUN_AVDD_HDMI_PLL"; |
| regulator-min-microvolt = <1050000>; |
| regulator-max-microvolt = <1050000>; |
| gpio = <&gpio TEGRA_GPIO(H, 7) GPIO_ACTIVE_LOW>; |
| vin-supply = <&vdd_1v05_run>; |
| }; |
| |
| vdd_5v0_hdmi: regulator@12 { |
| compatible = "regulator-fixed"; |
| reg = <12>; |
| regulator-name = "+5V_HDMI_CON"; |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5000000>; |
| gpio = <&gpio TEGRA_GPIO(K, 6) GPIO_ACTIVE_HIGH>; |
| enable-active-high; |
| vin-supply = <&vdd_5v0_sys>; |
| }; |
| }; |
| |
| sound { |
| compatible = "nvidia,tegra-audio-max98090-venice2", |
| "nvidia,tegra-audio-max98090"; |
| nvidia,model = "NVIDIA Tegra Venice2"; |
| |
| nvidia,audio-routing = |
| "Headphones", "HPR", |
| "Headphones", "HPL", |
| "Speakers", "SPKR", |
| "Speakers", "SPKL", |
| "Mic Jack", "MICBIAS", |
| "IN34", "Mic Jack"; |
| |
| nvidia,i2s-controller = <&tegra_i2s1>; |
| nvidia,audio-codec = <&acodec>; |
| |
| clocks = <&tegra_car TEGRA124_CLK_PLL_A>, |
| <&tegra_car TEGRA124_CLK_PLL_A_OUT0>, |
| <&tegra_car TEGRA124_CLK_EXTERN1>; |
| clock-names = "pll_a", "pll_a_out0", "mclk"; |
| }; |
| }; |
| |
| #include "cros-ec-keyboard.dtsi" |
