arch/arm64/boot/dts/freescale/fsl-imx8qxp-lpddr4-arm2-dsp.dts

// SPDX-License-Identifier: (GPL-2.0+
// Copyright 2017 NXP

#include "fsl-imx8qxp-lpddr4-arm2.dts"

/ {
	sound-cs42888 {
		status = "disabled";
	};

	dspaudio: dspaudio {
		compatible = "fsl,dsp-audio";
		pinctrl-names = "default";
		pinctrl-0 = <&pinctrl_esai0>;
		clocks = <&clk IMX8QXP_AUD_ESAI_0_IPG>,
			<&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>,
			<&clk IMX8QXP_AUD_ASRC_0_IPG>,
			<&clk IMX8QXP_CLK_DUMMY>,
			<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>,
			<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK1_CLK>,
			<&clk IMX8QXP_ACM_AUD_CLK0_SEL>,
			<&clk IMX8QXP_ACM_AUD_CLK1_SEL>;
		clock-names = "bus", "mclk", "ipg", "mem",
				"asrck_0", "asrck_1", "asrck_2", "asrck_3";
		assigned-clocks = <&clk IMX8QXP_ACM_ESAI0_MCLK_SEL>,
			<&clk IMX8QXP_AUD_PLL0_DIV>,
			<&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_DIV>,
			<&clk IMX8QXP_AUD_ACM_AUD_REC_CLK0_DIV>,
			<&clk IMX8QXP_AUD_ESAI_0_EXTAL_IPG>;
		assigned-clock-parents = <&clk IMX8QXP_AUD_ACM_AUD_PLL_CLK0_CLK>;
		assigned-clock-rates = <0>, <786432000>, <49152000>, <24576000>, <49152000>;
		power-domains = <&pd_esai0>;
		status = "okay";
	};

	sound-dsp {
		compatible = "fsl,imx-dsp-audio";
		model = "dsp-audio";
		cpu-dai = <&dspaudio>;
		audio-codec = <&codec>;
		audio-platform = <&dsp>;
	};
};

&edma0 {
	compatible = "fsl,imx8qm-edma";
	reg = <0x0 0x59280000 0x0 0x10000>, /* spdif0 rx */
		<0x0 0x59290000 0x0 0x10000>, /* spdif0 tx */
		<0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */
		<0x0 0x592d0000 0x0 0x10000>, /* sai0 tx */
		<0x0 0x592e0000 0x0 0x10000>, /* sai1 rx */
		<0x0 0x592f0000 0x0 0x10000>, /* sai1 tx */
		<0x0 0x59350000 0x0 0x10000>,
		<0x0 0x59370000 0x0 0x10000>;
	#dma-cells = <3>;
	shared-interrupt;
	dma-channels = <8>;
	interrupts = <GIC_SPI 457 IRQ_TYPE_LEVEL_HIGH>, /* spdif0 */
			<GIC_SPI 459 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */
			<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, /* sai1 */
			<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 391 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 393 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "edma0-chan8-rx", "edma0-chan9-tx", /* spdif0 */
			"edma0-chan12-rx", "edma0-chan13-tx", /* sai0 */
			"edma0-chan14-rx", "edma0-chan15-tx", /* sai1 */
			"edma0-chan21-tx",		/* gpt5 */
			"edma0-chan23-rx";		/* gpt7 */
	status = "okay";
};

/delete-node/ &pd_dma0_chan6;

&pd_asrc0 {
	reg = <SC_R_ASRC_0>;
	power-domains =<&pd_dma0_chan5>;
	#power-domain-cells = <0>;
	#address-cells = <1>;
	#size-cells = <0>;

	pd_dma0_chan6: PD_ESAI_0_RX {
		reg = <SC_R_DMA_0_CH6>;
		power-domains =<&pd_asrc0>;
		#power-domain-cells = <0>;
		#address-cells = <1>;
		#size-cells = <0>;

		pd_dma0_chan7: PD_ESAI_0_TX {
			reg = <SC_R_DMA_0_CH7>;
			power-domains =<&pd_dma0_chan6>;
			#power-domain-cells = <0>;
			#address-cells = <1>;
			#size-cells = <0>;

			pd_esai0: PD_AUD_ESAI_0 {
				reg = <SC_R_ESAI_0>;
				#power-domain-cells = <0>;
				power-domains =<&pd_dma0_chan7>;
			};
		};
	};
};

&esai0 {
	status = "disabled";
};

&asrc0 {
	status = "disabled";
};