commit 6418b0672064d0044b32226b60abeeb0ce45f26a
author Leonid Lobachev <leonidl@google.com> Tue Apr 30 13:23:31 2019 -0700
committer Alex Van Damme <atv@google.com> Tue May 14 10:34:41 2019 -0700
tree fdcd5d938e628799ab474d6f7a7d0039459e1dfb
parent 7df92b88d20d780be6f23b4f5458a1faab31d48c

Enable UART3 which is connected to 40pin header.

Enable UART3 and properly configure pinmux settings
for TX/RX pins.

Bug: 131176938, 131178416

Change-Id: I0bf5da18298d26ea5d7215d3cd581a9cc7d047a7
Signed-off-by: Leonid Lobachev <leonidl@google.com>

arch/arm64/boot/dts/freescale/fsl-imx8mq-som.dtsi

diff --git a/arch/arm64/boot/dts/freescale/fsl-imx8mq-som.dtsi b/arch/arm64/boot/dts/freescale/fsl-imx8mq-som.dtsi
index 6fefcb7..559fb512 100644
--- a/arch/arm64/boot/dts/freescale/fsl-imx8mq-som.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-imx8mq-som.dtsi
@@ -165,6 +165,13 @@
 			>;
 		};
 
+		pinctrl_uart3: uart3grp {
+			fsl,pins = <
+				MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX		0x49
+				MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX		0x49
+			>;
+		};
+
 		pinctrl_usdhc1: usdhc1grp {
 			fsl,pins = <
 				MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK			0x83
@@ -533,6 +540,14 @@
 	status = "okay";
 };
 
+&uart3 {
+	pinctrl-names = "default";
+	pinctrl-0 = <&pinctrl_uart3>;
+	assigned-clocks = <&clk IMX8MQ_CLK_UART3_SRC>;
+	assigned-clock-parents = <&clk IMX8MQ_CLK_25M>;
+	status = "okay";
+};
+
 &usdhc1 {
 	pinctrl-names = "default", "state_100mhz", "state_200mhz";
 	pinctrl-0 = <&pinctrl_usdhc1>;