| /* |
| * Copyright (C) 2016 Freescale Semiconductor, Inc. |
| * Copyright 2017 NXP |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License |
| * as published by the Free Software Foundation; either version 2 |
| * of the License, or (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| /dts-v1/; |
| |
| #include "fsl-imx8mq.dtsi" |
| |
| / { |
| model = "Freescale i.MX8MQ EVK"; |
| compatible = "fsl,imx8mq-evk", "fsl,imx8mq"; |
| |
| chosen { |
| bootargs = "console=ttymxc0,115200 earlycon=ec_imx6q,0x30860000,115200"; |
| stdout-path = &uart1; |
| }; |
| |
| regulators { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| reg_usdhc2_vmmc: usdhc2_vmmc { |
| compatible = "regulator-fixed"; |
| regulator-name = "VSD_3V3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; |
| off-on-delay = <20000>; |
| enable-active-high; |
| }; |
| |
| reg_gpio_dvfs: regulator-gpio { |
| compatible = "regulator-gpio"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_dvfs>; |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1000000>; |
| regulator-name = "gpio_dvfs"; |
| regulator-type = "voltage"; |
| gpios = <&gpio1 13 GPIO_ACTIVE_HIGH>; |
| states = <900000 0x1 1000000 0x0>; |
| }; |
| }; |
| |
| ir_recv: ir-receiver { |
| compatible = "gpio-ir-receiver"; |
| gpios = <&gpio1 12 GPIO_ACTIVE_LOW>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_ir_recv>; |
| }; |
| |
| brcmfmac: brcmfmac { |
| compatible = "cypress,brcmfmac"; |
| pinctrl-names = "init", "idle", "default"; |
| pinctrl-0 = <&pinctrl_wlan_init>; |
| pinctrl-1 = <&pinctrl_wlan_init>; |
| pinctrl-2 = <&pinctrl_wlan>; |
| }; |
| |
| modem_reset: modem-reset { |
| compatible = "gpio-reset"; |
| reset-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>; |
| reset-delay-us = <2000>; |
| reset-post-delay-ms = <40>; |
| #reset-cells = <0>; |
| }; |
| |
| wm8524: wm8524 { |
| compatible = "wlf,wm8524"; |
| clocks = <&clk IMX8MQ_CLK_SAI2_ROOT>; |
| clock-names = "mclk"; |
| wlf,mute-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; |
| }; |
| |
| sound-wm8524 { |
| compatible = "fsl,imx-audio-wm8524"; |
| model = "wm8524-audio"; |
| audio-cpu = <&sai2>; |
| audio-codec = <&wm8524>; |
| audio-routing = |
| "Line Out Jack", "LINEVOUTL", |
| "Line Out Jack", "LINEVOUTR"; |
| }; |
| |
| sound-hdmi { |
| compatible = "fsl,imx8mq-evk-cdnhdmi", |
| "fsl,imx-audio-cdnhdmi"; |
| model = "imx-audio-hdmi"; |
| audio-cpu = <&sai4>; |
| protocol = <1>; |
| hdmi-out; |
| constraint-rate = <44100>, |
| <88200>, |
| <176400>, |
| <32000>, |
| <48000>, |
| <96000>, |
| <192000>; |
| }; |
| |
| sound-spdif { |
| compatible = "fsl,imx-audio-spdif"; |
| model = "imx-spdif"; |
| spdif-controller = <&spdif1>; |
| spdif-out; |
| spdif-in; |
| }; |
| |
| sound-hdmi-arc { |
| compatible = "fsl,imx-audio-spdif"; |
| model = "imx-hdmi-arc"; |
| spdif-controller = <&spdif2>; |
| spdif-in; |
| }; |
| |
| sound-ak4458 { |
| compatible = "fsl,imx-audio-ak4458-mq"; |
| model = "ak4458-audio"; |
| audio-cpu = <&sai1>; |
| audio-codec = <&ak4458_1>, <&ak4458_2>; |
| ak4458,pdn-gpio = <&gpio3 18 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| sound-ak5558 { |
| compatible = "fsl,imx-audio-ak5558-mq"; |
| model = "ak5558-audio"; |
| audio-cpu = <&sai5>; |
| audio-codec = <&ak5558>; |
| }; |
| |
| sound-ak4497 { |
| compatible = "fsl,imx-audio-ak4497-mq"; |
| model = "ak4497-audio"; |
| audio-cpu = <&sai1>; |
| audio-codec = <&ak4497>; |
| status = "disabled"; |
| }; |
| }; |
| |
| &clk { |
| assigned-clocks = <&clk IMX8MQ_AUDIO_PLL1>, <&clk IMX8MQ_AUDIO_PLL2>; |
| assigned-clock-rates = <786432000>, <722534400>; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog>; |
| |
| imx8mq-evk { |
| pinctrl_hog: hoggrp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_NAND_READY_B_GPIO3_IO16 0x19 |
| MX8MQ_IOMUXC_NAND_WE_B_GPIO3_IO17 0x19 |
| MX8MQ_IOMUXC_NAND_WP_B_GPIO3_IO18 0x19 |
| >; |
| }; |
| |
| pinctrl_ir_recv: ir_recv { |
| fsl,pins = < |
| MX8MQ_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x4f |
| >; |
| }; |
| |
| pinctrl_csi1_pwn: csi1_pwn_grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_GPIO1_IO03_GPIO1_IO3 0x19 |
| >; |
| }; |
| pinctrl_csi2_pwn: csi2_pwn_grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x19 |
| >; |
| }; |
| |
| pinctrl_csi_rst: csi_rst_grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x19 |
| MX8MQ_IOMUXC_GPIO1_IO15_CCMSRCGPCMIX_CLKO2 0x59 |
| >; |
| }; |
| |
| pinctrl_fec1: fec1grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 |
| MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 |
| MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f |
| MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f |
| MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f |
| MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f |
| MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 |
| MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 |
| MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 |
| MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 |
| MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f |
| MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 |
| MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 |
| MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f |
| MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f |
| MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_I2C2_SCL_I2C2_SCL 0x40000067 |
| MX8MQ_IOMUXC_I2C2_SDA_I2C2_SDA 0x40000067 |
| >; |
| }; |
| |
| pinctrl_i2c3: i2c3grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x40000067 |
| MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x40000067 |
| >; |
| }; |
| |
| pinctrl_pcie0: pcie0grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_I2C4_SCL_PCIE1_CLKREQ_B 0x76 /* open drain, pull up */ |
| MX8MQ_IOMUXC_UART4_TXD_GPIO5_IO29 0x16 |
| MX8MQ_IOMUXC_UART4_RXD_GPIO5_IO28 0x16 |
| >; |
| }; |
| |
| pinctrl_pcie1: pcie1grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_I2C4_SDA_PCIE2_CLKREQ_B 0x76 /* open drain, pull up */ |
| MX8MQ_IOMUXC_ECSPI2_SCLK_GPIO5_IO10 0x16 |
| MX8MQ_IOMUXC_ECSPI2_MISO_GPIO5_IO12 0x16 |
| >; |
| }; |
| |
| pinctrl_dvfs: dvfsgrp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_GPIO1_IO13_GPIO1_IO13 0x16 |
| >; |
| }; |
| |
| pinctrl_typec: typecgrp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_NAND_RE_B_GPIO3_IO15 0x16 |
| MX8MQ_IOMUXC_NAND_CE2_B_GPIO3_IO3 0x17059 |
| >; |
| }; |
| |
| pinctrl_qspi: qspigrp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_NAND_ALE_QSPI_A_SCLK 0x82 |
| MX8MQ_IOMUXC_NAND_CE0_B_QSPI_A_SS0_B 0x82 |
| MX8MQ_IOMUXC_NAND_DATA00_QSPI_A_DATA0 0x82 |
| MX8MQ_IOMUXC_NAND_DATA01_QSPI_A_DATA1 0x82 |
| MX8MQ_IOMUXC_NAND_DATA02_QSPI_A_DATA2 0x82 |
| MX8MQ_IOMUXC_NAND_DATA03_QSPI_A_DATA3 0x82 |
| |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x49 |
| MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x49 |
| >; |
| }; |
| |
| pinctrl_uart3: uart3grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_UART3_TXD_UART3_DCE_TX 0x49 |
| MX8MQ_IOMUXC_UART3_RXD_UART3_DCE_RX 0x49 |
| MX8MQ_IOMUXC_ECSPI1_MISO_UART3_DCE_CTS_B 0x49 |
| MX8MQ_IOMUXC_ECSPI1_SS0_UART3_DCE_RTS_B 0x49 |
| MX8MQ_IOMUXC_NAND_CLE_GPIO3_IO5 0x19 |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 |
| MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 |
| MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 |
| MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x83 |
| MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc1_100mhz: usdhc1grp100mhz { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d |
| MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd |
| MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd |
| MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd |
| MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd |
| MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd |
| MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd |
| MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd |
| MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd |
| MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd |
| MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x8d |
| MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc1_200mhz: usdhc1grp200mhz { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f |
| MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf |
| MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf |
| MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf |
| MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf |
| MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf |
| MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf |
| MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf |
| MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf |
| MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf |
| MX8MQ_IOMUXC_SD1_STROBE_USDHC1_STROBE 0x9f |
| MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc2_gpio: usdhc2grpgpio { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD2_CD_B_GPIO2_IO12 0x41 |
| MX8MQ_IOMUXC_SD2_RESET_B_GPIO2_IO19 0x41 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 |
| MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 |
| MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 |
| MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 |
| MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 |
| MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 |
| MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc2_100mhz: usdhc2grp100mhz { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x8d |
| MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xcd |
| MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xcd |
| MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xcd |
| MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xcd |
| MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xcd |
| MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 |
| >; |
| }; |
| |
| pinctrl_usdhc2_200mhz: usdhc2grp200mhz { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x9f |
| MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xdf |
| MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xdf |
| MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xdf |
| MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xdf |
| MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xdf |
| MX8MQ_IOMUXC_GPIO1_IO04_USDHC2_VSELECT 0xc1 |
| >; |
| }; |
| |
| pinctrl_sai1_pcm: sai1grp_pcm { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 |
| MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 |
| >; |
| }; |
| |
| pinctrl_sai1_pcm_b2m: sai1grp_pcm_b2m { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SAI1_MCLK_SAI1_TX_BCLK 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 |
| MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_SYNC 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 |
| >; |
| }; |
| |
| pinctrl_sai1_dsd: sai1grp_dsd { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SAI1_MCLK_SAI1_MCLK 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXFS_SAI1_TX_SYNC 0xd6 |
| MX8MQ_IOMUXC_SAI1_RXD7_SAI1_TX_DATA4 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXC_SAI1_TX_BCLK 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD0_SAI1_TX_DATA0 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD1_SAI1_TX_DATA1 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD2_SAI1_TX_DATA2 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD3_SAI1_TX_DATA3 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD4_SAI1_TX_DATA4 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD5_SAI1_TX_DATA5 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD6_SAI1_TX_DATA6 0xd6 |
| MX8MQ_IOMUXC_SAI1_TXD7_SAI1_TX_DATA7 0xd6 |
| >; |
| }; |
| |
| pinctrl_sai2: sai2grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SAI2_TXFS_SAI2_TX_SYNC 0xd6 |
| MX8MQ_IOMUXC_SAI2_TXC_SAI2_TX_BCLK 0xd6 |
| MX8MQ_IOMUXC_SAI2_MCLK_SAI2_MCLK 0xd6 |
| MX8MQ_IOMUXC_SAI2_TXD0_SAI2_TX_DATA0 0xd6 |
| MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0xd6 |
| >; |
| }; |
| |
| pinctrl_sai5: sai5grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SAI5_MCLK_SAI5_MCLK 0xd6 |
| MX8MQ_IOMUXC_SAI5_RXC_SAI5_RX_BCLK 0xd6 |
| MX8MQ_IOMUXC_SAI5_RXFS_SAI5_RX_SYNC 0xd6 |
| MX8MQ_IOMUXC_SAI5_RXD0_SAI5_RX_DATA0 0xd6 |
| MX8MQ_IOMUXC_SAI5_RXD1_SAI5_RX_DATA1 0xd6 |
| MX8MQ_IOMUXC_SAI5_RXD2_SAI5_RX_DATA2 0xd6 |
| MX8MQ_IOMUXC_SAI5_RXD3_SAI5_RX_DATA3 0xd6 |
| >; |
| }; |
| |
| pinctrl_spdif1: spdif1grp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_SPDIF_TX_SPDIF1_OUT 0xd6 |
| MX8MQ_IOMUXC_SPDIF_RX_SPDIF1_IN 0xd6 |
| >; |
| }; |
| |
| pinctrl_wdog: wdoggrp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 |
| >; |
| }; |
| |
| pinctrl_wlan: wlangrp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_GPIO1_IO00_ANAMIX_REF_CLK_32K 0x16 |
| >; |
| }; |
| |
| pinctrl_wlan_init: wlan_initgrp { |
| fsl,pins = < |
| MX8MQ_IOMUXC_GPIO1_IO00_GPIO1_IO0 0x16 |
| >; |
| }; |
| |
| pinctrl_i2c1_dsi_ts_int: dsi_ts_int { |
| fsl,pins = < |
| MX8MQ_IOMUXC_ECSPI1_MOSI_GPIO5_IO7 0x19 |
| >; |
| }; |
| }; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_fec1>; |
| phy-mode = "rgmii-id"; |
| phy-handle = <ðphy0>; |
| fsl,magic-packet; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@0 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <0>; |
| at803x,led-act-blind-workaround; |
| at803x,eee-disabled; |
| }; |
| }; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <400000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| status = "okay"; |
| |
| pmic: pfuze100@08 { |
| compatible = "fsl,pfuze100"; |
| reg = <0x08>; |
| |
| regulators { |
| sw1a_reg: sw1ab { |
| regulator-min-microvolt = <300000>; |
| regulator-max-microvolt = <1875000>; |
| }; |
| |
| sw1c_reg: sw1c { |
| regulator-min-microvolt = <300000>; |
| regulator-max-microvolt = <1875000>; |
| }; |
| |
| sw2_reg: sw2 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| sw3a_reg: sw3ab { |
| regulator-min-microvolt = <400000>; |
| regulator-max-microvolt = <1975000>; |
| regulator-always-on; |
| }; |
| |
| sw4_reg: sw4 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| swbst_reg: swbst { |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5150000>; |
| }; |
| |
| snvs_reg: vsnvs { |
| regulator-min-microvolt = <1000000>; |
| regulator-max-microvolt = <3000000>; |
| regulator-always-on; |
| }; |
| |
| vref_reg: vrefddr { |
| regulator-always-on; |
| }; |
| |
| vgen1_reg: vgen1 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1550000>; |
| }; |
| |
| vgen2_reg: vgen2 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1550000>; |
| regulator-always-on; |
| }; |
| |
| vgen3_reg: vgen3 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen4_reg: vgen4 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen5_reg: vgen5 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen6_reg: vgen6 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| }; |
| }; |
| }; |
| |
| typec_ptn5100: ptn5110@50 { |
| compatible = "usb,tcpci"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_typec>; |
| reg = <0x50>; |
| interrupt-parent = <&gpio3>; |
| interrupts = <3 8>; |
| ss-sel-gpios = <&gpio3 15 GPIO_ACTIVE_HIGH>; |
| src-pdos = <0x380190c8>; |
| snk-pdos = <0x380190c8 0x3802d0c8>; |
| max-snk-mv = <9000>; |
| max-snk-ma = <2000>; |
| op-snk-mw = <9000>; |
| max-snk-mw = <18000>; |
| port-type = "drp"; |
| default-role = "sink"; |
| }; |
| |
| ov5640_mipi2: ov5640_mipi2@3c { |
| compatible = "ovti,ov5640_mipi"; |
| reg = <0x3c>; |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_csi2_pwn>, <&pinctrl_csi_rst>; |
| clocks = <&clk IMX8MQ_CLK_CLKO2>; |
| clock-names = "csi_mclk"; |
| assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; |
| assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; |
| assigned-clock-rates = <20000000>; |
| csi_id = <1>; |
| pwn-gpios = <&gpio1 5 GPIO_ACTIVE_HIGH>; |
| mclk = <20000000>; |
| mclk_source = <0>; |
| port { |
| ov5640_mipi2_ep: endpoint { |
| remote-endpoint = <&mipi2_sensor_ep>; |
| }; |
| }; |
| }; |
| |
| }; |
| |
| &i2c2 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| status = "okay"; |
| |
| ov5640_mipi: ov5640_mipi@3c { |
| compatible = "ovti,ov5640_mipi"; |
| reg = <0x3c>; |
| status = "okay"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_csi1_pwn>; |
| clocks = <&clk IMX8MQ_CLK_CLKO2>; |
| clock-names = "csi_mclk"; |
| assigned-clocks = <&clk IMX8MQ_CLK_CLKO2>; |
| assigned-clock-parents = <&clk IMX8MQ_SYS2_PLL_200M>; |
| assigned-clock-rates = <20000000>; |
| csi_id = <0>; |
| pwn-gpios = <&gpio1 3 GPIO_ACTIVE_HIGH>; |
| mclk = <20000000>; |
| mclk_source = <0>; |
| port { |
| ov5640_mipi1_ep: endpoint { |
| remote-endpoint = <&mipi1_sensor_ep>; |
| }; |
| }; |
| }; |
| }; |
| |
| &i2c3 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c3>; |
| status = "okay"; |
| |
| ak4458_1: ak4458@10 { |
| compatible = "asahi-kasei,ak4458"; |
| reg = <0x10>; |
| }; |
| |
| ak4458_2: ak4458@12 { |
| compatible = "asahi-kasei,ak4458"; |
| reg = <0x12>; |
| }; |
| |
| ak5558: ak5558@13 { |
| compatible = "asahi-kasei,ak5558"; |
| reg = <0x13>; |
| ak5558,pdn-gpio = <&gpio3 17 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| ak4497: ak4497@11 { |
| compatible = "asahi-kasei,ak4497"; |
| reg = <0x11>; |
| ak4497,pdn-gpio = <&gpio3 16 GPIO_ACTIVE_HIGH>; |
| }; |
| |
| synaptics_dsx_ts: synaptics_dsx_ts@20 { |
| compatible = "synaptics_dsx"; |
| reg = <0x20>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>; |
| interrupt-parent = <&gpio5>; |
| interrupts = <7 IRQ_TYPE_LEVEL_LOW>; |
| synaptics,diagonal-rotation; |
| status = "disabled"; |
| }; |
| |
| adv_bridge: adv7535@3d { |
| compatible = "adi,adv7533"; |
| reg = <0x3d>; |
| adi,addr-cec = <0x3b>; |
| adi,dsi-lanes = <4>; |
| pinctrl-0 = <&pinctrl_i2c1_dsi_ts_int>; |
| interrupt-parent = <&gpio5>; |
| interrupts = <7 IRQ_TYPE_LEVEL_LOW>; |
| |
| status = "disabled"; |
| |
| port { |
| adv7535_in: endpoint { |
| remote-endpoint = <&mipi_dsi_bridge_adv>; |
| }; |
| }; |
| }; |
| }; |
| |
| &pcie0{ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pcie0>; |
| disable-gpio = <&gpio5 29 GPIO_ACTIVE_LOW>; |
| reset-gpio = <&gpio5 28 GPIO_ACTIVE_LOW>; |
| ext_osc = <1>; |
| hard-wired = <1>; |
| status = "okay"; |
| }; |
| |
| &pcie1{ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pcie1>; |
| disable-gpio = <&gpio5 10 GPIO_ACTIVE_LOW>; |
| reset-gpio = <&gpio5 12 GPIO_ACTIVE_LOW>; |
| ext_osc = <1>; |
| status = "okay"; |
| }; |
| |
| &uart1 { /* console */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| assigned-clocks = <&clk IMX8MQ_CLK_UART1>; |
| assigned-clock-parents = <&clk IMX8MQ_CLK_25M>; |
| status = "okay"; |
| }; |
| |
| &qspi { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_qspi>; |
| status = "okay"; |
| |
| flash0: n25q256a@0 { |
| reg = <0>; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "micron,n25q256a"; |
| spi-max-frequency = <29000000>; |
| spi-nor,ddr-quad-read-dummy = <6>; |
| }; |
| }; |
| |
| &uart3 { /* BT */ |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart3>; |
| assigned-clocks = <&clk IMX8MQ_CLK_UART3>; |
| assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>; |
| fsl,uart-has-rtscts; |
| resets = <&modem_reset>; |
| status = "okay"; |
| }; |
| |
| &usdhc1 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| pinctrl-1 = <&pinctrl_usdhc1_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc1_200mhz>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; |
| pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; |
| bus-width = <4>; |
| cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; |
| vmmc-supply = <®_usdhc2_vmmc>; |
| status = "okay"; |
| }; |
| |
| &usb3_phy0 { |
| status = "okay"; |
| }; |
| |
| &usb3_0 { |
| status = "okay"; |
| }; |
| |
| &usb_dwc3_0 { |
| status = "okay"; |
| extcon = <&typec_ptn5100>; |
| dr_mode = "otg"; |
| hnp-disable; |
| srp-disable; |
| adp-disable; |
| }; |
| |
| &usb3_phy1 { |
| status = "okay"; |
| }; |
| |
| &usb3_1 { |
| status = "okay"; |
| }; |
| |
| &usb_dwc3_1 { |
| status = "okay"; |
| dr_mode = "host"; |
| }; |
| |
| &sai1 { |
| pinctrl-names = "default", "pcm_b2m", "dsd"; |
| pinctrl-0 = <&pinctrl_sai1_pcm>; |
| pinctrl-1 = <&pinctrl_sai1_pcm_b2m>; |
| pinctrl-2 = <&pinctrl_sai1_dsd>; |
| assigned-clocks = <&clk IMX8MQ_CLK_SAI1>; |
| assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; |
| assigned-clock-rates = <49152000>; |
| clocks = <&clk IMX8MQ_CLK_SAI1_IPG>, <&clk IMX8MQ_CLK_DUMMY>, |
| <&clk IMX8MQ_CLK_SAI1_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, |
| <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, |
| <&clk IMX8MQ_AUDIO_PLL2_OUT>; |
| clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; |
| fsl,sai-multi-lane; |
| fsl,dataline,dsd = <0 0xff 0xff 2 0xff 0x11>; |
| dmas = <&sdma2 8 26 0>, <&sdma2 9 26 0>; |
| status = "okay"; |
| }; |
| |
| &sai2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sai2>; |
| assigned-clocks = <&clk IMX8MQ_CLK_SAI2>; |
| assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; |
| assigned-clock-rates = <24576000>; |
| status = "okay"; |
| }; |
| |
| &sai4 { |
| assigned-clocks = <&clk IMX8MQ_CLK_SAI4>; |
| assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; |
| assigned-clock-rates = <24576000>; |
| clocks = <&clk IMX8MQ_CLK_SAI4_IPG>, <&clk IMX8MQ_CLK_DUMMY>, |
| <&clk IMX8MQ_CLK_SAI4_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, |
| <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, |
| <&clk IMX8MQ_AUDIO_PLL2_OUT>; |
| clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; |
| status = "okay"; |
| }; |
| |
| &sai5 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sai5>; |
| assigned-clocks = <&clk IMX8MQ_CLK_SAI5>; |
| assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; |
| assigned-clock-rates = <49152000>; |
| clocks = <&clk IMX8MQ_CLK_SAI5_IPG>, <&clk IMX8MQ_CLK_DUMMY>, |
| <&clk IMX8MQ_CLK_SAI5_ROOT>, <&clk IMX8MQ_CLK_DUMMY>, |
| <&clk IMX8MQ_CLK_DUMMY>, <&clk IMX8MQ_AUDIO_PLL1_OUT>, |
| <&clk IMX8MQ_AUDIO_PLL2_OUT>; |
| clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3", "pll8k", "pll11k"; |
| fsl,sai-asynchronous; |
| status = "okay"; |
| }; |
| |
| &spdif1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_spdif1>; |
| assigned-clocks = <&clk IMX8MQ_CLK_SPDIF1>; |
| assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; |
| assigned-clock-rates = <24576000>; |
| status = "okay"; |
| }; |
| |
| &spdif2 { |
| assigned-clocks = <&clk IMX8MQ_CLK_SPDIF2>; |
| assigned-clock-parents = <&clk IMX8MQ_AUDIO_PLL1_OUT>; |
| assigned-clock-rates = <24576000>; |
| status = "okay"; |
| }; |
| |
| &gpu_pd { |
| power-supply = <&sw1a_reg>; |
| }; |
| |
| &vpu_pd { |
| power-supply = <&sw1c_reg>; |
| }; |
| |
| &gpu { |
| status = "okay"; |
| }; |
| |
| &vpu { |
| status = "okay"; |
| }; |
| |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| fsl,ext-reset-output; |
| status = "okay"; |
| }; |
| |
| &mu { |
| status = "okay"; |
| }; |
| |
| &A53_0 { |
| operating-points = < |
| /* kHz uV */ |
| 1500000 1000000 |
| 1300000 1000000 |
| 1000000 900000 |
| 800000 900000 |
| >; |
| dc-supply = <®_gpio_dvfs>; |
| }; |
| |
| &dcss { |
| status = "okay"; |
| |
| disp-dev = "hdmi_disp"; |
| }; |
| |
| &hdmi { |
| status = "okay"; |
| }; |
| |
| &csi1_bridge { |
| fsl,mipi-mode; |
| fsl,two-8bit-sensor-mode; |
| status = "okay"; |
| |
| port { |
| csi1_ep: endpoint { |
| remote-endpoint = <&csi1_mipi_ep>; |
| }; |
| }; |
| }; |
| |
| &csi2_bridge { |
| fsl,mipi-mode; |
| fsl,two-8bit-sensor-mode; |
| status = "okay"; |
| |
| port { |
| csi2_ep: endpoint { |
| remote-endpoint = <&csi2_mipi_ep>; |
| }; |
| }; |
| }; |
| |
| &mipi_csi_1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "okay"; |
| port { |
| mipi1_sensor_ep: endpoint1 { |
| remote-endpoint = <&ov5640_mipi1_ep>; |
| data-lanes = <1 2>; |
| }; |
| |
| csi1_mipi_ep: endpoint2 { |
| remote-endpoint = <&csi1_ep>; |
| }; |
| }; |
| }; |
| |
| &mipi_csi_2 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| status = "okay"; |
| port { |
| mipi2_sensor_ep: endpoint1 { |
| remote-endpoint = <&ov5640_mipi2_ep>; |
| data-lanes = <1 2>; |
| }; |
| |
| csi2_mipi_ep: endpoint2 { |
| remote-endpoint = <&csi2_ep>; |
| }; |
| }; |
| }; |
| |
| &mipi_dsi_bridge { |
| port@1 { |
| mipi_dsi_bridge_adv: endpoint { |
| remote-endpoint = <&adv7535_in>; |
| }; |
| }; |
| }; |
