| Freescale i.MX DRM master device |
| ================================ |
| |
| The freescale i.MX DRM master device is a virtual device needed to list all |
| IPU or other display interface nodes that comprise the graphics subsystem. |
| |
| Required properties: |
| - compatible: Should be "fsl,imx-display-subsystem" |
| - ports: Should contain a list of phandles pointing to display interface ports |
| of IPU devices |
| |
| example: |
| |
| display-subsystem { |
| compatible = "fsl,display-subsystem"; |
| ports = <&ipu_di0>; |
| }; |
| |
| |
| Freescale i.MX IPUv3 |
| ==================== |
| |
| Required properties: |
| - compatible: Should be "fsl,<chip>-ipu" |
| - reg: should be register base and length as documented in the |
| datasheet |
| - interrupts: Should contain sync interrupt and error interrupt, |
| in this order. |
| - resets: phandle pointing to the system reset controller and |
| reset line index, see reset/fsl,imx-src.txt for details |
| Optional properties: |
| - port@[0-3]: Port nodes with endpoint definitions as defined in |
| Documentation/devicetree/bindings/media/video-interfaces.txt. |
| Ports 0 and 1 should correspond to CSI0 and CSI1, |
| ports 2 and 3 should correspond to DI0 and DI1, respectively. |
| |
| example: |
| |
| ipu: ipu@18000000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx53-ipu"; |
| reg = <0x18000000 0x080000000>; |
| interrupts = <11 10>; |
| resets = <&src 2>; |
| |
| ipu_di0: port@2 { |
| reg = <2>; |
| |
| ipu_di0_disp0: endpoint { |
| remote-endpoint = <&display_in>; |
| }; |
| }; |
| }; |
| |
| Freescale i.MX DPU |
| ==================== |
| |
| Required properties: |
| - compatible: Should be "fsl,<chip>-dpu" |
| - reg: should be register base and length as documented in the |
| datasheet |
| - intsteer: phandle pointing to interrupt steer. |
| - interrupts, interrupt-names: Should contain interrupts and names as |
| documented in the datasheet. |
| - clocks, clock-names: phandles to the DPU clocks described in |
| Documentation/devicetree/bindings/clock/clock-bindings.txt |
| The following clocks are expected on i.MX8qm and i.MX8qxp: |
| "pll0" - PLL clock for display interface 0 |
| "pll1" - PLL clock for display interface 1 |
| "disp0" - pixel clock for display interface 0 |
| "disp1" - pixel clock for display interface 1 |
| The needed clock numbers for each are documented in |
| Documentation/devicetree/bindings/clock/imx8qm-clock.txt, and in |
| Documentation/devicetree/bindings/clock/imx8qxp-clock.txt. |
| - power-domains: phandle pointing to power domain. |
| - fsl,dpr-channels: phandles to the DPR channels attached to this DPU, |
| sorted by memory map addresses. Only valid for i.MX8qm and i.MX8qxp. |
| Optional properties: |
| - port@[0-1]: Port nodes with endpoint definitions as defined in |
| Documentation/devicetree/bindings/media/video-interfaces.txt. |
| ports 0 and 1 should correspond to display interface 0 and |
| display interface 1, respectively. |
| |
| example: |
| |
| dpu: dpu@56180000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "fsl,imx8qm-dpu"; |
| reg = <0x0 0x56180000 0x0 0x40000>; |
| intsteer = <&dpu1_intsteer>; |
| interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "irq_common", |
| "irq_stream0a", |
| "irq_stream0b", |
| "irq_stream1a", |
| "irq_stream1b", |
| "irq_reserved0", |
| "irq_reserved1", |
| "irq_blit"; |
| clocks = <&clk IMX8QM_DC0_PLL0_CLK>, |
| <&clk IMX8QM_DC0_PLL1_CLK>, |
| <&clk IMX8QM_DC0_DISP0_CLK>, |
| <&clk IMX8QM_DC0_DISP1_CLK>; |
| clock-names = "pll0", "pll1", "disp0", "disp1"; |
| power-domains = <&pd_dc0>; |
| fsl,dpr-channels = <&dpr1_channel1>, <&dpr1_channel2>, |
| <&dpr1_channel3>, <&dpr2_channel1>, |
| <&dpr2_channel2>, <&dpr2_channel3>; |
| |
| dpu1_disp1: port@1 { |
| reg = <1>; |
| |
| dpu1_disp1_lvds0: lvds0-endpoint { |
| remote-endpoint = <&ldb1_lvds0>; |
| }; |
| |
| dpu1_disp1_lvds1: lvds1-endpoint { |
| remote-endpoint = <&ldb1_lvds1>; |
| }; |
| }; |
| }; |
| |
| |
| NXP i.MX Display Controller Subsystem (DCSS) |
| ============================================= |
| |
| Required properties: |
| - compatible: Should be "nxp,<chip>-dcss" |
| - reg: should be register base and length as documented in the |
| datasheet. |
| - interrupts, interrupt-names: Should contain interrupts and names as |
| documented in the datasheet. |
| - interrupt-parent: contains the phandle to IRQ Steer module. |
| - clocks, clock-names: phandles to the DCSS clocks described in |
| Documentation/devicetree/bindings/clock/clock-bindings.txt |
| - disp-dev: can take following values: |
| - hdmi_disp: DCSS output goes to HDMI |
| - mipi_disp: DCSS output goes to MIPI_DSI |
| Optional properties: |
| - port@[0-1]: Port nodes with endpoint definitions as defined in |
| Documentation/devicetree/bindings/media/video-interfaces.txt. |
| ports 0 and 1 should correspond to display interface 0 and |
| display interface 1, respectively. |
| |
| |
| example: |
| |
| dcss_drm: dcss@0x32e00000 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| compatible = "nxp,imx8mq-dcss"; |
| reg = <0x0 0x32e00000 0x0 0x30000>; |
| interrupts = <3 IRQ_TYPE_LEVEL_HIGH>, <4 IRQ_TYPE_LEVEL_HIGH>, <5 IRQ_TYPE_LEVEL_HIGH>, |
| <6 IRQ_TYPE_LEVEL_HIGH>, <8 IRQ_TYPE_EDGE_RISING>; |
| interrupt-names = "dpr_dc_ch0", "dpr_dc_ch1", "dpr_dc_ch2", "ctx_ld", |
| "dtg_prg1"; |
| interrupt-parent = <&irqsteer_dcss>; |
| clocks = <&clk IMX8MQ_CLK_DISP_APB_ROOT>, |
| <&clk IMX8MQ_CLK_DISP_AXI_ROOT>, |
| <&clk IMX8MQ_CLK_DISP_RTRM_ROOT>, |
| <&clk IMX8MQ_CLK_DC_PIXEL_DIV>, |
| <&clk IMX8MQ_CLK_DISP_DTRC_DIV>; |
| clock-names = "apb", "axi", "rtrm", "pixel", "dtrc"; |
| assigned-clocks = <&clk IMX8MQ_CLK_DISP_APB_SRC>, |
| <&clk IMX8MQ_CLK_DISP_AXI_SRC>, |
| <&clk IMX8MQ_CLK_DISP_RTRM_SRC>, |
| <&clk IMX8MQ_CLK_DC_PIXEL_SRC>, |
| <&clk IMX8MQ_CLK_DISP_DTRC_SRC>; |
| assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_800M>, |
| <&clk IMX8MQ_SYS1_PLL_800M>, |
| <&clk IMX8MQ_SYS1_PLL_800M>, |
| <&clk IMX8MQ_VIDEO_PLL1_OUT>, |
| <&clk IMX8MQ_CLK_25M>; |
| assigned-clock-rate = <800000000>, <800000000>, <800000000>, <594000000>, <25000000>; |
| |
| disp-dev = "hdmi_disp"; |
| |
| status = "okay"; |
| |
| dcss_disp0: port@0 { |
| reg = <0>; |
| |
| dcss_disp0_imx_stub: imx_stub_conenc { |
| remote-endpoint = <&imx_stub_conenc0>; |
| }; |
| }; |
| }; |
| |
| Freescale i.MX8 PRG (Prefetch Resolve Gasket) |
| ============================================= |
| Required properties: |
| - compatible: should be "fsl,<chip>-prg" |
| - reg: should be register base and length as documented in the |
| datasheet |
| - clocks: phandles to the PRG apb and rtram clocks, as described in |
| Documentation/devicetree/bindings/clock/clock-bindings.txt, |
| Documentation/devicetree/bindings/clock/imx8qm-clock.txt and |
| Documentation/devicetree/bindings/clock/imx8qxp-clock.txt |
| - clock-names: should be "apb" and "rtram" |
| - power-domains: phandle pointing to power domain |
| |
| example: |
| |
| prg@56040000 { |
| compatible = "fsl,imx8qm-prg"; |
| reg = <0x0 0x56040000 0x0 0x10000>; |
| clocks = <&clk IMX8QM_DC0_PRG0_APB_CLK>, |
| <&clk IMX8QM_DC0_PRG0_RTRAM_CLK>; |
| clock-names = "apb", "rtram"; |
| power-domains = <&pd_dc0>; |
| }; |
| |
| Freescale i.MX8 DPRC (Display Prefetch Resolve Channel) |
| ======================================================= |
| Required properties: |
| - compatible: should be "fsl,<chip>-dpr-channel" |
| - reg: should be register base and length as documented in the |
| datasheet |
| - fsl,sc-resource: SCU resource number as described in |
| Documentation/devicetree/bindings/soc/fsl/imx_rsrc.txt |
| - fsl,prgs: phandles to the PRG unit(s) attached to this DPRC, the first one |
| is the primary PRG and the second one(if available) is the auxiliary PRG |
| which is used to fetch luma chunk of a YUV frame with 2 planars. |
| - clocks: phandles to the DPRC apb, b and rtram clocks, as described in |
| Documentation/devicetree/bindings/clock/clock-bindings.txt, |
| Documentation/devicetree/bindings/clock/imx8qm-clock.txt and |
| Documentation/devicetree/bindings/clock/imx8qxp-clock.txt |
| - clock-names: should be "apb", "b" and "rtram" |
| - power-domains: phandle pointing to power domain |
| |
| example: |
| |
| dpr-channel@56100000 { |
| compatible = "fsl,imx8qm-dpr-channel"; |
| reg = <0x0 0x56100000 0x0 0x10000>; |
| fsl,sc-resource = <SC_R_DC_0_VIDEO0>; |
| fsl,prgs = <&prg4>, <&prg5>; |
| clocks = <&clk IMX8QM_DC0_DPR1_APB_CLK>, |
| <&clk IMX8QM_DC0_DPR1_B_CLK>, |
| <&clk IMX8QM_DC0_RTRAM1_CLK>; |
| clock-names = "apb", "b", "rtram"; |
| power-domains = <&pd_dc0>; |
| }; |
| |
| Parallel display support |
| ======================== |
| |
| Required properties: |
| - compatible: Should be "fsl,imx-parallel-display" |
| Optional properties: |
| - interface_pix_fmt: How this display is connected to the |
| display interface. Currently supported types: "rgb24", "rgb565", "bgr666" |
| and "lvds666". |
| - edid: verbatim EDID data block describing attached display. |
| - ddc: phandle describing the i2c bus handling the display data |
| channel |
| - port@[0-1]: Port nodes with endpoint definitions as defined in |
| Documentation/devicetree/bindings/media/video-interfaces.txt. |
| Port 0 is the input port connected to the IPU display interface, |
| port 1 is the output port connected to a panel. |
| |
| example: |
| |
| display@di0 { |
| compatible = "fsl,imx-parallel-display"; |
| edid = [edid-data]; |
| interface-pix-fmt = "rgb24"; |
| |
| port@0 { |
| reg = <0>; |
| |
| display_in: endpoint { |
| remote-endpoint = <&ipu_di0_disp0>; |
| }; |
| }; |
| |
| port@1 { |
| reg = <1>; |
| |
| display_out: endpoint { |
| remote-endpoint = <&panel_in>; |
| }; |
| }; |
| }; |
| |
| panel { |
| ... |
| |
| port { |
| panel_in: endpoint { |
| remote-endpoint = <&display_out>; |
| }; |
| }; |
| }; |