| /* |
| * Copyright (C) 2015 Freescale Semiconductor, Inc. |
| * Copyright 2017 NXP |
| * |
| * This program is free software; you can redistribute it and/or modify |
| * it under the terms of the GNU General Public License version 2 as |
| * published by the Free Software Foundation. |
| */ |
| |
| /dts-v1/; |
| |
| #include <dt-bindings/input/input.h> |
| #include "imx6ul.dtsi" |
| |
| / { |
| model = "Freescale i.MX6 UltraLite 9x9 EVK Board"; |
| compatible = "fsl,imx6ul-9x9-evk", "fsl,imx6ul"; |
| |
| backlight { |
| compatible = "pwm-backlight"; |
| pwms = <&pwm1 0 5000000>; |
| brightness-levels = <0 4 8 16 32 64 128 255>; |
| default-brightness-level = <6>; |
| status = "okay"; |
| }; |
| |
| chosen { |
| stdout-path = &uart1; |
| }; |
| |
| memory { |
| reg = <0x80000000 0x10000000>; |
| }; |
| |
| reserved-memory { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| ranges; |
| |
| linux,cma { |
| compatible = "shared-dma-pool"; |
| reusable; |
| size = <0x6000000>; |
| linux,cma-default; |
| }; |
| }; |
| |
| pxp_v4l2 { |
| compatible = "fsl,imx6ul-pxp-v4l2", "fsl,imx6sx-pxp-v4l2", "fsl,imx6sl-pxp-v4l2"; |
| status = "okay"; |
| }; |
| |
| regulators { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| reg_can_3v3: regulator@0 { |
| compatible = "regulator-fixed"; |
| reg = <0>; |
| regulator-name = "can-3v3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpios = <&gpio_spi 3 GPIO_ACTIVE_LOW>; |
| }; |
| |
| reg_gpio_dvfs: regulator-gpio { |
| compatible = "regulator-gpio"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_dvfs>; |
| regulator-min-microvolt = <1300000>; |
| regulator-max-microvolt = <1400000>; |
| regulator-name = "gpio_dvfs"; |
| regulator-type = "voltage"; |
| gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>; |
| states = <1300000 0x1 1400000 0x0>; |
| }; |
| |
| reg_sd1_vmmc: regulator@1 { |
| compatible = "regulator-fixed"; |
| regulator-name = "VSD_3V3"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>; |
| off-on-delay = <20000>; |
| enable-active-high; |
| }; |
| }; |
| |
| sound { |
| compatible = "fsl,imx6ul-evk-wm8960", |
| "fsl,imx-audio-wm8960"; |
| model = "wm8960-audio"; |
| cpu-dai = <&sai2>; |
| audio-codec = <&codec>; |
| asrc-controller = <&asrc>; |
| codec-master; |
| gpr = <&gpr 4 0x100000 0x100000>; |
| /* |
| * hp-det = <hp-det-pin hp-det-polarity>; |
| * hp-det-pin: JD1 JD2 or JD3 |
| * hp-det-polarity = 0: hp detect high for headphone |
| * hp-det-polarity = 1: hp detect high for speaker |
| */ |
| hp-det = <3 0>; |
| hp-det-gpios = <&gpio5 4 0>; |
| mic-det-gpios = <&gpio5 4 0>; |
| audio-routing = |
| "Headphone Jack", "HP_L", |
| "Headphone Jack", "HP_R", |
| "Ext Spk", "SPK_LP", |
| "Ext Spk", "SPK_LN", |
| "Ext Spk", "SPK_RP", |
| "Ext Spk", "SPK_RN", |
| "LINPUT2", "Mic Jack", |
| "LINPUT3", "Mic Jack", |
| "RINPUT1", "Main MIC", |
| "RINPUT2", "Main MIC", |
| "Mic Jack", "MICB", |
| "Main MIC", "MICB", |
| "CPU-Playback", "ASRC-Playback", |
| "Playback", "CPU-Playback", |
| "ASRC-Capture", "CPU-Capture", |
| "CPU-Capture", "Capture"; |
| }; |
| |
| spi4 { |
| compatible = "spi-gpio"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_spi4>; |
| pinctrl-assert-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; |
| status = "okay"; |
| gpio-sck = <&gpio5 11 0>; |
| gpio-mosi = <&gpio5 10 0>; |
| cs-gpios = <&gpio5 7 0>; |
| num-chipselects = <1>; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| gpio_spi: gpio_spi@0 { |
| compatible = "fairchild,74hc595"; |
| gpio-controller; |
| #gpio-cells = <2>; |
| reg = <0>; |
| registers-number = <1>; |
| registers-default = /bits/ 8 <0x57>; |
| spi-max-frequency = <100000>; |
| }; |
| }; |
| }; |
| |
| &clks { |
| assigned-clocks = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; |
| assigned-clock-rates = <786432000>; |
| }; |
| |
| &cpu0 { |
| /* |
| * on i.MX6UL, no seperated VDD_ARM_IN and VDD_SOC_IN, |
| * to align with other platform and use the same cpufreq |
| * driver, still use the seperated OPP define for arm |
| * and soc. |
| */ |
| operating-points = < |
| /* kHz uV */ |
| 528000 1175000 |
| 396000 1175000 |
| 198000 1175000 |
| >; |
| fsl,soc-operating-points = < |
| /* KHz uV */ |
| 528000 1175000 |
| 396000 1175000 |
| 198000 1175000 |
| >; |
| fsl,arm-soc-shared = <1>; |
| }; |
| |
| ®_arm { |
| vin-supply = <&sw1c_reg>; |
| regulator-allow-bypass; |
| }; |
| |
| ®_soc { |
| vin-supply = <&sw1c_reg>; |
| regulator-allow-bypass; |
| }; |
| |
| &csi { |
| status = "disabled"; |
| |
| port { |
| csi1_ep: endpoint { |
| remote-endpoint = <&ov5640_ep>; |
| }; |
| }; |
| }; |
| |
| &fec1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet1>; |
| phy-mode = "rmii"; |
| phy-handle = <ðphy0>; |
| status = "okay"; |
| }; |
| |
| &fec2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_enet2>; |
| phy-mode = "rmii"; |
| phy-handle = <ðphy1>; |
| status = "okay"; |
| |
| mdio { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| ethphy0: ethernet-phy@2 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <2>; |
| }; |
| |
| ethphy1: ethernet-phy@1 { |
| compatible = "ethernet-phy-ieee802.3-c22"; |
| reg = <1>; |
| }; |
| }; |
| }; |
| |
| &can1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan1>; |
| xceiver-supply = <®_can_3v3>; |
| status = "okay"; |
| }; |
| |
| &can2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_flexcan2>; |
| xceiver-supply = <®_can_3v3>; |
| status = "okay"; |
| }; |
| |
| &gpc { |
| fsl,cpu_pupscr_sw2iso = <0xf>; |
| fsl,cpu_pupscr_sw = <0x0>; |
| fsl,cpu_pdnscr_iso2sw = <0x1>; |
| fsl,cpu_pdnscr_iso = <0x1>; |
| fsl,ldo-bypass = <1>; |
| }; |
| |
| &i2c1 { |
| clock-frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c1>; |
| status = "okay"; |
| |
| pmic: pfuze3000@08 { |
| compatible = "fsl,pfuze3000"; |
| reg = <0x08>; |
| |
| regulators { |
| sw1a_reg: sw1a { |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <6250>; |
| }; |
| |
| /* use sw1c_reg to align with pfuze100/pfuze200 */ |
| sw1c_reg: sw1b { |
| regulator-min-microvolt = <700000>; |
| regulator-max-microvolt = <1475000>; |
| regulator-boot-on; |
| regulator-always-on; |
| regulator-ramp-delay = <6250>; |
| }; |
| |
| sw2_reg: sw2 { |
| regulator-min-microvolt = <2500000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| sw3a_reg: sw3 { |
| regulator-min-microvolt = <900000>; |
| regulator-max-microvolt = <1650000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| swbst_reg: swbst { |
| regulator-min-microvolt = <5000000>; |
| regulator-max-microvolt = <5150000>; |
| }; |
| |
| snvs_reg: vsnvs { |
| regulator-min-microvolt = <1000000>; |
| regulator-max-microvolt = <3000000>; |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vref_reg: vrefddr { |
| regulator-boot-on; |
| regulator-always-on; |
| }; |
| |
| vgen1_reg: vldo1 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen2_reg: vldo2 { |
| regulator-min-microvolt = <800000>; |
| regulator-max-microvolt = <1550000>; |
| regulator-always-on; |
| }; |
| |
| vgen3_reg: vccsd { |
| regulator-min-microvolt = <2850000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen4_reg: v33 { |
| regulator-min-microvolt = <2850000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen5_reg: vldo3 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| |
| vgen6_reg: vldo4 { |
| regulator-min-microvolt = <1800000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| }; |
| }; |
| |
| mag3110@0e { |
| compatible = "fsl,mag3110"; |
| reg = <0x0e>; |
| position = <2>; |
| }; |
| |
| fxls8471@1e { |
| compatible = "fsl,fxls8471"; |
| reg = <0x1e>; |
| position = <0>; |
| interrupt-parent = <&gpio5>; |
| interrupts = <0 8>; |
| }; |
| }; |
| |
| &i2c2 { |
| clock_frequency = <100000>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_i2c2>; |
| status = "okay"; |
| |
| codec: wm8960@1a { |
| compatible = "wlf,wm8960"; |
| reg = <0x1a>; |
| clocks = <&clks IMX6UL_CLK_SAI2>; |
| clock-names = "mclk"; |
| wlf,shared-lrclk; |
| }; |
| |
| ov5640: ov5640@3c { |
| compatible = "ovti,ov5640"; |
| reg = <0x3c>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_csi1>; |
| clocks = <&clks IMX6UL_CLK_CSI>; |
| clock-names = "csi_mclk"; |
| pwn-gpios = <&gpio_spi 6 1>; |
| rst-gpios = <&gpio_spi 5 0>; |
| csi_id = <0>; |
| mclk = <24000000>; |
| mclk_source = <0>; |
| status = "disabled"; |
| port { |
| ov5640_ep: endpoint { |
| remote-endpoint = <&csi1_ep>; |
| }; |
| }; |
| }; |
| }; |
| |
| &iomuxc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_hog_1>; |
| imx6ul-evk { |
| pinctrl_csi1: csi1grp { |
| fsl,pins = < |
| MX6UL_PAD_CSI_MCLK__CSI_MCLK 0x1b088 |
| MX6UL_PAD_CSI_PIXCLK__CSI_PIXCLK 0x1b088 |
| MX6UL_PAD_CSI_VSYNC__CSI_VSYNC 0x1b088 |
| MX6UL_PAD_CSI_HSYNC__CSI_HSYNC 0x1b088 |
| MX6UL_PAD_CSI_DATA00__CSI_DATA02 0x1b088 |
| MX6UL_PAD_CSI_DATA01__CSI_DATA03 0x1b088 |
| MX6UL_PAD_CSI_DATA02__CSI_DATA04 0x1b088 |
| MX6UL_PAD_CSI_DATA03__CSI_DATA05 0x1b088 |
| MX6UL_PAD_CSI_DATA04__CSI_DATA06 0x1b088 |
| MX6UL_PAD_CSI_DATA05__CSI_DATA07 0x1b088 |
| MX6UL_PAD_CSI_DATA06__CSI_DATA08 0x1b088 |
| MX6UL_PAD_CSI_DATA07__CSI_DATA09 0x1b088 |
| >; |
| }; |
| |
| pinctrl_dvfs: dvfsgrp { |
| fsl,pins = < |
| MX6UL_PAD_SNVS_TAMPER3__GPIO5_IO03 0x79 |
| >; |
| }; |
| |
| pinctrl_enet1: enet1grp { |
| fsl,pins = < |
| MX6UL_PAD_ENET1_RX_EN__ENET1_RX_EN 0x1b0b0 |
| MX6UL_PAD_ENET1_RX_ER__ENET1_RX_ER 0x1b0b0 |
| MX6UL_PAD_ENET1_RX_DATA0__ENET1_RDATA00 0x1b0b0 |
| MX6UL_PAD_ENET1_RX_DATA1__ENET1_RDATA01 0x1b0b0 |
| MX6UL_PAD_ENET1_TX_EN__ENET1_TX_EN 0x1b0b0 |
| MX6UL_PAD_ENET1_TX_DATA0__ENET1_TDATA00 0x1b0b0 |
| MX6UL_PAD_ENET1_TX_DATA1__ENET1_TDATA01 0x1b0b0 |
| MX6UL_PAD_ENET1_TX_CLK__ENET1_REF_CLK1 0x4001b031 |
| >; |
| }; |
| |
| pinctrl_enet2: enet2grp { |
| fsl,pins = < |
| MX6UL_PAD_GPIO1_IO07__ENET2_MDC 0x1b0b0 |
| MX6UL_PAD_GPIO1_IO06__ENET2_MDIO 0x1b0b0 |
| MX6UL_PAD_ENET2_RX_EN__ENET2_RX_EN 0x1b0b0 |
| MX6UL_PAD_ENET2_RX_ER__ENET2_RX_ER 0x1b0b0 |
| MX6UL_PAD_ENET2_RX_DATA0__ENET2_RDATA00 0x1b0b0 |
| MX6UL_PAD_ENET2_RX_DATA1__ENET2_RDATA01 0x1b0b0 |
| MX6UL_PAD_ENET2_TX_EN__ENET2_TX_EN 0x1b0b0 |
| MX6UL_PAD_ENET2_TX_DATA0__ENET2_TDATA00 0x1b0b0 |
| MX6UL_PAD_ENET2_TX_DATA1__ENET2_TDATA01 0x1b0b0 |
| MX6UL_PAD_ENET2_TX_CLK__ENET2_REF_CLK2 0x4001b031 |
| MX6UL_PAD_SNVS_TAMPER0__GPIO5_IO00 0x80000000 |
| >; |
| }; |
| |
| pinctrl_flexcan1: flexcan1grp{ |
| fsl,pins = < |
| MX6UL_PAD_UART3_RTS_B__FLEXCAN1_RX 0x1b020 |
| MX6UL_PAD_UART3_CTS_B__FLEXCAN1_TX 0x1b020 |
| >; |
| }; |
| |
| pinctrl_flexcan2: flexcan2grp{ |
| fsl,pins = < |
| MX6UL_PAD_UART2_RTS_B__FLEXCAN2_RX 0x1b020 |
| MX6UL_PAD_UART2_CTS_B__FLEXCAN2_TX 0x1b020 |
| >; |
| }; |
| |
| pinctrl_hog_1: hoggrp-1 { |
| fsl,pins = < |
| MX6UL_PAD_UART1_RTS_B__GPIO1_IO19 0x17059 /* SD1 CD */ |
| MX6UL_PAD_GPIO1_IO05__USDHC1_VSELECT 0x17059 /* SD1 VSELECT */ |
| MX6UL_PAD_GPIO1_IO09__GPIO1_IO09 0x17059 /* SD1 RESET */ |
| >; |
| }; |
| |
| pinctrl_i2c1: i2c1grp { |
| fsl,pins = < |
| MX6UL_PAD_UART4_TX_DATA__I2C1_SCL 0x4001b8b0 |
| MX6UL_PAD_UART4_RX_DATA__I2C1_SDA 0x4001b8b0 |
| >; |
| }; |
| |
| pinctrl_i2c2: i2c2grp { |
| fsl,pins = < |
| MX6UL_PAD_UART5_TX_DATA__I2C2_SCL 0x4001b8b0 |
| MX6UL_PAD_UART5_RX_DATA__I2C2_SDA 0x4001b8b0 |
| >; |
| }; |
| |
| pinctrl_lcdif_ctrl: lcdifctrlgrp { |
| fsl,pins = < |
| MX6UL_PAD_LCD_CLK__LCDIF_CLK 0x79 |
| MX6UL_PAD_LCD_ENABLE__LCDIF_ENABLE 0x79 |
| MX6UL_PAD_LCD_HSYNC__LCDIF_HSYNC 0x79 |
| MX6UL_PAD_LCD_VSYNC__LCDIF_VSYNC 0x79 |
| /* used for lcd reset */ |
| MX6UL_PAD_SNVS_TAMPER9__GPIO5_IO09 0x79 |
| >; |
| }; |
| |
| pinctrl_lcdif_dat: lcdifdatgrp { |
| fsl,pins = < |
| MX6UL_PAD_LCD_DATA00__LCDIF_DATA00 0x79 |
| MX6UL_PAD_LCD_DATA01__LCDIF_DATA01 0x79 |
| MX6UL_PAD_LCD_DATA02__LCDIF_DATA02 0x79 |
| MX6UL_PAD_LCD_DATA03__LCDIF_DATA03 0x79 |
| MX6UL_PAD_LCD_DATA04__LCDIF_DATA04 0x79 |
| MX6UL_PAD_LCD_DATA05__LCDIF_DATA05 0x79 |
| MX6UL_PAD_LCD_DATA06__LCDIF_DATA06 0x79 |
| MX6UL_PAD_LCD_DATA07__LCDIF_DATA07 0x79 |
| MX6UL_PAD_LCD_DATA08__LCDIF_DATA08 0x79 |
| MX6UL_PAD_LCD_DATA09__LCDIF_DATA09 0x79 |
| MX6UL_PAD_LCD_DATA10__LCDIF_DATA10 0x79 |
| MX6UL_PAD_LCD_DATA11__LCDIF_DATA11 0x79 |
| MX6UL_PAD_LCD_DATA12__LCDIF_DATA12 0x79 |
| MX6UL_PAD_LCD_DATA13__LCDIF_DATA13 0x79 |
| MX6UL_PAD_LCD_DATA14__LCDIF_DATA14 0x79 |
| MX6UL_PAD_LCD_DATA15__LCDIF_DATA15 0x79 |
| MX6UL_PAD_LCD_DATA16__LCDIF_DATA16 0x79 |
| MX6UL_PAD_LCD_DATA17__LCDIF_DATA17 0x79 |
| MX6UL_PAD_LCD_DATA18__LCDIF_DATA18 0x79 |
| MX6UL_PAD_LCD_DATA19__LCDIF_DATA19 0x79 |
| MX6UL_PAD_LCD_DATA20__LCDIF_DATA20 0x79 |
| MX6UL_PAD_LCD_DATA21__LCDIF_DATA21 0x79 |
| MX6UL_PAD_LCD_DATA22__LCDIF_DATA22 0x79 |
| MX6UL_PAD_LCD_DATA23__LCDIF_DATA23 0x79 |
| >; |
| }; |
| |
| pinctrl_pwm1: pwm1grp { |
| fsl,pins = < |
| MX6UL_PAD_GPIO1_IO08__PWM1_OUT 0x110b0 |
| >; |
| }; |
| |
| pinctrl_qspi: qspigrp { |
| fsl,pins = < |
| MX6UL_PAD_NAND_WP_B__QSPI_A_SCLK 0x70a1 |
| MX6UL_PAD_NAND_READY_B__QSPI_A_DATA00 0x70a1 |
| MX6UL_PAD_NAND_CE0_B__QSPI_A_DATA01 0x70a1 |
| MX6UL_PAD_NAND_CE1_B__QSPI_A_DATA02 0x70a1 |
| MX6UL_PAD_NAND_CLE__QSPI_A_DATA03 0x70a1 |
| MX6UL_PAD_NAND_DQS__QSPI_A_SS0_B 0x70a1 |
| >; |
| }; |
| |
| pinctrl_sai2: sai2grp { |
| fsl,pins = < |
| MX6UL_PAD_JTAG_TDI__SAI2_TX_BCLK 0x17088 |
| MX6UL_PAD_JTAG_TDO__SAI2_TX_SYNC 0x17088 |
| MX6UL_PAD_JTAG_TRST_B__SAI2_TX_DATA 0x11088 |
| MX6UL_PAD_JTAG_TCK__SAI2_RX_DATA 0x11088 |
| MX6UL_PAD_JTAG_TMS__SAI2_MCLK 0x17088 |
| MX6UL_PAD_SNVS_TAMPER4__GPIO5_IO04 0x17059 |
| >; |
| }; |
| |
| pinctrl_sim2_1: sim2grp-1 { |
| fsl,pins = < |
| MX6UL_PAD_CSI_DATA03__SIM2_PORT1_PD 0xb808 |
| MX6UL_PAD_CSI_DATA04__SIM2_PORT1_CLK 0x31 |
| MX6UL_PAD_CSI_DATA05__SIM2_PORT1_RST_B 0xb808 |
| MX6UL_PAD_CSI_DATA06__SIM2_PORT1_SVEN 0xb808 |
| MX6UL_PAD_CSI_DATA07__SIM2_PORT1_TRXD 0xb809 |
| MX6UL_PAD_CSI_DATA02__GPIO4_IO23 0x3008 |
| >; |
| }; |
| |
| pinctrl_spi4: spi4grp { |
| fsl,pins = < |
| MX6UL_PAD_BOOT_MODE0__GPIO5_IO10 0x70a1 |
| MX6UL_PAD_BOOT_MODE1__GPIO5_IO11 0x70a1 |
| MX6UL_PAD_SNVS_TAMPER7__GPIO5_IO07 0x70a1 |
| MX6UL_PAD_SNVS_TAMPER8__GPIO5_IO08 0x80000000 |
| >; |
| }; |
| |
| pinctrl_tsc: tscgrp { |
| fsl,pins = < |
| MX6UL_PAD_GPIO1_IO01__GPIO1_IO01 0xb0 |
| MX6UL_PAD_GPIO1_IO02__GPIO1_IO02 0xb0 |
| MX6UL_PAD_GPIO1_IO03__GPIO1_IO03 0xb0 |
| MX6UL_PAD_GPIO1_IO04__GPIO1_IO04 0xb0 |
| >; |
| }; |
| |
| pinctrl_uart1: uart1grp { |
| fsl,pins = < |
| MX6UL_PAD_UART1_TX_DATA__UART1_DCE_TX 0x1b0b1 |
| MX6UL_PAD_UART1_RX_DATA__UART1_DCE_RX 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_uart2: uart2grp { |
| fsl,pins = < |
| MX6UL_PAD_UART2_TX_DATA__UART2_DCE_TX 0x1b0b1 |
| MX6UL_PAD_UART2_RX_DATA__UART2_DCE_RX 0x1b0b1 |
| MX6UL_PAD_UART3_RX_DATA__UART2_DCE_RTS 0x1b0b1 |
| MX6UL_PAD_UART3_TX_DATA__UART2_DCE_CTS 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_uart2dte: uart2dtegrp { |
| fsl,pins = < |
| MX6UL_PAD_UART2_TX_DATA__UART2_DTE_RX 0x1b0b1 |
| MX6UL_PAD_UART2_RX_DATA__UART2_DTE_TX 0x1b0b1 |
| MX6UL_PAD_UART3_RX_DATA__UART2_DTE_CTS 0x1b0b1 |
| MX6UL_PAD_UART3_TX_DATA__UART2_DTE_RTS 0x1b0b1 |
| >; |
| }; |
| |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x17059 |
| MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x10059 |
| MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x17059 |
| MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x17059 |
| MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x17059 |
| MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x17059 |
| >; |
| }; |
| |
| pinctrl_usdhc1_100mhz: usdhc1grp100mhz { |
| fsl,pins = < |
| MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170b9 |
| MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100b9 |
| MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170b9 |
| MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170b9 |
| MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170b9 |
| MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170b9 |
| >; |
| }; |
| |
| pinctrl_usdhc1_200mhz: usdhc1grp200mhz { |
| fsl,pins = < |
| MX6UL_PAD_SD1_CMD__USDHC1_CMD 0x170f9 |
| MX6UL_PAD_SD1_CLK__USDHC1_CLK 0x100f9 |
| MX6UL_PAD_SD1_DATA0__USDHC1_DATA0 0x170f9 |
| MX6UL_PAD_SD1_DATA1__USDHC1_DATA1 0x170f9 |
| MX6UL_PAD_SD1_DATA2__USDHC1_DATA2 0x170f9 |
| MX6UL_PAD_SD1_DATA3__USDHC1_DATA3 0x170f9 |
| >; |
| }; |
| |
| pinctrl_usdhc2: usdhc2grp { |
| fsl,pins = < |
| MX6UL_PAD_NAND_RE_B__USDHC2_CLK 0x17059 |
| MX6UL_PAD_NAND_WE_B__USDHC2_CMD 0x17059 |
| MX6UL_PAD_NAND_DATA00__USDHC2_DATA0 0x17059 |
| MX6UL_PAD_NAND_DATA01__USDHC2_DATA1 0x17059 |
| MX6UL_PAD_NAND_DATA02__USDHC2_DATA2 0x17059 |
| MX6UL_PAD_NAND_DATA03__USDHC2_DATA3 0x17059 |
| >; |
| }; |
| |
| pinctrl_wdog: wdoggrp { |
| fsl,pins = < |
| MX6UL_PAD_LCD_RESET__WDOG1_WDOG_ANY 0x30b0 |
| >; |
| }; |
| }; |
| }; |
| |
| &lcdif { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lcdif_dat |
| &pinctrl_lcdif_ctrl>; |
| display = <&display0>; |
| status = "okay"; |
| |
| display0: display { |
| bits-per-pixel = <16>; |
| bus-width = <24>; |
| |
| display-timings { |
| native-mode = <&timing0>; |
| timing0: timing0 { |
| clock-frequency = <9200000>; |
| hactive = <480>; |
| vactive = <272>; |
| hfront-porch = <8>; |
| hback-porch = <4>; |
| hsync-len = <41>; |
| vback-porch = <2>; |
| vfront-porch = <4>; |
| vsync-len = <10>; |
| |
| hsync-active = <0>; |
| vsync-active = <0>; |
| de-active = <1>; |
| pixelclk-active = <0>; |
| }; |
| }; |
| }; |
| }; |
| |
| &pwm1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pwm1>; |
| status = "okay"; |
| }; |
| |
| &pxp { |
| status = "okay"; |
| }; |
| |
| &qspi { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_qspi>; |
| status = "okay"; |
| ddrsmp=<0>; |
| |
| flash0: n25q256a@0 { |
| #address-cells = <1>; |
| #size-cells = <1>; |
| compatible = "micron,n25q256a"; |
| spi-max-frequency = <29000000>; |
| spi-nor,ddr-quad-read-dummy = <6>; |
| reg = <0>; |
| }; |
| }; |
| |
| &sai2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sai2>; |
| |
| assigned-clocks = <&clks IMX6UL_CLK_SAI2_SEL>, |
| <&clks IMX6UL_CLK_SAI2>; |
| assigned-clock-parents = <&clks IMX6UL_CLK_PLL4_AUDIO_DIV>; |
| assigned-clock-rates = <0>, <12288000>; |
| |
| status = "okay"; |
| }; |
| |
| &sim2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_sim2_1>; |
| assigned-clocks = <&clks IMX6UL_CLK_SIM_SEL>; |
| assigned-clock-parents = <&clks IMX6UL_CLK_SIM_PODF>; |
| assigned-clock-rates = <240000000>; |
| pinctrl-assert-gpios = <&gpio4 23 GPIO_ACTIVE_LOW>; |
| port = <1>; |
| sven_low_active; |
| status = "okay"; |
| }; |
| |
| &tsc { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_tsc>; |
| xnur-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>; |
| measure_delay_time = <0xffff>; |
| pre_charge_time = <0xfff>; |
| status = "okay"; |
| }; |
| |
| &uart1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart1>; |
| status = "okay"; |
| }; |
| |
| &uart2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_uart2>; |
| fsl,uart-has-rtscts; |
| /* for DTE mode, add below change */ |
| /* fsl,dte-mode; */ |
| /* pinctrl-0 = <&pinctrl_uart2dte>; */ |
| status = "okay"; |
| }; |
| |
| &usbotg1 { |
| dr_mode = "otg"; |
| srp-disable; |
| hnp-disable; |
| adp-disable; |
| status = "okay"; |
| }; |
| |
| &usbotg2 { |
| dr_mode = "host"; |
| disable-over-current; |
| status = "okay"; |
| }; |
| |
| &usdhc1 { |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| pinctrl-1 = <&pinctrl_usdhc1_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc1_200mhz>; |
| cd-gpios = <&gpio1 19 GPIO_ACTIVE_LOW>; |
| keep-power-in-suspend; |
| enable-sdio-wakeup; |
| vmmc-supply = <®_sd1_vmmc>; |
| status = "okay"; |
| }; |
| |
| &usdhc2 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usdhc2>; |
| no-1-8-v; |
| non-removable; |
| keep-power-in-suspend; |
| enable-sdio-wakeup; |
| status = "okay"; |
| }; |
| |
| &wdog1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_wdog>; |
| fsl,ext-reset-output; |
| }; |
