| Device Tree Clock bindings for ZTE zx296718 |
| |
| This binding uses the common clock binding[1]. |
| |
| [1] Documentation/devicetree/bindings/clock/clock-bindings.txt |
| |
| Required properties: |
| - compatible : shall be one of the following: |
| "zte,zx296718-topcrm": |
| zx296718 top clock selection, divider and gating |
| |
| "zte,zx296718-lsp0crm" and |
| "zte,zx296718-lsp1crm": |
| zx296718 device level clock selection and gating |
| |
| - reg: Address and length of the register set |
| |
| The clock consumer should specify the desired clock by having the clock |
| ID in its "clocks" phandle cell. See include/dt-bindings/clock/zx296718-clock.h |
| for the full list of zx296718 clock IDs. |
| |
| |
| topclk: topcrm@1461000 { |
| compatible = "zte,zx296718-topcrm-clk"; |
| reg = <0x01461000 0x1000>; |
| #clock-cells = <1>; |
| }; |
| |
| usbphy0:usb-phy0 { |
| compatible = "zte,zx296718-usb-phy"; |
| #phy-cells = <0>; |
| clocks = <&topclk USB20_PHY_CLK>; |
| clock-names = "phyclk"; |
| status = "okay"; |
| }; |