| /* |
| * Copyright 2018-2019 NXP |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License |
| * as published by the Free Software Foundation; either version 2 |
| * of the License, or (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| /dts-v1/; |
| |
| /* |
| * At current stage, M41 is not ready to communicate with XEN, so we |
| * we need a way to tell XEN uboot is running or linux is running. |
| * XEN will check the contents of this area. |
| * So reserve a page at the beginning of GUEST_RAM0_BASE to avoid Linux |
| * touch this area. |
| */ |
| /memreserve/ 0x80000000 0x1000; |
| |
| #include <dt-bindings/interrupt-controller/arm-gic.h> |
| #include <dt-bindings/clock/imx8qm-clock.h> |
| #include <dt-bindings/input/input.h> |
| #include <dt-bindings/soc/imx_rsrc.h> |
| #include <dt-bindings/soc/imx8_hsio.h> |
| #include <dt-bindings/soc/imx8_pd.h> |
| #include <dt-bindings/pinctrl/pads-imx8qm.h> |
| #include <dt-bindings/gpio/gpio.h> |
| #include <dt-bindings/thermal/thermal.h> |
| |
| / { |
| model = "Freescale i.MX8QM DOMU"; |
| compatible = "fsl,imx8qm-mek", "fsl,imx8qm", "xen,xenvm-4.10", "xen,xenvm"; |
| interrupt-parent = <&gic>; |
| #address-cells = <0x2>; |
| #size-cells = <0x2>; |
| |
| /delete-node/ aliases; |
| |
| aliases { |
| mmc0 = &usdhc1; |
| dpu1 = &dpu2; |
| ldb1 = &ldb2; |
| serial1 = &lpuart1; |
| isi0 = &isi_0; |
| isi1 = &isi_1; |
| isi2 = &isi_2; |
| isi3 = &isi_3; |
| csi0 = &mipi_csi_0; |
| i2c1 = &i2c_rpbus_1; |
| }; |
| |
| cpus { |
| #address-cells = <0x2>; |
| #size-cells = <0x0>; |
| |
| cpu@0 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| enable-method = "psci"; |
| reg = <0x0 0x0>; |
| }; |
| |
| cpu@1 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| enable-method = "psci"; |
| reg = <0x0 0x1>; |
| }; |
| |
| cpu@2 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| enable-method = "psci"; |
| reg = <0x0 0x2>; |
| }; |
| |
| cpu@3 { |
| device_type = "cpu"; |
| compatible = "arm,armv8"; |
| enable-method = "psci"; |
| reg = <0x0 0x3>; |
| }; |
| }; |
| |
| psci { |
| compatible = "arm,psci-1.0"; |
| method = "hvc"; |
| }; |
| |
| memory@80000000 { |
| device_type = "memory"; |
| /* Will be updated by U-Boot or XEN TOOL */ |
| reg = <0x00000000 0x80000000 0 0x80000000>; |
| }; |
| |
| /* |
| * The reserved memory will be used when using U-Boot loading android |
| * image. For booting kernel using xl tool, pass args: |
| * cma=960M@2400M-3584M |
| * For the rpmsg_reserved area, need xl tool to create for non-android. |
| */ |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| passthrough; |
| |
| /* |
| * reserved-memory layout |
| * 0x8800_0000 ~ 0x8FFF_FFFF is reserved for M4 |
| * Shouldn't be used at A core and Linux side. |
| * |
| */ |
| |
| decoder_boot: decoder_boot@0x84000000 { |
| no-map; |
| reg = <0 0x84000000 0 0x2000000>; |
| }; |
| encoder_boot: encoder_boot@0x86000000 { |
| no-map; |
| reg = <0 0x86000000 0 0x400000>; |
| }; |
| /* |
| * CM40 rpmsg memory is still for Dom0, the domu.cfg |
| * not map 0x90000000 - 0x90100000 to DomU. |
| */ |
| rpmsg_reserved: rpmsg@0x90000000 { |
| no-map; |
| reg = <0 0x90000000 0 0x400000>; |
| }; |
| rpmsg_dma_reserved:rpmsg_dma@0x90400000 { |
| compatible = "shared-dma-pool"; |
| no-map; |
| reg = <0 0x90400000 0 0x1C00000>; |
| }; |
| decoder_rpc: decoder_rpc@0x92000000 { |
| no-map; |
| reg = <0 0x92000000 0 0x200000>; |
| }; |
| encoder_rpc: encoder_rpc@0x92200000 { |
| no-map; |
| reg = <0 0x92200000 0 0x200000>; |
| }; |
| dsp_reserved: dsp@0x92400000 { |
| no-map; |
| reg = <0 0x92400000 0 0x2000000>; |
| }; |
| encoder_reserved: encoder_reserved@0x94400000 { |
| no-map; |
| reg = <0 0x94400000 0 0x800000>; |
| }; |
| |
| /* global autoconfigured region for contiguous allocations */ |
| linux,cma { |
| compatible = "shared-dma-pool"; |
| reusable; |
| size = <0 0x3c000000>; |
| alloc-ranges = <0 0x96000000 0 0x3c000000>; |
| linux,cma-default; |
| }; |
| }; |
| |
| gic: interrupt-controller@3001000 { |
| compatible = "arm,gic-v3"; |
| #interrupt-cells = <3>; |
| #address-cells = <0x0>; |
| interrupt-controller; |
| redistributor-stride = <0x20000>; |
| #redistributor-regions = <0x1>; |
| reg = <0x0 0x3001000 0 0x10000>, /* GIC Dist */ |
| <0x0 0x3020000 0 0x1000000>; /* GICR */ |
| interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_HIGH)>; |
| interrupt-parent = <&gic>; |
| linux,phandle = <0xfde8>; |
| phandle = <0xfde8>; |
| }; |
| |
| timer { |
| compatible = "arm,armv8-timer"; |
| interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>, |
| <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; |
| interrupt-parent = <&gic>; |
| clock-frequency = <8000000>; |
| }; |
| |
| hypervisor { |
| compatible = "xen,xen-4.11", "xen,xen"; |
| reg = <0x0 0x38000000 0x0 0x1000000>; |
| interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(6) | IRQ_TYPE_LEVEL_LOW)>; |
| interrupt-parent = <&gic>; |
| }; |
| |
| clocks { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| clk0: clock@0 { |
| compatible = "fixed-clock"; |
| reg = <0>; |
| #clock-cells = <0>; |
| clock-frequency = <24000000>; |
| }; |
| }; |
| |
| rtc0: rtc@23000000 { |
| compatible = "arm,pl031", "arm,primecell"; |
| reg = <0x0 0x23000000 0x0 0x1000>; |
| interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>; |
| clocks = <&clk0>; |
| clock-names = "apb_pclk"; |
| }; |
| |
| lvds_backlight1: lvds_backlight@1 { |
| compatible = "pwm-backlight"; |
| pwms = <&lvds1_pwm 0 100000 0>; |
| |
| brightness-levels = < 0 1 2 3 4 5 6 7 8 9 |
| 10 11 12 13 14 15 16 17 18 19 |
| 20 21 22 23 24 25 26 27 28 29 |
| 30 31 32 33 34 35 36 37 38 39 |
| 40 41 42 43 44 45 46 47 48 49 |
| 50 51 52 53 54 55 56 57 58 59 |
| 60 61 62 63 64 65 66 67 68 69 |
| 70 71 72 73 74 75 76 77 78 79 |
| 80 81 82 83 84 85 86 87 88 89 |
| 90 91 92 93 94 95 96 97 98 99 |
| 100>; |
| default-brightness-level = <80>; |
| }; |
| |
| passthrough { |
| compatible = "simple-bus"; |
| ranges; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| firmware { |
| android { |
| compatible = "android,firmware"; |
| fstab { |
| compatible = "android,fstab"; |
| vendor { |
| compatible = "android,vendor"; |
| /* emmc node which used if androidboot.storage_type=emmc */ |
| dev_emmc = "/dev/block/platform/passthrough/5b010000.usdhc/by-name/vendor"; |
| type = "ext4"; |
| mnt_flags = "ro,barrier=1,inode_readahead_blks=8"; |
| fsmgr_flags = "wait,slotselect,avb"; |
| }; |
| }; |
| |
| vbmeta { |
| /*we need use FirstStageMountVBootV2 if we enable avb*/ |
| compatible = "android,vbmeta"; |
| /*parts means the partition witch can be mount in first stage*/ |
| parts = "vbmeta,boot,system,vendor"; |
| }; |
| }; |
| }; |
| |
| mu_m0: mu_m0@2d000000 { |
| compatible = "fsl,imx8-mu0-vpu-m0"; |
| reg = <0x0 0x2d000000 0x0 0x20000>; |
| interrupts = <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>; |
| fsl,vpu_ap_mu_id = <16>; |
| status = "okay"; |
| }; |
| |
| mu1_m0: mu1_m0@2d020000 { |
| compatible = "fsl,imx8-mu1-vpu-m0"; |
| reg = <0x0 0x2d020000 0x0 0x20000>; |
| interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; |
| fsl,vpu_ap_mu_id = <17>; |
| status = "okay"; |
| }; |
| mu2_m0: mu2_m0@2d040000 { |
| compatible = "fsl,imx8-mu2-vpu-m0"; |
| reg = <0x0 0x2d040000 0x0 0x20000>; |
| interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; |
| fsl,vpu_ap_mu_id = <18>; |
| status = "okay"; |
| }; |
| |
| mu13: mu13@5d280000 { |
| compatible = "fsl,imx8-mu-dsp"; |
| reg = <0x0 0x5d280000 0x0 0x10000>; |
| interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>; |
| fsl,dsp_ap_mu_id = <13>; |
| status = "okay"; |
| }; |
| |
| |
| vpu_decoder: vpu_decoder@2c000000 { |
| compatible = "nxp,imx8qm-b0-vpudec", "nxp,imx8qxp-b0-vpudec"; |
| boot-region = <&decoder_boot>; |
| rpc-region = <&decoder_rpc>; |
| reg = <0x0 0x2c000000 0x0 0x1000000>; |
| reg-names = "vpu_regs"; |
| reg-csr = <0x2d080000>; |
| power-domains = <&pd_vpu_dec>; |
| status = "disabled"; |
| }; |
| |
| vpu_encoder: vpu_encoder@2d000000 { |
| compatible = "nxp,imx8qm-b0-vpuenc"; |
| #address-cells = <1>; |
| #size-cells = <1>; |
| |
| boot-region = <&encoder_boot>; |
| rpc-region = <&encoder_rpc>; |
| reserved-region = <&encoder_reserved>; |
| reg = <0x0 0x2d000000 0x0 0x1000000>, /*VPU Encoder*/ |
| <0x0 0x2c000000 0x0 0x2000000>; /*VPU*/ |
| reg-names = "vpu_regs"; |
| power-domains = <&pd_vpu_enc>; |
| reg-rpc-system = <0x40000000>; |
| |
| resolution-max = <1920 1080>; |
| fps-max = <120>; |
| status = "disabled"; |
| |
| core0@1020000 { |
| compatible = "fsl,imx8-mu1-vpu-m0"; |
| reg = <0x1020000 0x20000>; |
| reg-csr = <0x1090000 0x10000>; |
| interrupts = <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>; |
| fsl,vpu_ap_mu_id = <17>; |
| fw-buf-size = <0x200000>; |
| rpc-buf-size = <0x80000>; |
| print-buf-size = <0x80000>; |
| }; |
| core1@1040000 { |
| compatible = "fsl,imx8-mu2-vpu-m0"; |
| reg = <0x1040000 0x20000>; |
| reg-csr = <0x10a0000 0x10000>; |
| interrupts = <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; |
| fsl,vpu_ap_mu_id = <18>; |
| fw-buf-size = <0x200000>; |
| rpc-buf-size = <0x80000>; |
| print-buf-size = <0x80000>; |
| }; |
| }; |
| |
| clk: clk { |
| compatible = "fsl,imx8qm-clk"; |
| #clock-cells = <1>; |
| fsl,lpcg_base_offset = <0x00000000 0x00000000>; |
| }; |
| |
| iomuxc: iomuxc { |
| compatible = "fsl,imx8qm-iomuxc"; |
| }; |
| |
| regulators { |
| compatible = "simple-bus"; |
| #address-cells = <1>; |
| #size-cells = <0>; |
| |
| epdev_on: fixedregulator@100 { |
| compatible = "regulator-fixed"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-name = "epdev_on"; |
| gpio = <&gpio4 9 0>; |
| enable-active-high; |
| }; |
| |
| reg_audio: fixedregulator@2 { |
| compatible = "regulator-fixed"; |
| reg = <2>; |
| regulator-name = "cs42888_supply"; |
| regulator-min-microvolt = <3300000>; |
| regulator-max-microvolt = <3300000>; |
| regulator-always-on; |
| }; |
| }; |
| |
| #include "fsl-imx8qm-device.dtsi" |
| |
| mu2: mu@5d1d0000 { |
| compatible = "fsl,imx8-mu"; |
| reg = <0x0 0x5d1d0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; |
| fsl,scu_ap_mu_id = <0>; |
| status = "okay"; |
| }; |
| |
| usb_lpcg { |
| reg = <0x0 0x5b270000 0x0 0x10000>; |
| }; |
| |
| edma01: dma-controller1@5a1f0000 { |
| compatible = "fsl,imx8qm-edma"; |
| reg = <0x0 0x5a2e0000 0x0 0x10000>, /* channel14 UART1 rx */ |
| <0x0 0x5a2f0000 0x0 0x10000>; /* channel15 UART1 tx */ |
| #dma-cells = <3>; |
| dma-channels = <2>; |
| interrupts = <GIC_SPI 436 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 437 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "edma0-chan14-rx", "edma0-chan15-tx"; |
| status = "okay"; |
| }; |
| |
| edma20: dma-controller@591f0000 { |
| compatible = "fsl,imx8qm-adma"; |
| reg = <0x0 0x59200000 0x0 0x10000>, /* asrc0 */ |
| <0x0 0x59210000 0x0 0x10000>, |
| <0x0 0x59220000 0x0 0x10000>, |
| <0x0 0x59230000 0x0 0x10000>, |
| <0x0 0x59240000 0x0 0x10000>, |
| <0x0 0x59250000 0x0 0x10000>; |
| #dma-cells = <3>; |
| shared-interrupt; |
| dma-channels = <6>; |
| interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, /* asrc0 */ |
| <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, |
| <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "edma2-chan0-rx", "edma2-chan1-rx", /* asrc0 */ |
| "edma2-chan2-rx", "edma2-chan3-tx", |
| "edma2-chan4-tx", "edma2-chan5-tx"; |
| status = "okay"; |
| }; |
| |
| edma21: dma-controller@0x59260000 { |
| compatible = "fsl,imx8qm-adma"; |
| reg = <0x0 0x59260000 0x0 0x10000>, /* esai0 rx */ |
| <0x0 0x59270000 0x0 0x10000>; /* esai0 tx */ |
| #dma-cells = <3>; |
| shared-interrupt; |
| dma-channels = <2>; |
| interrupts = <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, /* esai0 */ |
| <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "edma2-chan6-rx", "edma2-chan7-tx"; /* esai0 */ |
| status = "okay"; |
| }; |
| |
| edma24: dma-controller@0x592c0000 { |
| compatible = "fsl,imx8qm-adma"; |
| reg = <0x0 0x592c0000 0x0 0x10000>, /* sai0 rx */ |
| <0x0 0x592d0000 0x0 0x10000>; /* sai0 tx */ |
| #dma-cells = <3>; |
| shared-interrupt; |
| dma-channels = <2>; |
| interrupts = <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, /* sai0 */ |
| <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>; |
| interrupt-names = "edma2-chan12-rx", "edma2-chan13-tx"; /* sai0 */ |
| fsl,sc_rsrc_id = <SC_R_DMA_2_CH12>, |
| <SC_R_DMA_2_CH13>; |
| status = "okay"; |
| }; |
| |
| sound-cs42888 { |
| compatible = "fsl,imx8qm-sabreauto-cs42888", |
| "fsl,imx-audio-cs42888"; |
| model = "imx-cs42888"; |
| esai-controller = <&esai0>; |
| audio-codec = <&cs42888>; |
| asrc-controller = <&asrc0>; |
| status = "okay"; |
| }; |
| |
| xen_i2c0: xen_i2c@0 { |
| compatible = "xen,i2c"; |
| be-adapter = "5a800000.i2c"; |
| status = "okay"; |
| }; |
| |
| xen_i2c1: xen_i2c@1 { |
| compatible = "xen,i2c"; |
| be-adapter = "3b230000.i2c"; |
| status = "okay"; |
| }; |
| }; |
| |
| /* |
| * vehicle core driver device node which open power domain dc by default |
| */ |
| vehicle_core: vehicle_core { |
| compatible = "nxp,imx-vehicle"; |
| status = "disabled"; |
| }; |
| |
| /* |
| * vehicle M4 driver which can get info from MCU. |
| */ |
| vehicle_rpmsg_m4: vehicle_rpmsg_m4 { |
| compatible = "nxp,imx-vehicle-m4"; |
| status = "disabled"; |
| }; |
| }; |
| |
| /delete-node/ &tsens; |
| /delete-node/ &thermal_zones; |
| /delete-node/ &rtc; |
| |
| &display { |
| ports = <&dpu2_disp0>, <&dpu2_disp1>; |
| }; |
| |
| &dpu2_intsteer { |
| reg = <0x0 0x57000000 0x0 0x10000>; |
| status = "okay"; |
| }; |
| |
| &prg10 { |
| reg = <0x0 0x57040000 0x0 0x10000>; |
| status = "okay"; |
| }; |
| |
| &prg11 { |
| reg = <0x0 0x57050000 0x0 0x10000>; |
| status = "okay"; |
| }; |
| |
| &prg12 { |
| reg = <0x0 0x57060000 0x0 0x10000>; |
| status = "okay"; |
| }; |
| |
| &prg13 { |
| reg = <0x0 0x57070000 0x0 0x10000>; |
| status = "okay"; |
| }; |
| |
| &prg14 { |
| reg = <0x0 0x57080000 0x0 0x10000>; |
| status = "okay"; |
| }; |
| |
| &prg15 { |
| reg = <0x0 0x57090000 0x0 0x10000>; |
| status = "okay"; |
| }; |
| |
| &prg16 { |
| reg = <0x0 0x570a0000 0x0 0x10000>; |
| status = "okay"; |
| }; |
| |
| &prg17 { |
| reg = <0x0 0x570b0000 0x0 0x10000>; |
| status = "okay"; |
| }; |
| |
| &prg18 { |
| reg = <0x0 0x570c0000 0x0 0x10000>; |
| status = "okay"; |
| }; |
| |
| &dpr3_channel1 { |
| reg = <0x0 0x570d0000 0x0 0x10000>; |
| status = "okay"; |
| }; |
| |
| &dpr3_channel2 { |
| reg = <0x0 0x570e0000 0x0 0x10000>; |
| status = "okay"; |
| }; |
| |
| &dpr3_channel3 { |
| reg = <0x0 0x570f0000 0x0 0x10000>; |
| status = "okay"; |
| }; |
| |
| &dpr4_channel1 { |
| reg = <0x0 0x57100000 0x0 0x10000>; |
| status = "okay"; |
| }; |
| |
| &dpr4_channel2 { |
| reg = <0x0 0x57110000 0x0 0x10000>; |
| status = "okay"; |
| }; |
| |
| &dpr4_channel3 { |
| reg = <0x0 0x57120000 0x0 0x10000>; |
| status = "okay"; |
| }; |
| |
| &dpu2 { |
| reg = <0x0 0x57180000 0x0 0x40000>; |
| status = "okay"; |
| |
| dpu2_disp0: port@0 { |
| dpu2_disp0_mipi_dsi: mipi-dsi-endpoint { |
| /delete-property/ remote-endpoint; |
| }; |
| }; |
| dpu2_disp1: port@1 { |
| reg = <1>; |
| |
| dpu2_disp1_lvds0: lvds0-endpoint { |
| remote-endpoint = <&ldb2_lvds0>; |
| }; |
| |
| dpu2_disp1_lvds1: lvds1-endpoint { |
| remote-endpoint = <&ldb2_lvds1>; |
| }; |
| }; |
| }; |
| |
| &pixel_combiner2 { |
| status = "okay"; |
| }; |
| |
| /delete-node/ &hdmi; |
| /delete-node/ &hdmi_rx; |
| /delete-node/ &irqsteer_dsi0; |
| /delete-node/ &i2c0_mipi_dsi0; |
| /delete-node/ &mipi_dsi_csr1; |
| /delete-node/ &mipi_dsi_phy1; |
| /delete-node/ &mipi_dsi1; |
| /delete-node/ &mipi_dsi_bridge1; |
| |
| &lvds_region2 { |
| reg = <0x0 0x57240000 0x0 0x10000>; |
| status = "okay"; |
| }; |
| |
| &ldb2_phy { |
| reg = <0x0 0x57241000 0x0 0x100>; |
| status = "okay"; |
| }; |
| |
| &ldb2 { |
| status = "okay"; |
| |
| lvds-channel@0 { |
| fsl,data-mapping = "jeida"; |
| fsl,data-width = <24>; |
| status = "okay"; |
| |
| port@1 { |
| reg = <1>; |
| |
| lvds1_out: endpoint { |
| remote-endpoint = <&it6263_1_in>; |
| }; |
| }; |
| }; |
| }; |
| |
| /delete-node/ &lvds0_pwm; |
| /delete-node/ &dpu1_intsteer; |
| /delete-node/ &prg1; |
| /delete-node/ &prg2; |
| /delete-node/ &prg3; |
| /delete-node/ &prg4; |
| /delete-node/ &prg5; |
| /delete-node/ &prg6; |
| /delete-node/ &prg7; |
| /delete-node/ &prg8; |
| /delete-node/ &prg9; |
| /delete-node/ &dpr1_channel1; |
| /delete-node/ &dpr1_channel2; |
| /delete-node/ &dpr1_channel3; |
| /delete-node/ &dpr2_channel1; |
| /delete-node/ &dpr2_channel2; |
| /delete-node/ &dpr2_channel3; |
| /delete-node/ &dpu1; |
| /delete-node/ &pixel_combiner1; |
| |
| &dsp { |
| status = "okay"; |
| }; |
| |
| /delete-node/ &irqsteer_dsi1; |
| /delete-node/ &i2c0_mipi_dsi1; |
| /delete-node/ &mipi_dsi_csr2; |
| /delete-node/ &mipi_dsi_phy2; |
| /delete-node/ &mipi_dsi2; |
| /delete-node/ &mipi_dsi_bridge2; |
| /delete-node/ &lvds_region1; |
| /delete-node/ &ldb1_phy; |
| /delete-node/ &ldb1; |
| /*/delete-node/ &camera;*/ |
| /delete-node/ &adc0; |
| /delete-node/ &adc1; |
| /delete-node/ &i2c0; |
| /delete-node/ &i2c1; |
| /delete-node/ &i2c2; |
| /delete-node/ &i2c3; |
| /delete-node/ &i2c4; |
| /delete-node/ &i2c0_cm40; |
| /delete-node/ &i2c0_cm41; |
| /delete-node/ &irqsteer_hdmi; |
| /delete-node/ &irqsteer_hdmi_rx; |
| /delete-node/ &i2c0_hdmi; |
| |
| &irqsteer_lvds1 { |
| reg = <0x0 0x57240000 0x0 0x1000>; |
| /delete-property/ interrupt-parent; |
| status = "okay"; |
| }; |
| |
| /delete-node/ &flexcan1; |
| /delete-node/ &flexcan2; |
| /delete-node/ &flexcan3; |
| |
| &i2c1_lvds1 { |
| reg = <0x0 0x57247000 0x0 0x1000>; |
| status = "okay"; |
| }; |
| |
| /delete-node/ &irqsteer_lvds0; |
| /delete-node/ &i2c1_lvds0; |
| /*/delete-node/ &irqsteer_csi0;*/ |
| /*/delete-node/ &i2c0_mipi_csi0;*/ |
| /delete-node/ &irqsteer_csi1; |
| /delete-node/ &i2c0_mipi_csi1; |
| /delete-node/ &lpspi0; |
| /delete-node/ &lpspi3; |
| /delete-node/ &lpuart0; |
| |
| &lpuart1 { |
| /delete-property/ interrupt-parent; |
| reg = <0x0 0x5a070000 0 0x1000>; |
| dmas = <&edma01 15 0 0>, <&edma01 14 0 1>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lpuart1>; |
| status = "okay"; |
| }; |
| |
| /delete-node/ &lpuart2; |
| /delete-node/ &lpuart3; |
| /delete-node/ &lpuart4; |
| /delete-node/ &emvsim0; |
| /delete-node/ &edma0; |
| /delete-node/ &edma2; |
| /delete-node/ &edma3; |
| &gpio0 { |
| /delete-property/ power-domains; |
| status = "disabled"; |
| }; |
| &gpio1 { |
| /delete-property/ power-domains; |
| status = "okay"; |
| }; |
| &gpio2 { |
| /delete-property/ power-domains; |
| status = "disabled"; |
| }; |
| &gpio3 { |
| /delete-property/ power-domains; |
| status = "disabled"; |
| }; |
| &gpio4 { |
| /delete-property/ power-domains; |
| status = "okay"; |
| }; |
| &gpio5 { |
| /delete-property/ power-domains; |
| status = "disabled"; |
| }; |
| &gpio6 { |
| /delete-property/ power-domains; |
| status = "disabled"; |
| }; |
| &gpio7 { |
| /delete-property/ power-domains; |
| status = "disabled"; |
| }; |
| |
| /*/delete-node/ &gpio0_mipi_csi0;*/ |
| /delete-node/ &gpio0_mipi_csi1; |
| /delete-node/ &gpt0; |
| /delete-node/ &pwm0; |
| /delete-node/ &pwm1; |
| /delete-node/ &pwm2; |
| /delete-node/ &pwm3; |
| /delete-node/ &pwm4; |
| /delete-node/ &pwm5; |
| /delete-node/ &pwm6; |
| /delete-node/ &pwm7; |
| |
| &gpu_3d1 { |
| reg = <0x0 0x54100000 0 0x40000>; |
| status = "okay"; |
| }; |
| |
| /delete-node/ &gpu_3d0; |
| |
| &imx8_gpu_ss { |
| /* xen guests have 2GB of low RAM @ 2GB */ |
| reg = <0x0 0x80000000 0x0 0x80000000>, <0x0 0x0 0x0 0x10000000>; |
| reg-names = "phys_baseaddr", "contiguous_mem"; |
| cores = <&gpu_3d1>; |
| status = "okay"; |
| }; |
| |
| /delete-node/ &mlb; |
| |
| &usdhc1 { |
| compatible = "fsl,imx8qm-usdhc", "fsl,imx6sl-usdhc"; |
| /*interrupt-parent = <&gic>;*/ |
| /delete-property/ interrupt-parent; |
| reg = <0x0 0x5b010000 0x0 0x10000>; |
| }; |
| |
| /delete-node/ &usdhc2; |
| /delete-node/ &usdhc3; |
| /delete-node/ &fec1; |
| /delete-node/ &fec2; |
| |
| &usbmisc1 { |
| reg = <0x0 0x5b0d0200 0x0 0x200>; |
| }; |
| |
| &usbmisc2 { |
| status = "okay"; |
| }; |
| |
| &usbphy1 { |
| reg = <0x0 0x5b100000 0x0 0x200>; |
| }; |
| |
| /delete-node/ &usbh1; |
| |
| &usbotg3 { |
| /delete-property/ interrupt-parent; |
| dr_mode = "otg"; |
| extcon = <&typec_ptn5110>; |
| status = "okay"; |
| }; |
| |
| &usbphynop1 { |
| status = "okay"; |
| }; |
| |
| /delete-node/ &usbphynop2; |
| |
| &usbotg1 { |
| reg = <0x0 0x5b0d0000 0x0 0x200>; |
| /delete-property/ interrupt-parent; |
| }; |
| |
| /delete-node/ &ddr_pmu0; |
| /delete-node/ &ddr_pmu1; |
| /delete-node/ &vpu; |
| |
| &acm { |
| status = "okay"; |
| }; |
| |
| &esai0 { |
| compatible = "fsl,imx8qm-esai"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_esai0>; |
| dmas = <&edma21 6 0 1>, <&edma21 7 0 0>; |
| assigned-clocks = <&clk IMX8QM_ACM_ESAI0_MCLK_SEL>, |
| <&clk IMX8QM_AUD_PLL0_DIV>, |
| <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, |
| <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, |
| <&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>; |
| assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>; |
| assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>; |
| status = "okay"; |
| }; |
| |
| /delete-node/ &esai1; |
| /delete-node/ &spdif0; |
| /delete-node/ &spdif1; |
| /delete-node/ &sai1; |
| &sai0 { |
| dmas = <&edma24 12 0 1>, <&edma24 13 0 0>; |
| }; |
| /delete-node/ &sai2; |
| /delete-node/ &sai3; |
| /delete-node/ &sai_hdmi_rx; |
| /delete-node/ &sai_hdmi_tx; |
| /delete-node/ &sai6; |
| /delete-node/ &sai7; |
| /delete-node/ &amix; |
| |
| &asrc0 { |
| dmas = <&edma20 0 0 0>, <&edma20 1 0 0>, <&edma20 2 0 0>, |
| <&edma20 3 0 1>, <&edma20 4 0 1>, <&edma20 5 0 1>; |
| fsl,asrc-rate = <48000>; |
| status = "okay"; |
| }; |
| |
| /delete-node/ &asrc1; |
| /delete-node/ &mqs; |
| /delete-node/ &flexspi0; |
| |
| &dma_cap { |
| compatible = "dma-capability"; |
| only-dma-mask32 = <1>; |
| }; |
| |
| /delete-node/ &ocotp; |
| &pciea { |
| ext_osc = <1>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_pciea>; |
| disable-gpio = <&gpio1 13 GPIO_ACTIVE_LOW>; |
| reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; |
| clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>; |
| epdev_on-supply = <&epdev_on>; |
| status = "okay"; |
| }; |
| /delete-node/ &pcieb; |
| /delete-node/ &sata; |
| |
| /delete-node/ &intmux_cm40; |
| /delete-node/ &intmux_cm41; |
| |
| &rpmsg1{ |
| /* |
| * 64K for one rpmsg instance: |
| */ |
| vdev-nums = <2>; |
| reg = <0x0 0x90100000 0x0 0x20000>; |
| status = "okay"; |
| }; |
| |
| &mu_rpmsg1 { |
| reg = <0x0 0x5d210000 0x0 0x10000>; |
| }; |
| |
| /*/delete-node/ &crypto;*/ |
| /*/delete-node/ &caam_sm;*/ |
| /*/delete-node/ &sc_pwrkey;*/ |
| /delete-node/ &wdog; |
| /delete-node/ &wu; |
| |
| &iomuxc { |
| imx8qm-mek { |
| pinctrl_usdhc1: usdhc1grp { |
| fsl,pins = < |
| SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 |
| SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 |
| SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 |
| SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 |
| SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 |
| SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 |
| SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 |
| SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 |
| SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 |
| SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 |
| SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 |
| SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 |
| >; |
| }; |
| |
| pinctrl_usdhc1_100mhz: usdhc1grp100mhz { |
| fsl,pins = < |
| SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 |
| SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 |
| SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 |
| SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 |
| SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 |
| SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 |
| SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 |
| SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 |
| SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 |
| SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 |
| SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 |
| SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 |
| >; |
| }; |
| |
| pinctrl_usdhc1_200mhz: usdhc1grp200mhz { |
| fsl,pins = < |
| SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 |
| SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 |
| SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 |
| SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 |
| SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 |
| SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 |
| SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 |
| SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 |
| SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 |
| SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 |
| SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 |
| SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 |
| >; |
| }; |
| |
| pinctrl_usbotg1: usbotg1 { |
| fsl,pins = < |
| SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021 |
| >; |
| }; |
| |
| pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp { |
| fsl,pins = < |
| SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c |
| SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c |
| >; |
| }; |
| |
| pinctrl_lvds1_pwm0: lvds1pwm0grp { |
| fsl,pins = < |
| SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020 |
| >; |
| }; |
| |
| pinctrl_lpuart1: lpuart1grp { |
| fsl,pins = < |
| SC_P_UART1_RX_DMA_UART1_RX 0x06000020 |
| SC_P_UART1_TX_DMA_UART1_TX 0x06000020 |
| SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020 |
| SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020 |
| SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021 |
| >; |
| }; |
| |
| pinctrl_pciea: pcieagrp{ |
| fsl,pins = < |
| SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x06000021 |
| SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x04000021 |
| SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x06000021 |
| SC_P_LVDS1_I2C0_SDA_LSIO_GPIO1_IO13 0x06000000 |
| SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x06000021 |
| >; |
| }; |
| |
| pinctrl_typec: typecgrp { |
| fsl,pins = < |
| SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60 |
| SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60 |
| SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021 |
| >; |
| }; |
| |
| pinctrl_isl29023: isl29023grp { |
| fsl,pins = < |
| SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 |
| >; |
| }; |
| |
| pinctrl_esai0: esai0grp { |
| fsl,pins = < |
| SC_P_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040 |
| SC_P_ESAI0_FST_AUD_ESAI0_FST 0xc6000040 |
| SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040 |
| SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040 |
| SC_P_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040 |
| SC_P_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040 |
| SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040 |
| SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040 |
| SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040 |
| SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040 |
| >; |
| }; |
| }; |
| }; |
| |
| &usdhc1 { |
| /delete-property/ iommus; |
| pinctrl-names = "default", "state_100mhz", "state_200mhz"; |
| pinctrl-0 = <&pinctrl_usdhc1>; |
| pinctrl-1 = <&pinctrl_usdhc1_100mhz>; |
| pinctrl-2 = <&pinctrl_usdhc1_200mhz>; |
| bus-width = <8>; |
| non-removable; |
| status = "okay"; |
| }; |
| |
| &usbotg1 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_usbotg1>; |
| srp-disable; |
| hnp-disable; |
| adp-disable; |
| power-polarity-active-high; |
| disable-over-current; |
| status = "okay"; |
| }; |
| |
| &i2c1_lvds1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lvds1_lpi2c1>; |
| clock-frequency = <100000>; |
| status = "okay"; |
| |
| lvds-to-hdmi-bridge@4c { |
| compatible = "ite,it6263"; |
| reg = <0x4c>; |
| |
| port { |
| it6263_1_in: endpoint { |
| clock-lanes = <3>; |
| data-lanes = <0 1 2 4>; |
| remote-endpoint = <&lvds1_out>; |
| }; |
| }; |
| }; |
| }; |
| |
| &vpu_decoder { |
| core_type = <2>; |
| status = "okay"; |
| }; |
| |
| &vpu_encoder { |
| status = "okay"; |
| }; |
| |
| &xen_i2c0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-frequency = <100000>; |
| status = "okay"; |
| |
| isl29023@44 { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_isl29023>; |
| compatible = "fsl,isl29023"; |
| reg = <0x44>; |
| rext = <499>; |
| interrupt-parent = <&gpio4>; |
| interrupts = <11 2>; |
| }; |
| |
| fxos8700@1e { |
| compatible = "fsl,fxos8700"; |
| reg = <0x1e>; |
| interrupt-open-drain; |
| }; |
| |
| fxas2100x@20 { |
| compatible = "fsl,fxas2100x"; |
| reg = <0x20>; |
| interrupt-open-drain; |
| }; |
| |
| mpl3115@60 { |
| compatible = "fsl,mpl3115"; |
| reg = <0x60>; |
| interrupt-open-drain; |
| }; |
| |
| typec_ptn5110: typec@50 { |
| compatible = "usb,tcpci"; |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_typec>; |
| reg = <0x51>; |
| interrupt-parent = <&gpio4>; |
| interrupts = <26 IRQ_TYPE_LEVEL_LOW>; |
| ss-sel-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>; |
| reset-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>; |
| src-pdos = <0x380190c8 0x3803c0c8>; |
| port-type = "drp"; |
| sink-disable; |
| default-role = "source"; |
| status = "okay"; |
| }; |
| }; |
| |
| &xen_i2c1 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| clock-frequency = <100000>; |
| status = "okay"; |
| |
| cs42888: cs42888@48 { |
| compatible = "cirrus,cs42888"; |
| reg = <0x48>; |
| clocks = <&clk IMX8QM_AUD_MCLKOUT0>; |
| clock-names = "mclk"; |
| VA-supply = <®_audio>; |
| VD-supply = <®_audio>; |
| VLS-supply = <®_audio>; |
| VLC-supply = <®_audio>; |
| reset-gpio = <&gpio4 25 1>; |
| power-domains = <&pd_mclk_out0>; |
| assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>, |
| <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>, |
| <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>, |
| <&clk IMX8QM_AUD_MCLKOUT0>; |
| assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>; |
| status = "okay"; |
| }; |
| }; |
| |
| /* Camera */ |
| /delete-node/ &isi_4; |
| /delete-node/ &isi_5; |
| /delete-node/ &isi_6; |
| /delete-node/ &isi_7; |
| /delete-node/ &mipi_csi_1; |
| /delete-node/ &jpegdec; |
| /delete-node/ &jpegenc; |
| |
| &gpio0_mipi_csi0 { |
| status = "okay"; |
| }; |
| |
| &irqsteer_csi0 { |
| status = "okay"; |
| }; |
| |
| &isi_0 { |
| status = "okay"; |
| }; |
| |
| &isi_1 { |
| status = "okay"; |
| }; |
| |
| &isi_2 { |
| status = "okay"; |
| }; |
| |
| &isi_3 { |
| status = "okay"; |
| }; |
| |
| &mipi_csi_0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| virtual-channel; |
| status = "okay"; |
| |
| /* Camera 0 MIPI CSI-2 (CSIS0) */ |
| port@0 { |
| reg = <0>; |
| mipi_csi0_ep: endpoint { |
| remote-endpoint = <&max9286_0_ep>; |
| data-lanes = <1 2 3 4>; |
| }; |
| }; |
| }; |
| |
| &i2c0_mipi_csi0 { |
| #address-cells = <1>; |
| #size-cells = <0>; |
| pinctrl-names = "default"; |
| clock-frequency = <100000>; |
| status = "okay"; |
| |
| |
| max9286_mipi@6A { |
| compatible = "maxim,max9286_mipi"; |
| reg = <0x6A>; |
| clocks = <&clk IMX8QM_CLK_DUMMY>; |
| clock-names = "capture_mclk"; |
| mclk = <27000000>; |
| mclk_source = <0>; |
| pwn-gpios = <&gpio1 27 GPIO_ACTIVE_HIGH>; |
| virtual-channel; |
| port { |
| max9286_0_ep: endpoint { |
| remote-endpoint = <&mipi_csi0_ep>; |
| data-lanes = <1 2 3 4>; |
| }; |
| }; |
| }; |
| }; |
| |
| &lvds1_pwm { |
| pinctrl-names = "default"; |
| pinctrl-0 = <&pinctrl_lvds1_pwm0>; |
| status = "okay"; |
| }; |
