| /* |
| * Copyright 2018 NXP |
| * |
| * This program is free software; you can redistribute it and/or |
| * modify it under the terms of the GNU General Public License |
| * as published by the Free Software Foundation; either version 2 |
| * of the License, or (at your option) any later version. |
| * |
| * This program is distributed in the hope that it will be useful, |
| * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| * GNU General Public License for more details. |
| */ |
| |
| /dts-v1/; |
| |
| /memreserve/ 0x84000000 0x4000000; |
| /memreserve/ 0x90000000 0x400000; |
| /memreserve/ 0x90400000 0x2000000; |
| /memreserve/ 0x92400000 0x2000000; |
| /memreserve/ 0x94400000 0x1800000; |
| |
| #include "fsl-imx8qm-mek.dtsi" |
| #include "fsl-imx8qm-xen.dtsi" |
| |
| / { |
| model = "Freescale i.MX8QM MEK DOM0"; |
| compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; |
| |
| chosen { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| |
| /* Could be updated by U-Boot */ |
| module@0 { |
| bootargs = "earlycon=xen console=hvc0 loglevel=8 root=/dev/mmcblk1p2 rw rootwait"; |
| compatible = "xen,linux-zimage", "xen,multiboot-module"; |
| reg = <0x00000000 0x80a00000 0x00000000 0xf93a00>; |
| }; |
| }; |
| |
| domu { |
| /* |
| * There are 5 MUs, 0A is used by Dom0, 1A is used |
| * by ATF, so for DomU, 2A/3A/4A could be used. |
| * SC_R_MU_0A |
| * SC_R_MU_1A |
| * SC_R_MU_2A |
| * SC_R_MU_3A |
| * SC_R_MU_4A |
| * The rsrcs and pads will be configured by uboot scu_rm cmd |
| */ |
| #address-cells = <1>; |
| #size-cells = <0>; |
| doma { |
| compatible = "xen,domu"; |
| /* |
| * The name entry in VM configuration file |
| * needs to be same as here. |
| */ |
| domain_name = "DomU"; |
| /* |
| * The reg property will be updated by U-Boot to |
| * reflect the partition id. |
| */ |
| reg = <0>; |
| init_on_rsrcs = < |
| SC_R_MU_2A |
| >; |
| rsrcs = < |
| SC_R_MU_6A |
| SC_R_GPU_0_PID0 |
| SC_R_GPU_0_PID1 |
| SC_R_GPU_0_PID2 |
| SC_R_GPU_0_PID3 |
| SC_R_LVDS_0 |
| SC_R_LVDS_0_I2C_0 |
| SC_R_LVDS_0_PWM_0 |
| SC_R_DC_0 |
| SC_R_DC_0_BLIT0 |
| SC_R_DC_0_BLIT1 |
| SC_R_DC_0_BLIT2 |
| SC_R_DC_0_BLIT_OUT |
| SC_R_UNUSED9 |
| SC_R_UNUSED10 |
| SC_R_DC_0_WARP |
| SC_R_UNUSED11 |
| SC_R_UNUSED12 |
| SC_R_DC_0_VIDEO0 |
| SC_R_DC_0_VIDEO1 |
| SC_R_DC_0_FRAC0 |
| SC_R_UNUSED13 |
| SC_R_DC_0_PLL_0 |
| SC_R_DC_0_PLL_1 |
| SC_R_MIPI_0 |
| SC_R_MIPI_0_I2C_0 |
| SC_R_MIPI_0_I2C_1 |
| SC_R_MIPI_0_PWM_0 |
| SC_R_HDMI |
| SC_R_HDMI_PLL_0 |
| SC_R_HDMI_PLL_1 |
| SC_R_HDMI_I2C_0 |
| SC_R_HDMI_I2S |
| SC_R_HDMI_RX |
| SC_R_SDHC_0 |
| SC_R_USB_0 |
| SC_R_USB_0_PHY |
| SC_R_UART_1 |
| SC_R_DMA_0_CH14 |
| SC_R_DMA_0_CH15 |
| SC_R_MU_2A |
| /* pcie */ |
| SC_R_PCIE_B |
| SC_R_PCIE_A |
| SC_R_SERDES_0 |
| SC_R_HSIO_GPIO |
| /*vpu*/ |
| SC_R_VPU |
| SC_R_VPU_PID0 |
| SC_R_VPU_PID1 |
| SC_R_VPU_PID2 |
| SC_R_VPU_PID3 |
| SC_R_VPU_PID4 |
| SC_R_VPU_PID5 |
| SC_R_VPU_PID6 |
| SC_R_VPU_PID7 |
| SC_R_VPU_DEC_0 |
| SC_R_VPU_ENC_0 |
| SC_R_VPU_ENC_1 |
| SC_R_VPU_TS_0 |
| SC_R_VPU_MU_0 |
| SC_R_VPU_MU_1 |
| SC_R_VPU_MU_2 |
| SC_R_VPU_MU_3 |
| /* crypto */ |
| SC_R_CAAM_JR2 |
| SC_R_CAAM_JR2_OUT |
| SC_R_CAAM_JR3 |
| SC_R_CAAM_JR3_OUT |
| /* Camera */ |
| SC_R_ISI_CH0 |
| SC_R_ISI_CH1 |
| SC_R_ISI_CH2 |
| SC_R_ISI_CH3 |
| SC_R_MIPI_0 |
| SC_R_MIPI_0_PWM_0 |
| SC_R_MIPI_0_I2C_0 |
| SC_R_MIPI_0_I2C_1 |
| SC_R_CSI_0 |
| SC_R_CSI_0_PWM_0 |
| SC_R_CSI_0_I2C_0 |
| /* usbotg3 */ |
| SC_R_USB_2 |
| SC_R_USB_2_PHY |
| >; |
| pads = < |
| /* i2c1_lvds1 */ |
| SC_P_LVDS1_I2C1_SCL |
| SC_P_LVDS1_I2C1_SDA |
| /* emmc */ |
| SC_P_EMMC0_CLK |
| SC_P_EMMC0_CMD |
| SC_P_EMMC0_DATA0 |
| SC_P_EMMC0_DATA1 |
| SC_P_EMMC0_DATA2 |
| SC_P_EMMC0_DATA3 |
| SC_P_EMMC0_DATA4 |
| SC_P_EMMC0_DATA5 |
| SC_P_EMMC0_DATA6 |
| SC_P_EMMC0_DATA7 |
| SC_P_EMMC0_STROBE |
| SC_P_EMMC0_RESET_B |
| /* usb otg */ |
| SC_P_USB_SS3_TC0 |
| /* uart1 */ |
| SC_P_UART1_RX |
| SC_P_UART1_TX |
| SC_P_UART1_CTS_B |
| SC_P_UART1_RTS_B |
| SC_P_QSPI1A_DQS |
| /* pciea */ |
| SC_P_PCIE_CTRL0_CLKREQ_B |
| SC_P_PCIE_CTRL0_WAKE_B |
| SC_P_PCIE_CTRL0_PERST_B |
| SC_P_LVDS1_I2C0_SDA |
| SC_P_USDHC2_RESET_B |
| /*usbotgs typec */ |
| SC_P_QSPI1A_SS0_B |
| SC_P_USB_SS3_TC3 |
| SC_P_QSPI1A_DATA0 |
| /* isl29023 */ |
| SC_P_USDHC2_WP |
| |
| >; |
| gpios = <&gpio1 13 GPIO_ACTIVE_LOW>, |
| <&gpio1 27 GPIO_ACTIVE_LOW>, |
| <&gpio4 6 GPIO_ACTIVE_LOW>, |
| <&gpio4 9 GPIO_ACTIVE_LOW>, |
| <&gpio4 11 GPIO_ACTIVE_HIGH>, |
| <&gpio4 19 GPIO_ACTIVE_HIGH>, |
| <&gpio4 26 GPIO_ACTIVE_HIGH>, |
| <&gpio4 27 GPIO_ACTIVE_LOW>, |
| <&gpio4 29 GPIO_ACTIVE_LOW>; |
| }; |
| }; |
| |
| reserved-memory { |
| /* global autoconfigured region for contiguous allocations */ |
| linux,cma { |
| compatible = "shared-dma-pool"; |
| reusable; |
| size = <0 0x28000000>; |
| alloc-ranges = <0 0xa0000000 0 0x40000000>; |
| linux,cma-default; |
| }; |
| }; |
| |
| display-subsystem { |
| compatible = "fsl,imx-display-subsystem"; |
| ports = <&dpu2_disp0>, <&dpu2_disp1>; |
| }; |
| |
| /* Passthrough to domu */ |
| mu2: mu@5d1d0000 { |
| compatible = "fsl,imx8-mu"; |
| reg = <0x0 0x5d1d0000 0x0 0x10000>; |
| interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; |
| fsl,scu_ap_mu_id = <0>; |
| xen,passthrough; |
| status = "disabled"; |
| }; |
| |
| cm41: cm41@1 { |
| fsl,sc_rsrc_id = <SC_R_M4_1_PID0>, |
| <SC_R_M4_1_PID1>, |
| <SC_R_M4_1_PID2>, |
| <SC_R_M4_1_PID3>, |
| <SC_R_M4_1_PID4>; |
| #stream-id-cells = <1>; |
| iommus = <&smmu>; |
| xen,passthrough; |
| }; |
| |
| irqsteer_cm41: irqsteer_cm41@0x51080000 { |
| reg = <0x0 0x51080000 0x0 0x10000>; |
| xen,passthrough; |
| }; |
| |
| mu_rpmsg1_b: mu_rpmsg1_b@0x5d2a0000 { |
| reg = <0x0 0x5d2a0000 0x0 0x10000>; |
| xen,passthrough; |
| }; |
| |
| decoder_boot_mem: decoder_boot_mem@0x84000000 { |
| xen,passthrough; |
| reg = <0 0x84000000 0 0x2000000>; |
| }; |
| |
| encoder_boot_mem: encoder_boot_mem@0x86000000 { |
| xen,passthrough; |
| reg = <0 0x86000000 0 0x2000000>; |
| }; |
| |
| rpmsg_reserved_mem: rpmsg_reserved_mem@90000000 { |
| reg = <0x0 0x90000000 0x0 0x400000>; |
| xen,passthrough; |
| }; |
| |
| decoder_rpc_mem: decoder_rpc_mem@0x90400000 { |
| xen,passthrough; |
| reg = <0 0x90400000 0 0x1000000>; |
| }; |
| |
| encoder_rpc_mem: encoder_rpc_mem@0x91400000 { |
| xen,passthrough; |
| reg = <0 0x91400000 0 0x1000000>; |
| }; |
| encoder_reserved_mem: encoder_reserved_mem@0x94400000 { |
| xen,passthrough; |
| reg = <0 0x94400000 0 0x800000>; |
| }; |
| |
| decoder_str_mem: str_mem@0x94400000 { |
| xen,passthrough; |
| reg = <0 0x94400000 0 0x1800000>; |
| }; |
| |
| gpio4_dummy: gpio4_dummy@0{ |
| /* Passthrough gpio4 interrupt to DomU */ |
| interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; |
| xen,passthrough; |
| }; |
| }; |
| |
| &mu_rpmsg1 { |
| xen,passthrough; |
| }; |
| |
| &rpmsg1 { |
| /* Let xen not create mapping form dom0 */ |
| /delete-property/ reg; |
| status = "disabled"; |
| }; |
| |
| &mu_6_lpcg { |
| xen,passthrough; |
| }; |
| |
| &mu_6_lpcg_b { |
| xen,passthrough; |
| }; |
| |
| &mu_7_lpcg_b { |
| xen,passthrough; |
| }; |
| |
| &usbotg1_lpcg { |
| xen,passthrough; |
| }; |
| |
| &sdhc1_lpcg { |
| xen,passthrough; |
| }; |
| |
| &lpuart1 { |
| xen,passthrough; |
| }; |
| |
| &lpuart1_lpcg { |
| xen,passthrough; |
| }; |
| |
| /* |
| * DomU CM41 use this, but DomU OS not need this, |
| * because smmu is enabled for CM41, so need to |
| *create the lpuart2 mapping in SMMU |
| */ |
| &lpuart2 { |
| xen,passthrough; |
| }; |
| |
| &lpuart2_lpcg { |
| xen,passthrough; |
| }; |
| |
| &di_lvds0_lpcg { |
| xen,passthrough; |
| }; |
| |
| &dc_0_lpcg { |
| xen,passthrough; |
| }; |
| |
| &edma01 { |
| #stream-id-cells = <1>; |
| xen,passthrough; |
| fsl,sc_rsrc_id = <SC_R_DMA_0_CH14>, |
| <SC_R_DMA_0_CH15>; |
| }; |
| |
| /* |
| * SMMU, for simplity, we put all all the resources needs to programmed |
| * for VPU under vpu_decoder node, then in cfg file only add vpu_decoder |
| * in dt_dev is enough. |
| */ |
| &smmu { |
| mmu-masters = <&dpu1 0x13>, <&gpu_3d0 0x15>, |
| <&usdhc1 0x12>, <&usbotg1 0x11>, |
| <&edma01 0x10>, <&cm41 0x09>, <&pciea 0x08>, |
| <&vpu_decoder 0x7>, <&crypto 0x6>, <&isi_0 0x5>, |
| <&usbotg3 0x4>, <&hdmi 0x3>; |
| }; |
| |
| &lvds_region1 { |
| xen,passthrough; |
| }; |
| |
| &irqsteer_lvds0 { |
| xen,passthrough; |
| }; |
| |
| &i2c1_lvds0 { |
| xen,passthrough; |
| }; |
| |
| &ldb1_phy { |
| xen,passthrough; |
| }; |
| |
| &ldb1 { |
| xen,passthrough; |
| }; |
| |
| &dpu1_intsteer { |
| xen,passthrough; |
| }; |
| |
| &dpu1 { |
| xen,passthrough; |
| #stream-id-cells = <1>; |
| iommus = <&smmu>; |
| }; |
| |
| &pixel_combiner1 { |
| xen,passthrough; |
| }; |
| |
| &prg1 { |
| xen,passthrough; |
| }; |
| |
| &prg2 { |
| xen,passthrough; |
| }; |
| |
| &prg3 { |
| xen,passthrough; |
| }; |
| |
| &prg4 { |
| xen,passthrough; |
| }; |
| |
| &prg5 { |
| xen,passthrough; |
| }; |
| |
| &prg6 { |
| xen,passthrough; |
| }; |
| |
| &prg7 { |
| xen,passthrough; |
| }; |
| |
| &prg8 { |
| xen,passthrough; |
| }; |
| |
| &prg9 { |
| xen,passthrough; |
| }; |
| |
| &dpr1_channel1 { |
| xen,passthrough; |
| }; |
| |
| &dpr1_channel2 { |
| xen,passthrough; |
| }; |
| |
| &dpr1_channel3 { |
| xen,passthrough; |
| }; |
| |
| &dpr2_channel1 { |
| xen,passthrough; |
| }; |
| |
| &dpr2_channel2 { |
| xen,passthrough; |
| }; |
| |
| &dpr2_channel3 { |
| xen,passthrough; |
| }; |
| |
| /* GPU */ |
| &pd_gpu0 { |
| xen,passthrough; |
| }; |
| |
| &gpu_3d0 { |
| xen,passthrough; |
| #stream-id-cells = <1>; |
| iommus = <&smmu>; |
| }; |
| |
| &imx8_gpu_ss { |
| cores = <&gpu_3d1>; |
| /delete-property/ reg; |
| /delete-property/ reg-names; |
| }; |
| |
| &sata { |
| status = "disabled"; |
| }; |
| |
| &usdhc1 { |
| xen,passthrough; |
| #stream-id-cells = <1>; |
| iommus = <&smmu>; |
| }; |
| |
| &usbotg1 { |
| /* Hack reg */ |
| reg = <0x0 0x5b0d0000 0x0 0x1000>; |
| xen,passthrough; |
| #stream-id-cells = <1>; |
| iommus = <&smmu>; |
| }; |
| |
| &usbmisc1 { |
| /* Hack */ |
| /delete-property/ reg; |
| status = "disabled"; |
| }; |
| |
| &usbphy1 { |
| reg = <0x0 0x5b100000 0x0 0x1000>; |
| xen,passthrough; |
| }; |
| |
| &hsio { |
| xen,passthrough; |
| }; |
| |
| &hsio_pcie_x2_lpcg { |
| xen,passthrough; |
| }; |
| |
| &hsio_phy_x2_lpcg { |
| xen,passthrough; |
| }; |
| |
| &hsio_pcie_x2_crr2_lpcg { |
| xen,passthrough; |
| }; |
| |
| &hsio_pcie_x1_lpcg { |
| xen,passthrough; |
| }; |
| |
| &pciea { |
| #stream-id-cells = <1>; |
| iommus = <&smmu>; |
| xen,passthrough; |
| fsl,sc_rsrc_id = <SC_R_PCIE_A>; |
| }; |
| |
| &pcieb { |
| xen,passthrough; |
| }; |
| |
| &gpio1 { |
| xen,shared; |
| }; |
| |
| &gpt0 { |
| /delete-property/ interrupts; |
| status = "disabled"; |
| }; |
| |
| &gpio4 { |
| /* |
| * Use GPT0 interrupt for hack |
| * This could be removed when interrupt sharing be supported. |
| */ |
| interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; |
| xen,domu-irq; |
| xen,shared; |
| }; |
| |
| &dsp { |
| xen,passthrough; |
| }; |
| |
| &mu_m0 { |
| xen,passthrough; |
| }; |
| |
| &mu1_m0 { |
| xen,passthrough; |
| }; |
| |
| &mu2_m0 { |
| xen,passthrough; |
| }; |
| |
| &vpu_decoder { |
| #stream-id-cells = <1>; |
| iommus = <&smmu>; |
| xen,passthrough; |
| fsl,sc_rsrc_id = <SC_R_VPU>, |
| <SC_R_VPU_PID0>, |
| <SC_R_VPU_PID1>, |
| <SC_R_VPU_PID2>, |
| <SC_R_VPU_PID3>, |
| <SC_R_VPU_PID4>, |
| <SC_R_VPU_PID5>, |
| <SC_R_VPU_PID6>, |
| <SC_R_VPU_PID7>, |
| <SC_R_VPU_DEC_0>, |
| <SC_R_VPU_ENC_0>, |
| <SC_R_VPU_ENC_1>, |
| <SC_R_VPU_TS_0>, |
| <SC_R_VPU_MU_0>, |
| <SC_R_VPU_MU_1>, |
| <SC_R_VPU_MU_2>, |
| <SC_R_VPU_MU_3>; |
| }; |
| |
| &vpu_decoder_csr { |
| xen,passthrough; |
| }; |
| |
| &vpu_encoder { |
| iommus = <&smmu>; |
| #stream-id-cells = <1>; |
| xen,passthrough; |
| }; |
| |
| &crypto { |
| xen,passthrough; |
| iommus = <&smmu>; |
| #stream-id-cells = <1>; |
| /* JR1 is not used by Linux */ |
| fsl,sc_rsrc_id = <SC_R_CAAM_JR2>, <SC_R_CAAM_JR2_OUT>, |
| <SC_R_CAAM_JR3>, <SC_R_CAAM_JR3_OUT>; |
| }; |
| |
| &sec_jr2 { |
| xen,passthrough; |
| }; |
| |
| &sec_jr3 { |
| xen,passthrough; |
| }; |
| |
| &caam_sm { |
| xen,passthrough; |
| }; |
| |
| &i2c0 { |
| isl29023@44 { |
| xen,passthrough; |
| }; |
| |
| fxos8700@1e { |
| xen,passthrough; |
| }; |
| |
| fxas2100x@20 { |
| xen,passthrough; |
| }; |
| |
| mpl3115@60 { |
| xen,passthrough; |
| }; |
| |
| typec_ptn5110: typec@50 { |
| xen,passthrough; |
| }; |
| }; |
| |
| /* Camera */ |
| &img_pdma_0_lpcg { |
| xen,passthrough; |
| }; |
| |
| &img_pdma_1_lpcg { |
| xen,passthrough; |
| }; |
| |
| &img_pdma_2_lpcg { |
| xen,passthrough; |
| }; |
| |
| &img_pdma_3_lpcg { |
| xen,passthrough; |
| }; |
| |
| &mipi_csi_0_lpcg { |
| xen,passthrough; |
| }; |
| |
| &img_pxl_link_csi0_lpcg { |
| xen,passthrough; |
| }; |
| |
| &gpio0_mipi_csi0 { |
| xen,passthrough; |
| }; |
| |
| &irqsteer_csi0 { |
| xen,passthrough; |
| }; |
| |
| &isi_0 { |
| xen,passthrough; |
| #stream-id-cells = <1>; |
| iommus = <&smmu>; |
| fsl,sc_rsrc_id = <SC_R_ISI_CH0>, |
| <SC_R_ISI_CH1>, |
| <SC_R_ISI_CH2>, |
| <SC_R_ISI_CH3>; |
| }; |
| |
| &isi_1 { |
| xen,passthrough; |
| }; |
| |
| &isi_2 { |
| xen,passthrough; |
| }; |
| |
| &isi_3 { |
| xen,passthrough; |
| }; |
| |
| &mipi_csi_0 { |
| xen,passthrough; |
| }; |
| |
| &i2c0_mipi_csi0 { |
| xen,passthrough; |
| }; |
| |
| &isi_4 { |
| status = "okay"; |
| }; |
| |
| &isi_5 { |
| status = "okay"; |
| }; |
| |
| &isi_6 { |
| status = "okay"; |
| }; |
| |
| &isi_7 { |
| status = "okay"; |
| }; |
| |
| &mipi_csi_1 { |
| status = "okay"; |
| }; |
| |
| &i2c0_mipi_csi1 { |
| status = "okay"; |
| }; |
| |
| &usbotg3_lpcg { |
| xen,passthrough; |
| }; |
| |
| &usbotg3 { |
| xen,passthrough; |
| #stream-id-cells = <1>; |
| iommus = <&smmu>; |
| }; |
| |
| /* hdmi */ |
| &hdmi { |
| xen,passthrough; |
| #stream-id-cells = <1>; |
| iommus = <&smmu>; |
| fsl,sc_rsrc_id = <SC_R_HDMI>, |
| <SC_R_HDMI_RX>; |
| }; |
| |
| &hdmi_rx { |
| xen,passthrough; |
| }; |
| |
| &irqsteer_hdmi { |
| xen,passthrough; |
| }; |
| |
| &irqsteer_hdmi_rx { |
| xen,passthrough; |
| }; |
| |
| &i2c0_hdmi { |
| xen,passthrough; |
| }; |
| |
| &sai_hdmi_rx { |
| xen,passthrough; |
| }; |
| |
| &sai_hdmi_tx { |
| xen,passthrough; |
| }; |
