| /* |
| * Cyrus 5020 Device Tree Source, based on p5020ds.dts |
| * |
| * Copyright 2015 Andy Fleming |
| * |
| * p5020ds.dts copyright: |
| * Copyright 2010 - 2014 Freescale Semiconductor Inc. |
| * |
| * This program is free software; you can redistribute it and/or modify it |
| * under the terms of the GNU General Public License as published by the |
| * Free Software Foundation; either version 2 of the License, or (at your |
| * option) any later version. |
| */ |
| |
| /include/ "p5020si-pre.dtsi" |
| |
| / { |
| model = "varisys,CYRUS"; |
| compatible = "varisys,CYRUS"; |
| #address-cells = <2>; |
| #size-cells = <2>; |
| interrupt-parent = <&mpic>; |
| |
| memory { |
| device_type = "memory"; |
| }; |
| |
| reserved-memory { |
| #address-cells = <2>; |
| #size-cells = <2>; |
| ranges; |
| |
| bman_fbpr: bman-fbpr { |
| size = <0 0x1000000>; |
| alignment = <0 0x1000000>; |
| }; |
| qman_fqd: qman-fqd { |
| size = <0 0x400000>; |
| alignment = <0 0x400000>; |
| }; |
| qman_pfdr: qman-pfdr { |
| size = <0 0x2000000>; |
| alignment = <0 0x2000000>; |
| }; |
| }; |
| |
| dcsr: dcsr@f00000000 { |
| ranges = <0x00000000 0xf 0x00000000 0x01008000>; |
| }; |
| |
| bportals: bman-portals@ff4000000 { |
| ranges = <0x0 0xf 0xf4000000 0x200000>; |
| }; |
| |
| qportals: qman-portals@ff4200000 { |
| ranges = <0x0 0xf 0xf4200000 0x200000>; |
| }; |
| |
| soc: soc@ffe000000 { |
| ranges = <0x00000000 0xf 0xfe000000 0x1000000>; |
| reg = <0xf 0xfe000000 0 0x00001000>; |
| spi@110000 { |
| }; |
| |
| i2c@118100 { |
| }; |
| |
| i2c@119100 { |
| rtc@6f { |
| compatible = "microchip,mcp7941x"; |
| reg = <0x6f>; |
| }; |
| }; |
| }; |
| |
| rio: rapidio@ffe0c0000 { |
| reg = <0xf 0xfe0c0000 0 0x11000>; |
| |
| port1 { |
| ranges = <0 0 0xc 0x20000000 0 0x10000000>; |
| }; |
| port2 { |
| ranges = <0 0 0xc 0x30000000 0 0x10000000>; |
| }; |
| }; |
| |
| lbc: localbus@ffe124000 { |
| reg = <0xf 0xfe124000 0 0x1000>; |
| ranges = <0 0 0xf 0xe8000000 0x08000000 |
| 2 0 0xf 0xffa00000 0x00040000 |
| 3 0 0xf 0xffdf0000 0x00008000>; |
| }; |
| |
| pci0: pcie@ffe200000 { |
| reg = <0xf 0xfe200000 0 0x1000>; |
| ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 |
| 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; |
| pcie@0 { |
| ranges = <0x02000000 0 0xe0000000 |
| 0x02000000 0 0xe0000000 |
| 0 0x20000000 |
| |
| 0x01000000 0 0x00000000 |
| 0x01000000 0 0x00000000 |
| 0 0x00010000>; |
| }; |
| }; |
| |
| pci1: pcie@ffe201000 { |
| reg = <0xf 0xfe201000 0 0x1000>; |
| ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 |
| 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; |
| pcie@0 { |
| ranges = <0x02000000 0 0xe0000000 |
| 0x02000000 0 0xe0000000 |
| 0 0x20000000 |
| |
| 0x01000000 0 0x00000000 |
| 0x01000000 0 0x00000000 |
| 0 0x00010000>; |
| }; |
| }; |
| |
| pci2: pcie@ffe202000 { |
| reg = <0xf 0xfe202000 0 0x1000>; |
| ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 |
| 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; |
| pcie@0 { |
| ranges = <0x02000000 0 0xe0000000 |
| 0x02000000 0 0xe0000000 |
| 0 0x20000000 |
| |
| 0x01000000 0 0x00000000 |
| 0x01000000 0 0x00000000 |
| 0 0x00010000>; |
| }; |
| }; |
| |
| pci3: pcie@ffe203000 { |
| reg = <0xf 0xfe203000 0 0x1000>; |
| ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 |
| 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; |
| pcie@0 { |
| ranges = <0x02000000 0 0xe0000000 |
| 0x02000000 0 0xe0000000 |
| 0 0x20000000 |
| |
| 0x01000000 0 0x00000000 |
| 0x01000000 0 0x00000000 |
| 0 0x00010000>; |
| }; |
| }; |
| }; |
| |
| /include/ "p5020si-post.dtsi" |
