blob: c3c1edc3bd0e2b82d191462b4e0e13658bac66a1 [file] [log] [blame]
/*
* Copyright 2017 NXP
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version 2
* of the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
#include "fsl-imx8qm.dtsi"
/ {
model = "Freescale i.MX8QM MEK";
compatible = "fsl,imx8qm-mek", "fsl,imx8qm";
chosen {
bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
stdout-path = &lpuart0;
};
modem_reset: modem-reset {
compatible = "gpio-reset";
reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>;
reset-delay-us = <2000>;
reset-post-delay-ms = <40>;
#reset-cells = <0>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_can01_en: regulator-can01-gen {
compatible = "regulator-fixed";
regulator-name = "can01-en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416 3 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_can2_en: regulator-can2-gen {
compatible = "regulator-fixed";
regulator-name = "can2-en";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416 4 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_can01_stby: regulator-can01-stby {
compatible = "regulator-fixed";
regulator-name = "can01-stby";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416 5 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_can01_en>;
};
reg_can2_stby: regulator-can2-stby {
compatible = "regulator-fixed";
regulator-name = "can2-stby";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&pca6416 6 GPIO_ACTIVE_HIGH>;
enable-active-high;
vin-supply = <&reg_can2_en>;
};
reg_fec2_supply: fec2_nvcc {
compatible = "regulator-fixed";
regulator-name = "fec2_nvcc";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
gpio = <&max7322 0 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
epdev_on: fixedregulator@100 {
compatible = "regulator-fixed";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-name = "epdev_on";
gpio = <&gpio4 9 0>;
enable-active-high;
};
reg_usdhc2_vmmc: usdhc2_vmmc {
compatible = "regulator-fixed";
regulator-name = "sw-3p3-sd1";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
off-on-delay = <4800>;
enable-active-high;
};
reg_audio: fixedregulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "cs42888_supply";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
sound: sound {
compatible = "fsl,imx7d-evk-wm8960",
"fsl,imx-audio-wm8960";
model = "wm8960-audio";
cpu-dai = <&sai1>;
audio-codec = <&wm8960>;
asrc-controller = <&asrc0>;
codec-master;
/*
* hp-det = <hp-det-pin hp-det-polarity>;
* hp-det-pin: JD1 JD2 or JD3
* hp-det-polarity = 0: hp detect high for headphone
* hp-det-polarity = 1: hp detect high for speaker
*/
hp-det = <2 0>;
audio-routing =
"Headphone Jack", "HP_L",
"Headphone Jack", "HP_R",
"Ext Spk", "SPK_LP",
"Ext Spk", "SPK_LN",
"Ext Spk", "SPK_RP",
"Ext Spk", "SPK_RN",
"LINPUT2", "Mic Jack",
"LINPUT3", "Mic Jack",
"RINPUT1", "Main MIC",
"RINPUT2", "Main MIC",
"Mic Jack", "MICB",
"Main MIC", "MICB",
"CPU-Playback", "ASRC-Playback",
"Playback", "CPU-Playback",
"ASRC-Capture", "CPU-Capture",
"CPU-Capture", "Capture";
};
sound-cs42888 {
compatible = "fsl,imx8qm-sabreauto-cs42888",
"fsl,imx-audio-cs42888";
model = "imx-cs42888";
esai-controller = <&esai0>;
audio-codec = <&cs42888>;
status = "okay";
};
sound-amix-sai {
compatible = "fsl,imx-audio-amix";
model = "amix-audio-sai";
dais = <&sai6>, <&sai7>;
amix-controller = <&amix>;
};
lvds_backlight0: lvds_backlight@0 {
compatible = "pwm-backlight";
pwms = <&lvds0_pwm 0 100000 0>;
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <80>;
};
lvds_backlight1: lvds_backlight@1 {
compatible = "pwm-backlight";
pwms = <&lvds1_pwm 0 100000 0>;
brightness-levels = < 0 1 2 3 4 5 6 7 8 9
10 11 12 13 14 15 16 17 18 19
20 21 22 23 24 25 26 27 28 29
30 31 32 33 34 35 36 37 38 39
40 41 42 43 44 45 46 47 48 49
50 51 52 53 54 55 56 57 58 59
60 61 62 63 64 65 66 67 68 69
70 71 72 73 74 75 76 77 78 79
80 81 82 83 84 85 86 87 88 89
90 91 92 93 94 95 96 97 98 99
100>;
default-brightness-level = <80>;
};
};
&acm {
status = "okay";
};
&amix {
status = "okay";
};
&sai6 {
assigned-clocks = <&clk IMX8QM_ACM_SAI6_MCLK_SEL>,
<&clk IMX8QM_AUD_PLL1_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>,
<&clk IMX8QM_AUD_SAI_6_MCLK>;
assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>;
assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
fsl,sai-asynchronous;
fsl,txm-rxs;
status = "okay";
};
&sai7 {
assigned-clocks = <&clk IMX8QM_ACM_SAI7_MCLK_SEL>,
<&clk IMX8QM_AUD_PLL1_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_REC_CLK1_DIV>,
<&clk IMX8QM_AUD_SAI_7_MCLK>;
assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK1_CLK>;
assigned-clock-rates = <0>, <786432000>, <98304000>, <12288000>, <98304000>;
fsl,sai-asynchronous;
fsl,txm-rxs;
status = "okay";
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
imx8qm-mek {
pinctrl_hog: hoggrp {
fsl,pins = <
SC_P_MCLK_OUT0_AUD_ACM_MCLK_OUT0 0x0600004c
SC_P_QSPI1A_DATA1_LSIO_GPIO4_IO25 0x0600004c
>;
};
pinctrl_cm41_i2c0: cm41i2c0grp {
fsl,pins = <
SC_P_M41_I2C0_SCL_M41_I2C0_SCL 0x0600004c
SC_P_M41_I2C0_SDA_M41_I2C0_SDA 0x0600004c
>;
};
pinctrl_esai0: esai0grp {
fsl,pins = <
SC_P_ESAI0_FSR_AUD_ESAI0_FSR 0xc6000040
SC_P_ESAI0_FST_AUD_ESAI0_FST 0xc6000040
SC_P_ESAI0_SCKR_AUD_ESAI0_SCKR 0xc6000040
SC_P_ESAI0_SCKT_AUD_ESAI0_SCKT 0xc6000040
SC_P_ESAI0_TX0_AUD_ESAI0_TX0 0xc6000040
SC_P_ESAI0_TX1_AUD_ESAI0_TX1 0xc6000040
SC_P_ESAI0_TX2_RX3_AUD_ESAI0_TX2_RX3 0xc6000040
SC_P_ESAI0_TX3_RX2_AUD_ESAI0_TX3_RX2 0xc6000040
SC_P_ESAI0_TX4_RX1_AUD_ESAI0_TX4_RX1 0xc6000040
SC_P_ESAI0_TX5_RX0_AUD_ESAI0_TX5_RX0 0xc6000040
>;
};
pinctrl_fec1: fec1grp {
fsl,pins = <
SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
>;
};
pinctrl_fec2: fec2grp {
fsl,pins = <
SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x06000020
SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x06000020
SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x06000020
SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x06000020
SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x06000020
SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x06000020
SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x06000020
SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x06000020
SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x06000020
SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x06000020
SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x06000020
SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x06000020
>;
};
pinctrl_flexspi0: flexspi0grp {
fsl,pins = <
SC_P_QSPI0A_DATA0_LSIO_QSPI0A_DATA0 0x0600004c
SC_P_QSPI0A_DATA1_LSIO_QSPI0A_DATA1 0x0600004c
SC_P_QSPI0A_DATA2_LSIO_QSPI0A_DATA2 0x0600004c
SC_P_QSPI0A_DATA3_LSIO_QSPI0A_DATA3 0x0600004c
SC_P_QSPI0A_DQS_LSIO_QSPI0A_DQS 0x0600004c
SC_P_QSPI0A_SS0_B_LSIO_QSPI0A_SS0_B 0x0600004c
SC_P_QSPI0A_SS1_B_LSIO_QSPI0A_SS1_B 0x0600004c
SC_P_QSPI0A_SCLK_LSIO_QSPI0A_SCLK 0x0600004c
SC_P_QSPI0B_SCLK_LSIO_QSPI0B_SCLK 0x0600004c
SC_P_QSPI0B_DATA0_LSIO_QSPI0B_DATA0 0x0600004c
SC_P_QSPI0B_DATA1_LSIO_QSPI0B_DATA1 0x0600004c
SC_P_QSPI0B_DATA2_LSIO_QSPI0B_DATA2 0x0600004c
SC_P_QSPI0B_DATA3_LSIO_QSPI0B_DATA3 0x0600004c
SC_P_QSPI0B_DQS_LSIO_QSPI0B_DQS 0x0600004c
SC_P_QSPI0B_SS0_B_LSIO_QSPI0B_SS0_B 0x0600004c
SC_P_QSPI0B_SS1_B_LSIO_QSPI0B_SS1_B 0x0600004c
>;
};
pinctrl_flexcan1: flexcan0grp {
fsl,pins = <
SC_P_FLEXCAN0_TX_DMA_FLEXCAN0_TX 0x21
SC_P_FLEXCAN0_RX_DMA_FLEXCAN0_RX 0x21
>;
};
pinctrl_flexcan2: flexcan1grp {
fsl,pins = <
SC_P_FLEXCAN1_TX_DMA_FLEXCAN1_TX 0x21
SC_P_FLEXCAN1_RX_DMA_FLEXCAN1_RX 0x21
>;
};
pinctrl_flexcan3: flexcan2grp {
fsl,pins = <
SC_P_FLEXCAN2_TX_DMA_FLEXCAN2_TX 0x21
SC_P_FLEXCAN2_RX_DMA_FLEXCAN2_RX 0x21
>;
};
pinctrl_lpuart0: lpuart0grp {
fsl,pins = <
SC_P_UART0_RX_DMA_UART0_RX 0x06000020
SC_P_UART0_TX_DMA_UART0_TX 0x06000020
>;
};
pinctrl_lpuart1: lpuart1grp {
fsl,pins = <
SC_P_UART1_RX_DMA_UART1_RX 0x06000020
SC_P_UART1_TX_DMA_UART1_TX 0x06000020
SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020
SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020
SC_P_QSPI1A_DQS_LSIO_GPIO4_IO22 0x00000021
>;
};
pinctrl_lpuart2: lpuart2grp {
fsl,pins = <
SC_P_UART0_RTS_B_DMA_UART2_RX 0x06000020
SC_P_UART0_CTS_B_DMA_UART2_TX 0x06000020
>;
};
pinctrl_lpuart3: lpuart3grp {
fsl,pins = <
SC_P_M41_GPIO0_00_DMA_UART3_RX 0x06000020
SC_P_M41_GPIO0_01_DMA_UART3_TX 0x06000020
>;
};
pinctrl_mlb: mlbgrp {
fsl,pins = <
SC_P_MLB_SIG_CONN_MLB_SIG 0x21
SC_P_MLB_CLK_CONN_MLB_CLK 0x21
SC_P_MLB_DATA_CONN_MLB_DATA 0x21
>;
};
pinctrl_sai1: sai1grp {
fsl,pins = <
SC_P_SAI1_RXD_AUD_SAI1_RXD 0x06000040
SC_P_SAI1_RXC_AUD_SAI1_RXC 0x06000040
SC_P_SAI1_RXFS_AUD_SAI1_RXFS 0x06000040
SC_P_SAI1_TXD_AUD_SAI1_TXD 0x06000060
SC_P_SAI1_TXC_AUD_SAI1_TXC 0x06000040
>;
};
pinctrl_i2c0: i2c0grp {
fsl,pins = <
SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0x06000021
SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0x06000021
>;
};
pinctrl_isl29023: isl29023grp {
fsl,pins = <
SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
SC_P_GPT0_CLK_DMA_I2C1_SCL 0x0600004c
SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x0600004c
>;
};
pinctrl_pciea: pcieagrp{
fsl,pins = <
SC_P_PCIE_CTRL0_CLKREQ_B_LSIO_GPIO4_IO27 0x00000021
SC_P_PCIE_CTRL0_WAKE_B_LSIO_GPIO4_IO28 0x00000021
SC_P_PCIE_CTRL0_PERST_B_LSIO_GPIO4_IO29 0x00000021
SC_P_LVDS1_I2C0_SDA_LVDS1_GPIO0_IO03 0x00000021
SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x00000021
>;
};
pinctrl_sim0: sim0grp {
fsl,pins = <
SC_P_SIM0_CLK_DMA_SIM0_CLK 0x21
SC_P_SIM0_IO_DMA_SIM0_IO 0x21
SC_P_SIM0_PD_DMA_SIM0_PD 0x21
SC_P_SIM0_POWER_EN_DMA_SIM0_POWER_EN 0x21
SC_P_SIM0_RST_DMA_SIM0_RST 0x21
>;
};
pinctrl_typec: typecgrp {
fsl,pins = <
SC_P_QSPI1A_SS0_B_LSIO_GPIO4_IO19 0x60
SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x60
SC_P_QSPI1A_DATA0_LSIO_GPIO4_IO26 0x00000021
>;
};
pinctrl_usbotg1: usbotg1 {
fsl,pins = <
SC_P_USB_SS3_TC0_CONN_USB_OTG1_PWR 0x00000021
>;
};
pinctrl_usdhc1: usdhc1grp {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
>;
};
pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
>;
};
pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
fsl,pins = <
SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040
SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
>;
};
pinctrl_usdhc2_gpio: usdhc2grpgpio {
fsl,pins = <
SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
>;
};
pinctrl_lvds0_lpi2c1: lvds0lpi2c1grp {
fsl,pins = <
SC_P_LVDS0_I2C1_SCL_LVDS0_I2C1_SCL 0xc600004c
SC_P_LVDS0_I2C1_SDA_LVDS0_I2C1_SDA 0xc600004c
>;
};
pinctrl_lvds1_lpi2c1: lvds1lpi2c1grp {
fsl,pins = <
SC_P_LVDS1_I2C1_SCL_LVDS1_I2C1_SCL 0xc600004c
SC_P_LVDS1_I2C1_SDA_LVDS1_I2C1_SDA 0xc600004c
>;
};
pinctrl_lvds0_pwm0: lvds0pwm0grp {
fsl,pins = <
SC_P_LVDS0_GPIO00_LVDS0_PWM0_OUT 0x00000020
>;
};
pinctrl_lvds1_pwm0: lvds1pwm0grp {
fsl,pins = <
SC_P_LVDS1_GPIO00_LVDS1_PWM0_OUT 0x00000020
>;
};
pinctrl_mipi0_lpi2c0: mipi0_lpi2c0grp {
fsl,pins = <
SC_P_MIPI_DSI0_I2C0_SCL_MIPI_DSI0_I2C0_SCL 0xc600004c
SC_P_MIPI_DSI0_I2C0_SDA_MIPI_DSI0_I2C0_SDA 0xc600004c
>;
};
pinctrl_mipi1_lpi2c0: mipi1_lpi2c0grp {
fsl,pins = <
SC_P_MIPI_DSI1_I2C0_SCL_MIPI_DSI1_I2C0_SCL 0xc600004c
SC_P_MIPI_DSI1_I2C0_SDA_MIPI_DSI1_I2C0_SDA 0xc600004c
>;
};
pinctrl_mipi_dsi_0_1_en: mipi_dsi_0_1_en {
fsl,pins = <
SC_P_LVDS0_I2C0_SDA_LSIO_GPIO1_IO07 0x00000021
>;
};
pinctrl_mipi_csi0_gpio: mipicsi0gpiogrp{
fsl,pins = <
SC_P_MIPI_CSI0_GPIO0_00_MIPI_CSI0_GPIO0_IO00 0x00000021
SC_P_MIPI_CSI0_GPIO0_01_MIPI_CSI0_GPIO0_IO01 0x00000021
>;
};
pinctrl_mipi_csi1_gpio: mipicsi1gpiogrp{
fsl,pins = <
SC_P_MIPI_CSI1_GPIO0_00_MIPI_CSI1_GPIO0_IO00 0x00000021
SC_P_MIPI_CSI1_GPIO0_01_MIPI_CSI1_GPIO0_IO01 0x00000021
>;
};
};
};
&asrc0 {
fsl,asrc-rate = <48000>;
status = "okay";
};
&esai0 {
compatible = "fsl,imx8qm-esai";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esai0>;
assigned-clocks = <&clk IMX8QM_ACM_ESAI0_MCLK_SEL>,
<&clk IMX8QM_AUD_PLL0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
<&clk IMX8QM_AUD_ESAI_0_EXTAL_IPG>;
assigned-clock-parents = <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_CLK>;
assigned-clock-rates = <0>, <786432000>, <49152000>, <12288000>, <49152000>;
status = "okay";
};
&emvsim0 {
pinctrl-names = "default", "sleep";
pinctrl-0 = <&pinctrl_sim0>;
pinctrl-1 = <&pinctrl_sim0>;
status = "okay";
};
&sai1 {
assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
<&clk IMX8QM_AUD_SAI_1_MCLK>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <49152000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_sai1>;
status = "okay";
};
&usbotg1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usbotg1>;
srp-disable;
hnp-disable;
adp-disable;
power-polarity-active-high;
disable-over-current;
status = "okay";
};
&usbotg3 {
dr_mode = "otg";
extcon = <&typec_ptn5110>;
status = "okay";
};
&usdhc1 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc1>;
pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
bus-width = <4>;
cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
vmmc-supply = <&reg_usdhc2_vmmc>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec1>;
phy-mode = "rgmii";
phy-handle = <&ethphy0>;
fsl,magic-packet;
fsl,rgmii_txc_dly;
fsl,rgmii_rxc_dly;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy0: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
ethphy1: ethernet-phy@1 {
compatible = "ethernet-phy-ieee802.3-c22";
reg = <1>;
at803x,eee-disabled;
at803x,vddio-1p8v;
};
};
};
&flexspi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexspi0>;
status = "okay";
flash0: mt35xu512aba@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "micron,mt35xu512aba";
spi-max-frequency = <29000000>;
spi-nor,ddr-quad-read-dummy = <8>;
};
};
&flexcan1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan1>;
xceiver-supply = <&reg_can01_stby>;
status = "okay";
};
&flexcan2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan2>;
xceiver-supply = <&reg_can01_stby>;
status = "okay";
};
&flexcan3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_flexcan3>;
xceiver-supply = <&reg_can2_stby>;
status = "okay";
};
&i2c0 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c0>;
status = "okay";
isl29023@44 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_isl29023>;
compatible = "fsl,isl29023";
reg = <0x44>;
rext = <499>;
interrupt-parent = <&gpio4>;
interrupts = <11 2>;
};
fxos8700@1e {
compatible = "fsl,fxos8700";
reg = <0x1e>;
interrupt-open-drain;
};
fxas2100x@20 {
compatible = "fsl,fxas2100x";
reg = <0x20>;
interrupt-open-drain;
};
max7322: gpio@68 {
compatible = "maxim,max7322";
reg = <0x68>;
gpio-controller;
#gpio-cells = <2>;
};
mpl3115@60 {
compatible = "fsl,mpl3115";
reg = <0x60>;
interrupt-open-drain;
};
typec_ptn5110: typec@50 {
compatible = "usb,tcpci";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_typec>;
reg = <0x51>;
interrupt-parent = <&gpio4>;
interrupts = <26 IRQ_TYPE_LEVEL_LOW>;
ss-sel-gpios = <&gpio4 6 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio4 19 GPIO_ACTIVE_HIGH>;
src-pdos = <0x380190c8 0x3803c0c8>;
port-type = "drp";
sink-disable;
default-role = "source";
status = "okay";
};
};
&i2c1 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
wm8960: wm8960@1a {
compatible = "wlf,wm8960";
reg = <0x1a>;
clocks = <&clk IMX8QM_AUD_MCLKOUT0>;
clock-names = "mclk";
wlf,shared-lrclk;
power-domains = <&pd_mclk_out0>;
assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
<&clk IMX8QM_AUD_MCLKOUT0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
};
};
&i2c0_cm41 {
#address-cells = <1>;
#size-cells = <0>;
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cm41_i2c0>;
status = "okay";
pca6416: gpio@20 {
compatible = "ti,tca6416";
reg = <0x20>;
gpio-controller;
#gpio-cells = <2>;
};
cs42888: cs42888@48 {
compatible = "cirrus,cs42888";
reg = <0x48>;
clocks = <&clk IMX8QM_AUD_MCLKOUT0>;
clock-names = "mclk";
VA-supply = <&reg_audio>;
VD-supply = <&reg_audio>;
VLS-supply = <&reg_audio>;
VLC-supply = <&reg_audio>;
reset-gpio = <&gpio4 25 1>;
power-domains = <&pd_mclk_out0>;
assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
<&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
<&clk IMX8QM_AUD_MCLKOUT0>;
assigned-clock-rates = <786432000>, <49152000>, <12288000>, <12288000>;
status = "okay";
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec2>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>;
phy-supply = <&reg_fec2_supply>;
fsl,magic-packet;
status = "okay";
};
&pd_dma_lpuart0 {
debug_console;
};
&lpuart0 { /* console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart0>;
status = "okay";
};
&lpuart1 { /* BT */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart1>;
resets = <&modem_reset>;
status = "okay";
};
&lpuart2 { /* Dbg console */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart2>;
status = "disabled";
};
&lpuart3 { /* MKbus */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lpuart3>;
status = "okay";
};
&gpu_3d0 {
status = "okay";
};
&gpu_3d1 {
status = "okay";
};
&imx8_gpu_ss {
status = "okay";
};
&prg1 {
status = "okay";
};
&prg2 {
status = "okay";
};
&prg3 {
status = "okay";
};
&prg4 {
status = "okay";
};
&prg5 {
status = "okay";
};
&prg6 {
status = "okay";
};
&prg7 {
status = "okay";
};
&prg8 {
status = "okay";
};
&prg9 {
status = "okay";
};
&dpr1_channel1 {
status = "okay";
};
&dpr1_channel2 {
status = "okay";
};
&dpr1_channel3 {
status = "okay";
};
&dpr2_channel1 {
status = "okay";
};
&dpr2_channel2 {
status = "okay";
};
&dpr2_channel3 {
status = "okay";
};
&dpu1 {
status = "okay";
};
&prg10 {
status = "okay";
};
&prg11 {
status = "okay";
};
&prg12 {
status = "okay";
};
&prg13 {
status = "okay";
};
&prg14 {
status = "okay";
};
&prg15 {
status = "okay";
};
&prg16 {
status = "okay";
};
&prg17 {
status = "okay";
};
&prg18 {
status = "okay";
};
&dpr3_channel1 {
status = "okay";
};
&dpr3_channel2 {
status = "okay";
};
&dpr3_channel3 {
status = "okay";
};
&dpr4_channel1 {
status = "okay";
};
&dpr4_channel2 {
status = "okay";
};
&dpr4_channel3 {
status = "okay";
};
&dpu2 {
status = "okay";
};
&pciea{
ext_osc = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pciea>;
disable-gpio = <&gpio0 3 GPIO_ACTIVE_LOW>;
reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>;
clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
epdev_on-supply = <&epdev_on>;
status = "okay";
};
&intmux_cm40 {
status = "okay";
};
&rpmsg{
/*
* 64K for one rpmsg instance:
* --0xb8000000~0xb800ffff: pingpong
*/
vdev-nums = <1>;
reg = <0x0 0xb8000000 0x0 0x10000>;
status = "okay";
};
&intmux_cm41 {
status = "okay";
};
&rpmsg1{
/*
* 64K for one rpmsg instance:
* --0xb8100000~0xb810ffff: pingpong
*/
vdev-nums = <1>;
reg = <0x0 0xb8100000 0x0 0x10000>;
status = "okay";
};
&mipi_csi_0 {
#address-cells = <1>;
#size-cells = <0>;
virtual-channel;
status = "okay";
/* Camera 0 MIPI CSI-2 (CSIS0) */
port@0 {
reg = <0>;
mipi_csi0_ep: endpoint {
remote-endpoint = <&max9286_0_ep>;
data-lanes = <1 2 3 4>;
};
};
};
&mipi_csi_1 {
#address-cells = <1>;
#size-cells = <0>;
virtual-channel;
status = "disabled";
/* Camera 0 MIPI CSI-2 (CSIS1) */
port@1 {
reg = <1>;
mipi_csi1_ep: endpoint {
remote-endpoint = <&max9286_1_ep>;
data-lanes = <1 2 3 4>;
};
};
};
&mlb {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mlb>;
status = "okay";
};
&gpio0_mipi_csi0 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mipi_csi0_gpio>;
status = "okay";
};
&gpio0_mipi_csi1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mipi_csi1_gpio>;
status = "okay";
};
&i2c0_mipi_csi0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
clock-frequency = <100000>;
status = "okay";
max9286_mipi@6A {
compatible = "maxim,max9286_mipi";
reg = <0x6A>;
clocks = <&clk IMX8QM_CLK_DUMMY>;
clock-names = "capture_mclk";
mclk = <27000000>;
mclk_source = <0>;
pwn-gpios = <&gpio0_mipi_csi0 0 GPIO_ACTIVE_HIGH>;
virtual-channel;
port {
max9286_0_ep: endpoint {
remote-endpoint = <&mipi_csi0_ep>;
data-lanes = <1 2 3 4>;
};
};
};
};
&i2c0_mipi_csi1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
clock-frequency = <100000>;
status = "disabled";
max9286_mipi@6A {
compatible = "maxim,max9286_mipi";
reg = <0x6A>;
clocks = <&clk IMX8QM_CLK_DUMMY>;
clock-names = "capture_mclk";
mclk = <27000000>;
mclk_source = <0>;
pwn-gpios = <&gpio0_mipi_csi1 0 GPIO_ACTIVE_HIGH>;
virtual-channel;
port {
max9286_1_ep: endpoint {
remote-endpoint = <&mipi_csi1_ep>;
data-lanes = <1 2 3 4>;
};
};
};
};
&isi_0 {
status = "okay";
};
&isi_1 {
status = "okay";
};
&isi_2 {
status = "okay";
};
&isi_3 {
status = "okay";
};
&sata {
pinctrl-0 = <&pinctrl_pciea>;
clkreq-gpio = <&gpio4 27 GPIO_ACTIVE_LOW>;
status = "okay";
};
&ldb1_phy {
status = "okay";
};
&ldb1 {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "jeida";
fsl,data-width = <24>;
status = "okay";
port@1 {
reg = <1>;
lvds0_out: endpoint {
remote-endpoint = <&it6263_0_in>;
};
};
};
};
&i2c1_lvds0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds0_lpi2c1>;
clock-frequency = <100000>;
status = "okay";
lvds-to-hdmi-bridge@4c {
compatible = "ite,it6263";
reg = <0x4c>;
port {
it6263_0_in: endpoint {
clock-lanes = <3>;
data-lanes = <0 1 2 4>;
remote-endpoint = <&lvds0_out>;
};
};
};
};
&ldb2_phy {
status = "okay";
};
&ldb2 {
status = "okay";
lvds-channel@0 {
fsl,data-mapping = "jeida";
fsl,data-width = <24>;
status = "okay";
port@1 {
reg = <1>;
lvds1_out: endpoint {
remote-endpoint = <&it6263_1_in>;
};
};
};
};
&i2c1_lvds1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds1_lpi2c1>;
clock-frequency = <100000>;
status = "okay";
lvds-to-hdmi-bridge@4c {
compatible = "ite,it6263";
reg = <0x4c>;
port {
it6263_1_in: endpoint {
clock-lanes = <3>;
data-lanes = <0 1 2 4>;
remote-endpoint = <&lvds1_out>;
};
};
};
};
&i2c0_mipi_dsi0 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mipi0_lpi2c0>;
clock-frequency = <100000>;
status = "okay";
adv_bridge1: adv7535@3d {
compatible = "adi,adv7535", "adi,adv7533";
reg = <0x3d>;
adi,dsi-lanes = <4>;
adi,dsi-channel = <1>;
status = "okay";
port {
adv7535_1_in: endpoint {
remote-endpoint = <&mipi_dsi_bridge1_adv>;
};
};
};
};
&mipi_dsi_phy1 {
status = "okay";
};
&mipi_dsi1 {
status = "okay";
};
&mipi_dsi_bridge1 {
status = "okay";
port@1 {
mipi_dsi_bridge1_adv: endpoint {
remote-endpoint = <&adv7535_1_in>;
};
};
};
&i2c0_mipi_dsi1 {
#address-cells = <1>;
#size-cells = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_mipi1_lpi2c0>;
clock-frequency = <100000>;
status = "okay";
adv_bridge2: adv7535@3d {
compatible = "adi,adv7535", "adi,adv7533";
reg = <0x3d>;
adi,dsi-lanes = <4>;
adi,dsi-channel = <1>;
status = "okay";
port {
adv7535_2_in: endpoint {
remote-endpoint = <&mipi_dsi_bridge2_adv>;
};
};
};
};
&mipi_dsi_phy2 {
status = "okay";
};
&mipi_dsi2 {
status = "okay";
};
&mipi_dsi_bridge2 {
status = "okay";
port@1 {
mipi_dsi_bridge2_adv: endpoint {
remote-endpoint = <&adv7535_2_in>;
};
};
};
&lvds0_pwm {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds0_pwm0>;
status = "okay";
};
&lvds1_pwm {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lvds1_pwm0>;
status = "okay";
};