Madan Mohan Koyyalamudi | e32d219 | 2013-09-28 23:54:37 -0700 | [diff] [blame] | 1 | /* |
Mohit Khanna | 8b0ec31 | 2014-03-17 18:03:03 -0700 | [diff] [blame] | 2 | * Copyright (c) 2013-2014 The Linux Foundation. All rights reserved. |
Madan Mohan Koyyalamudi | e32d219 | 2013-09-28 23:54:37 -0700 | [diff] [blame] | 3 | * |
| 4 | * Previously licensed under the ISC license by Qualcomm Atheros, Inc. |
| 5 | * |
| 6 | * |
| 7 | * Permission to use, copy, modify, and/or distribute this software for |
| 8 | * any purpose with or without fee is hereby granted, provided that the |
| 9 | * above copyright notice and this permission notice appear in all |
| 10 | * copies. |
| 11 | * |
| 12 | * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL |
| 13 | * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED |
| 14 | * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE |
| 15 | * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL |
| 16 | * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR |
| 17 | * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER |
| 18 | * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR |
| 19 | * PERFORMANCE OF THIS SOFTWARE. |
| 20 | */ |
| 21 | |
| 22 | /* |
| 23 | * This file was originally distributed by Qualcomm Atheros, Inc. |
| 24 | * under proprietary terms before Copyright ownership was assigned |
| 25 | * to the Linux Foundation. |
| 26 | */ |
| 27 | |
Prakash Dhavali | 25f7f89 | 2014-01-08 21:53:20 -0800 | [diff] [blame] | 28 | |
Madan Mohan Koyyalamudi | e32d219 | 2013-09-28 23:54:37 -0700 | [diff] [blame] | 29 | #ifndef _ATH_AH_OSDEP_H_ |
| 30 | |
| 31 | #define _ATH_AH_OSDEP_H_ |
| 32 | |
| 33 | /* |
| 34 | |
| 35 | * Atheros Hardware Access Layer (HAL) OS Dependent Definitions. |
| 36 | |
| 37 | */ |
| 38 | |
| 39 | |
| 40 | |
| 41 | /* |
| 42 | |
| 43 | * We're releasing binary HAL as a stand-alone module, so we don't |
| 44 | |
| 45 | * need to worry about compatibilities regarding calling convention. |
| 46 | |
| 47 | * By default, Windows uses PASCAL convention. |
| 48 | |
| 49 | */ |
| 50 | |
| 51 | #ifndef __ahdecl |
| 52 | |
| 53 | #define __ahdecl |
| 54 | |
| 55 | #endif |
| 56 | |
| 57 | |
| 58 | |
| 59 | #define __va_list va_list |
| 60 | |
| 61 | #define OS_INLINE __inline |
| 62 | |
| 63 | #ifndef inline |
| 64 | |
| 65 | #define inline __inline |
| 66 | |
| 67 | #endif |
| 68 | |
| 69 | //typedef unsigned int uintptr_t; |
| 70 | |
| 71 | //typedef unsigned long dma_addr_t; |
| 72 | |
| 73 | typedef int bus_space_tag_t; |
| 74 | |
| 75 | typedef char * bus_space_handle_t; |
| 76 | |
| 77 | typedef u_int32_t bus_addr_t; |
| 78 | |
| 79 | |
| 80 | |
| 81 | typedef void* HAL_SOFTC; |
| 82 | |
| 83 | typedef bus_space_handle_t HAL_BUS_HANDLE; |
| 84 | |
| 85 | typedef void* HAL_ADAPTER_HANDLE; |
| 86 | |
| 87 | typedef u_int32_t HAL_BUS_ADDR; /* XXX architecture dependent */ |
| 88 | |
| 89 | typedef bus_space_tag_t HAL_BUS_TAG; |
| 90 | |
| 91 | /* |
| 92 | |
| 93 | * Atomic interface |
| 94 | |
| 95 | */ |
| 96 | |
| 97 | typedef u_int32_t os_atomic_t; |
| 98 | |
| 99 | |
| 100 | /* no-ops */ |
| 101 | #define HAL_USE_INTERSPERSED_READS |
| 102 | #define HAL_NO_INTERSPERSED_READS |
| 103 | |
| 104 | //#define OS_ATOMIC_READ(_patomic_arg) (*(_patomic_arg)) |
| 105 | |
| 106 | //#define OS_ATOMIC_SET(_patomic_arg, v) InterlockedExchange(_patomic_arg, (v)) |
| 107 | |
| 108 | //#define OS_ATOMIC_ADD(v, _patomic_arg) InterlockedExchangeAdd(_patomic_arg, (v)) |
| 109 | |
| 110 | #define OS_ATOMIC_INC(_patomic_arg) ((*_patomic_arg)++) |
| 111 | |
| 112 | #define OS_ATOMIC_DEC(_patomic_arg) ((*_patomic_arg)--) |
| 113 | |
| 114 | //#define OS_ATOMIC_DEC_AND_TEST(_patomic_arg) (NdisInterlockedDecrement(_patomic_arg) == 0) |
| 115 | |
| 116 | |
| 117 | |
| 118 | //#define OS_CMPXCHG(_m, _old, _new) InterlockedCompareExchange(_m, _new, _old) |
| 119 | |
| 120 | |
| 121 | |
Jeff Johnson | 88a5741 | 2014-02-18 15:58:27 -0800 | [diff] [blame] | 122 | /* |
Madan Mohan Koyyalamudi | e32d219 | 2013-09-28 23:54:37 -0700 | [diff] [blame] | 123 | |
| 124 | * Supported Bus types |
| 125 | |
| 126 | */ |
| 127 | |
| 128 | typedef enum ath_hal_bus_type { |
| 129 | |
| 130 | HAL_BUS_TYPE_PCI, |
Mohit Khanna | 8b0ec31 | 2014-03-17 18:03:03 -0700 | [diff] [blame] | 131 | HAL_BUS_TYPE_AHB, |
| 132 | HAL_BUS_TYPE_SIM, /* simulator */ |
| 133 | HAL_BUS_TYPE_SDIO, |
Madan Mohan Koyyalamudi | e32d219 | 2013-09-28 23:54:37 -0700 | [diff] [blame] | 134 | } HAL_BUS_TYPE; |
| 135 | |
| 136 | |
| 137 | |
| 138 | |
| 139 | |
| 140 | /* |
| 141 | |
| 142 | * Bus to hal context handoff |
| 143 | |
| 144 | */ |
| 145 | |
| 146 | typedef struct hal_bus_context { |
| 147 | |
| 148 | HAL_BUS_TAG bc_tag; |
| 149 | |
| 150 | HAL_BUS_HANDLE bc_handle; |
| 151 | |
| 152 | HAL_BUS_TYPE bc_bustype; |
| 153 | |
| 154 | } HAL_BUS_CONTEXT; |
| 155 | |
| 156 | |
| 157 | |
| 158 | #ifndef abs |
| 159 | |
| 160 | #define abs(_a) ( (_a) < 0 ? -(_a) : (_a) ) |
| 161 | |
| 162 | #endif |
| 163 | |
| 164 | |
| 165 | |
| 166 | #define __printflike(_a,_b) \ |
| 167 | __attribute__ ((__format__ (__printf__, _a, _b))) |
| 168 | |
| 169 | |
| 170 | |
| 171 | struct ath_hal; |
| 172 | |
| 173 | struct hal_reg_parm { |
| 174 | |
| 175 | u_int8_t halPciePowerSaveEnable; // Program Serdes; Use ASPM |
| 176 | |
| 177 | u_int8_t halPcieL1SKPEnable; // Enable L1 SKP workaround |
| 178 | |
| 179 | u_int8_t halPcieClockReq; |
| 180 | |
| 181 | u_int32_t halPciePowerReset; |
| 182 | |
| 183 | u_int32_t halPcieWaen; |
| 184 | |
| 185 | u_int32_t halPcieDetach; |
| 186 | |
| 187 | u_int8_t halPcieRestore; |
| 188 | |
| 189 | u_int8_t halPllPwrSave; |
| 190 | |
| 191 | u_int8_t htEnable; // Enable/disable 11n mode |
| 192 | |
| 193 | u_int32_t ofdmTrigLow; |
| 194 | |
| 195 | u_int32_t ofdmTrigHigh; |
| 196 | |
| 197 | u_int32_t cckTrigHigh; |
| 198 | |
| 199 | u_int32_t cckTrigLow; |
| 200 | |
| 201 | u_int32_t enableANI; |
| 202 | |
| 203 | u_int8_t noiseImmunityLvl; |
| 204 | |
| 205 | u_int32_t ofdmWeakSigDet; |
| 206 | |
| 207 | u_int32_t cckWeakSigThr; |
| 208 | |
| 209 | u_int8_t spurImmunityLvl; |
| 210 | |
| 211 | u_int8_t firStepLvl; |
| 212 | |
| 213 | int8_t rssiThrHigh; |
| 214 | |
| 215 | int8_t rssiThrLow; |
| 216 | |
| 217 | u_int16_t diversityControl; // Enable/disable antenna diversity |
| 218 | |
Jeff Johnson | 88a5741 | 2014-02-18 15:58:27 -0800 | [diff] [blame] | 219 | u_int16_t antennaSwitchSwap; |
Madan Mohan Koyyalamudi | e32d219 | 2013-09-28 23:54:37 -0700 | [diff] [blame] | 220 | |
| 221 | u_int32_t forceBias; |
| 222 | |
| 223 | u_int32_t forceBiasAuto; |
| 224 | |
| 225 | int calInFlash; |
| 226 | |
Jeff Johnson | 88a5741 | 2014-02-18 15:58:27 -0800 | [diff] [blame] | 227 | #ifdef ATH_SUPPORT_TxBF |
Madan Mohan Koyyalamudi | e32d219 | 2013-09-28 23:54:37 -0700 | [diff] [blame] | 228 | |
| 229 | u_int8_t CVTimeOut; |
| 230 | |
| 231 | u_int16_t TxBFCtl; |
| 232 | |
| 233 | #endif |
| 234 | |
| 235 | }; |
| 236 | |
| 237 | |
| 238 | |
| 239 | /* |
| 240 | |
| 241 | * Byte order/swapping support. |
| 242 | |
| 243 | */ |
| 244 | |
| 245 | #define AH_LITTLE_ENDIAN 1234 |
| 246 | |
| 247 | #define AH_BIG_ENDIAN 4321 |
| 248 | |
| 249 | |
| 250 | |
| 251 | #ifdef MIPS32 |
| 252 | |
| 253 | #define AH_BYTE_ORDER AH_BIG_ENDIAN |
| 254 | |
| 255 | #endif |
| 256 | |
| 257 | |
| 258 | |
| 259 | #if AH_BYTE_ORDER == AH_BIG_ENDIAN |
| 260 | |
| 261 | /* |
| 262 | |
| 263 | * This could be optimized but since we only use it for |
| 264 | |
| 265 | * a few registers there's little reason to do so. |
| 266 | |
| 267 | */ |
| 268 | |
| 269 | static OS_INLINE u_int32_t |
| 270 | |
| 271 | __bswap32(u_int32_t _x) |
| 272 | |
| 273 | { |
| 274 | |
| 275 | return ((u_int32_t)( |
| 276 | |
| 277 | (((const u_int8_t *)(&_x))[0] ) | |
| 278 | |
| 279 | (((const u_int8_t *)(&_x))[1]<< 8) | |
| 280 | |
| 281 | (((const u_int8_t *)(&_x))[2]<<16) | |
| 282 | |
| 283 | (((const u_int8_t *)(&_x))[3]<<24)) |
| 284 | |
| 285 | ); |
| 286 | |
| 287 | } |
| 288 | |
| 289 | |
| 290 | |
| 291 | #ifndef __BIG_ENDIAN__ |
| 292 | |
| 293 | #define __BIG_ENDIAN__ |
| 294 | |
| 295 | #endif |
| 296 | |
| 297 | |
| 298 | |
| 299 | #else |
| 300 | |
| 301 | #define __bswap32(_x) (_x) |
| 302 | |
| 303 | #endif |
| 304 | |
| 305 | |
| 306 | |
| 307 | /* |
| 308 | |
| 309 | * Register read/write; we assume the registers will always |
| 310 | |
| 311 | * be memory-mapped. Note that register accesses are done |
| 312 | |
| 313 | * using target-specific functions when debugging is enabled |
| 314 | |
| 315 | * (AH_DEBUG) or we are explicitly configured this way. The |
| 316 | |
| 317 | * latter is used on some platforms where the full i/o space |
| 318 | |
| 319 | * cannot be directly mapped. |
| 320 | |
| 321 | * |
| 322 | |
| 323 | * The hardware registers are native little-endian byte order. |
| 324 | |
| 325 | * Big-endian hosts are handled by enabling hardware byte-swap |
| 326 | |
| 327 | * of register reads and writes at reset. But the PCI clock |
| 328 | |
| 329 | * domain registers are not byte swapped! Thus, on big-endian |
| 330 | |
| 331 | * platforms we have to byte-swap thoese registers specifically. |
| 332 | |
| 333 | * Most of this code is collapsed at compile time because the |
| 334 | |
| 335 | * register values are constants. |
| 336 | |
| 337 | */ |
| 338 | |
| 339 | |
| 340 | |
| 341 | #if AH_BYTE_ORDER == AH_BIG_ENDIAN |
| 342 | |
| 343 | |
| 344 | |
| 345 | #define _OS_REG_WRITE(_ah, _reg, _val) \ |
| 346 | *((volatile u_int32_t *)(AH_PRIVATE(_ah)->ah_sh + (_reg))) = (_val) |
| 347 | |
| 348 | #define _OS_REG_READ(_ah, _reg) \ |
| 349 | *((volatile u_int32_t *)(AH_PRIVATE(_ah)->ah_sh + (_reg))) |
| 350 | |
| 351 | |
| 352 | |
| 353 | #else /* _BYTE_ORDER == _LITTLE_ENDIAN */ |
| 354 | |
| 355 | #define __bswap32(_x) (_x) |
| 356 | |
| 357 | #define _OS_REG_WRITE(_ah, _reg, _val) \ |
| 358 | bus_space_write_4(AH_PRIVATE(_ah)->ah_st, AH_PRIVATE(_ah)->ah_sh, (_reg), (_val)) |
| 359 | |
| 360 | #define _OS_REG_READ(_ah, _reg) \ |
| 361 | ((u_int32_t) bus_space_read_4(AH_PRIVATE(_ah)->ah_st, AH_PRIVATE(_ah)->ah_sh, (_reg))) |
| 362 | |
| 363 | #endif /* _BYTE_ORDER */ |
| 364 | |
| 365 | |
| 366 | #ifndef ATH_SUPPORT_HTC |
| 367 | |
| 368 | /* no-op for non-USB solutions */ |
| 369 | #define ENABLE_REG_WRITE_BUFFER |
| 370 | #define DISABLE_REG_WRITE_BUFFER |
| 371 | #define OS_REG_WRITE_FLUSH(_ah) |
| 372 | #define HTC_SET_PS_STATE(_ah, _mode) |
| 373 | |
| 374 | #else /* ATH_SUPPORT_HTC */ |
| 375 | |
| 376 | #define ENABLE_REG_WRITE_BUFFER \ |
| 377 | if (!AH_PRIVATE(ah)->ah_reg_write_buffer_flag) \ |
| 378 | AH_PRIVATE(ah)->ah_reg_write_buffer_flag = 1; \ |
| 379 | else \ |
| 380 | HDPRINTF(ah, HAL_DBG_REG_IO, "%s: Error:REG_WRITE_BUFFER " \ |
| 381 | "had not been correctly disabled!\n", __func__); |
| 382 | |
| 383 | #define DISABLE_REG_WRITE_BUFFER \ |
| 384 | if (AH_PRIVATE(ah)->ah_reg_write_buffer_flag) \ |
| 385 | AH_PRIVATE(ah)->ah_reg_write_buffer_flag = 0; \ |
| 386 | else \ |
| 387 | HDPRINTF(ah, HAL_DBG_REG_IO, "%s: Error:REG_WRITE_BUFFER " \ |
| 388 | "had not been correctly disabled!\n", _func__); |
| 389 | |
| 390 | #define OS_REG_WRITE_FLUSH(_ah) \ |
| 391 | if (AH_PRIVATE(_ah)->ah_reg_write_buffer_flag) { \ |
| 392 | _OS_REG_WRITE_FLUSH(_ah); \ |
| 393 | } else \ |
| 394 | HDPRINTF(ah, HAL_DBG_REG_IO, "%s: Error:REG_WRITE_BUFFER " \ |
| 395 | "must be enabled!\n", _func__); |
| 396 | |
| 397 | extern void ath_hal_wmi_ps_set_state(struct ath_hal *ah, u_int16_t mode); |
| 398 | |
| 399 | #define HTC_SET_PS_STATE(_ah, _mode) \ |
| 400 | ath_hal_wmi_ps_set_state(_ah, _mode); |
| 401 | |
| 402 | #endif /* ATH_SUPPORT_HTC */ |
| 403 | |
| 404 | |
| 405 | #if defined(AH_DEBUG) || defined(AH_REGOPS_FUNC) || defined(AH_DEBUG_ALQ) |
| 406 | |
| 407 | #define OS_REG_WRITE(_ah, _reg, _val) ath_hal_reg_write(_ah, _reg, _val) |
| 408 | #define OS_REG_READ(_ah, _reg) ath_hal_reg_read(_ah, _reg) |
| 409 | |
| 410 | u_int32_t __ahdecl ath_hal_reg_read(struct ath_hal *, u_int32_t); |
| 411 | void __ahdecl ath_hal_reg_write(struct ath_hal *, u_int32_t, u_int32_t); |
| 412 | |
| 413 | #else |
| 414 | |
| 415 | #define OS_REG_WRITE(_ah, _reg, _val) _OS_REG_WRITE(_ah, _reg, _val) |
| 416 | #define OS_REG_READ(_ah, _reg) _OS_REG_READ(_ah, _reg) |
| 417 | |
| 418 | #endif /* AH_DEBUG || AH_REGFUNC || AH_DEBUG_ALQ */ |
| 419 | |
| 420 | |
| 421 | #ifdef AH_DEBUG_ALQ |
| 422 | extern void __ahdecl OS_MARK(struct ath_hal *, u_int id, u_int32_t value); |
| 423 | #else |
| 424 | #define OS_MARK(_ah, _id, _v) |
| 425 | #endif |
| 426 | |
| 427 | |
| 428 | /* |
| 429 | * Linux-specific attach/detach methods needed for module reference counting. |
| 430 | * |
| 431 | * XXX We can't use HAL_STATUS because the type isn't defined at this |
| 432 | * point (circular dependency); we wack the type and patch things |
| 433 | * up in the function. |
| 434 | * |
| 435 | * NB: These are intentionally not marked __ahdecl since they are |
| 436 | * compiled with the default calling convetion and are not called |
| 437 | * from within the HAL. |
| 438 | */ |
| 439 | |
| 440 | typedef u_int32_t (*HAL_BUS_CONFIG_READER)(HAL_SOFTC sc, u_int32_t offset, void *pBuffer, u_int32_t length); |
| 441 | |
| 442 | struct ath_hal_callback { |
| 443 | /* Callback Functions */ |
| 444 | HAL_BUS_CONFIG_READER read_pci_config_space; |
| 445 | }; |
| 446 | |
| 447 | |
| 448 | /* |
| 449 | * osdev_t specific flags. |
| 450 | */ |
| 451 | #define ATH_ATTACHED 0x0001 /* attach has succeeded */ |
| 452 | #define ATH_ENABLED 0x0002 /* chip is enabled */ |
| 453 | #define ATH_RXREFILL 0x0004 /* Refill the recv bufs */ |
| 454 | |
| 455 | #define ATH_IS_ENABLED(osdev) ((osdev)->sc_flags & ATH_ENABLED) |
| 456 | |
| 457 | #ifdef AR9100 |
| 458 | extern void ath_hal_ahb_mac_reset(void); |
| 459 | extern void ath_hal_get_chip_revisionid(u_int32_t *); |
| 460 | #endif |
| 461 | |
| 462 | #ifndef ARRAY_LENGTH |
| 463 | #define ARRAY_LENGTH(a) (sizeof(a) / sizeof((a)[0])) |
| 464 | #endif |
| 465 | |
| 466 | #endif /* _ATH_AH_OSDEP_H_ */ |