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Soby Mathewe33b78a2016-05-05 14:10:46 +01001/*
2 * Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 *
7 * Redistributions of source code must retain the above copyright notice, this
8 * list of conditions and the following disclaimer.
9 *
10 * Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
13 *
14 * Neither the name of ARM nor the names of its contributors may be used
15 * to endorse or promote products derived from this software without specific
16 * prior written permission.
17 *
18 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
19 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
21 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
22 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
23 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
24 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
25 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
26 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
27 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
28 * POSSIBILITY OF SUCH DAMAGE.
29 */
30
31#include <arch.h>
32#include <asm_macros.S>
33#include <assert_macros.S>
34#include <cpu_data.h>
35#include <cpu_macros.S>
36
Yatharth Kochar1a0a3f02016-06-28 16:58:26 +010037#if IMAGE_BL1 || IMAGE_BL32
Soby Mathewe33b78a2016-05-05 14:10:46 +010038 /*
39 * The reset handler common to all platforms. After a matching
40 * cpu_ops structure entry is found, the correponding reset_handler
41 * in the cpu_ops is invoked. The reset handler is invoked very early
42 * in the boot sequence and it is assumed that we can clobber r0 - r10
43 * without the need to follow AAPCS.
44 * Clobbers: r0 - r10
45 */
46 .globl reset_handler
47func reset_handler
48 mov r10, lr
49
50 /* The plat_reset_handler can clobber r0 - r9 */
51 bl plat_reset_handler
52
53 /* Get the matching cpu_ops pointer (clobbers: r0 - r5) */
54 bl get_cpu_ops_ptr
55
56#if ASM_ASSERTION
57 cmp r0, #0
58 ASM_ASSERT(ne)
59#endif
60
61 /* Get the cpu_ops reset handler */
62 ldr r1, [r0, #CPU_RESET_FUNC]
63 cmp r1, #0
64 mov lr, r10
65 bxne r1
66 bx lr
67endfunc reset_handler
68
Yatharth Kochar1a0a3f02016-06-28 16:58:26 +010069#endif /* IMAGE_BL1 || IMAGE_BL32 */
70
71#if IMAGE_BL32 /* The power down core and cluster is needed only in BL32 */
Soby Mathewe33b78a2016-05-05 14:10:46 +010072 /*
Jeenu Viswambharan5dd9dbb2016-11-18 12:58:28 +000073 * void prepare_cpu_pwr_dwn(unsigned int power_level)
74 *
75 * Prepare CPU power down function for all platforms. The function takes
76 * a domain level to be powered down as its parameter. After the cpu_ops
77 * pointer is retrieved from cpu_data, the handler for requested power
78 * level is called.
Soby Mathewe33b78a2016-05-05 14:10:46 +010079 */
Jeenu Viswambharan5dd9dbb2016-11-18 12:58:28 +000080 .globl prepare_cpu_pwr_dwn
81func prepare_cpu_pwr_dwn
Soby Mathewe33b78a2016-05-05 14:10:46 +010082 /*
Jeenu Viswambharan5dd9dbb2016-11-18 12:58:28 +000083 * If the given power level exceeds CPU_MAX_PWR_DWN_OPS, we call the
84 * power down handler for the last power level
Soby Mathewe33b78a2016-05-05 14:10:46 +010085 */
Jeenu Viswambharan5dd9dbb2016-11-18 12:58:28 +000086 mov r2, #(CPU_MAX_PWR_DWN_OPS - 1)
87 cmp r0, r2
88 movhi r0, r2
Soby Mathewe33b78a2016-05-05 14:10:46 +010089
Jeenu Viswambharan5dd9dbb2016-11-18 12:58:28 +000090 push {r0, lr}
91 bl _cpu_data
92 pop {r2, lr}
93
94 ldr r0, [r0, #CPU_DATA_CPU_OPS_PTR]
Soby Mathewe33b78a2016-05-05 14:10:46 +010095#if ASM_ASSERTION
Jeenu Viswambharan5dd9dbb2016-11-18 12:58:28 +000096 cmp r0, #0
Soby Mathewe33b78a2016-05-05 14:10:46 +010097 ASM_ASSERT(ne)
98#endif
99
Jeenu Viswambharan5dd9dbb2016-11-18 12:58:28 +0000100 /* Get the appropriate power down handler */
101 mov r1, #CPU_PWR_DWN_OPS
102 add r1, r1, r2, lsl #2
103 ldr r1, [r0, r1]
104 bx r1
105endfunc prepare_cpu_pwr_dwn
Soby Mathewe33b78a2016-05-05 14:10:46 +0100106
107 /*
108 * Initializes the cpu_ops_ptr if not already initialized
109 * in cpu_data. This must only be called after the data cache
110 * is enabled. AAPCS is followed.
111 */
112 .globl init_cpu_ops
113func init_cpu_ops
114 push {r4 - r6, lr}
115 bl _cpu_data
116 mov r6, r0
117 ldr r1, [r0, #CPU_DATA_CPU_OPS_PTR]
118 cmp r1, #0
119 bne 1f
120 bl get_cpu_ops_ptr
121#if ASM_ASSERTION
122 cmp r0, #0
123 ASM_ASSERT(ne)
124#endif
125 str r0, [r6, #CPU_DATA_CPU_OPS_PTR]!
1261:
127 pop {r4 - r6, pc}
128endfunc init_cpu_ops
129
Yatharth Kochar1a0a3f02016-06-28 16:58:26 +0100130#endif /* IMAGE_BL32 */
131
Soby Mathewe33b78a2016-05-05 14:10:46 +0100132 /*
133 * The below function returns the cpu_ops structure matching the
134 * midr of the core. It reads the MIDR and finds the matching
135 * entry in cpu_ops entries. Only the implementation and part number
136 * are used to match the entries.
137 * Return :
138 * r0 - The matching cpu_ops pointer on Success
139 * r0 - 0 on failure.
140 * Clobbers: r0 - r5
141 */
142 .globl get_cpu_ops_ptr
143func get_cpu_ops_ptr
144 /* Get the cpu_ops start and end locations */
145 ldr r4, =(__CPU_OPS_START__ + CPU_MIDR)
146 ldr r5, =(__CPU_OPS_END__ + CPU_MIDR)
147
148 /* Initialize the return parameter */
149 mov r0, #0
150
151 /* Read the MIDR_EL1 */
152 ldcopr r2, MIDR
153 ldr r3, =CPU_IMPL_PN_MASK
154
155 /* Retain only the implementation and part number using mask */
156 and r2, r2, r3
1571:
158 /* Check if we have reached end of list */
159 cmp r4, r5
160 bge error_exit
161
162 /* load the midr from the cpu_ops */
163 ldr r1, [r4], #CPU_OPS_SIZE
164 and r1, r1, r3
165
166 /* Check if midr matches to midr of this core */
167 cmp r1, r2
168 bne 1b
169
170 /* Subtract the increment and offset to get the cpu-ops pointer */
171 sub r0, r4, #(CPU_OPS_SIZE + CPU_MIDR)
172error_exit:
173 bx lr
174endfunc get_cpu_ops_ptr