MLK-19256 plat: imx8mm: correct dram apb clock rate dvfs

The DRAM APB bus clock rate is wrong before and after DVFS.
The register offset for APB bus clock is wrong, so fix it.

Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 079eebba34b09d6f9ffeb70d999fb4a065008b1c)
1 file changed