MLK-19256 plat: imx8mm: correct dram apb clock rate dvfs
The DRAM APB bus clock rate is wrong before and after DVFS.
The register offset for APB bus clock is wrong, so fix it.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit 079eebba34b09d6f9ffeb70d999fb4a065008b1c)
diff --git a/plat/imx/common/imx8m/clock.c b/plat/imx/common/imx8m/clock.c
index 72ddbd9..fee6821 100644
--- a/plat/imx/common/imx8m/clock.c
+++ b/plat/imx/common/imx8m/clock.c
@@ -8,9 +8,10 @@
#include <mmio.h>
#include <platform_def.h>
-#define CCM_IP_CLK_ROOT_GEN_TAGET(i) (IMX_CCM_BASE + 0x80 * (i) + 0x00)
-#define CCM_IP_CLK_ROOT_GEN_TAGET_SET(i) (IMX_CCM_BASE + 0x80 * (i) + 0x04)
-#define CCM_IP_CLK_ROOT_GEN_TAGET_CLR(i) (IMX_CCM_BASE + 0x80 * (i) + 0x08)
+#define IMX_CCM_IP_BASE (IMX_CCM_BASE + 0xa000)
+#define CCM_IP_CLK_ROOT_GEN_TAGET(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x00)
+#define CCM_IP_CLK_ROOT_GEN_TAGET_SET(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x04)
+#define CCM_IP_CLK_ROOT_GEN_TAGET_CLR(i) (IMX_CCM_IP_BASE + 0x80 * (i) + 0x08)
void ddr_pll_bypass_100mts(void)
{
