MLK-18343-2: plat: imx8mm: add support for RDC and CSU
move CSU and RDC driver to common/i.mx8m folder
and enable the driver for i.mx8mm
Signed-off-by: Silvano di Ninno <silvano.dininno@nxp.com>
Reviewed-by: Aymen Sghaier <aymen.sghaier@nxp.com>
(cherry picked from commit 7dd1b741efdc60ca6b5eaafc9d863744beb7064e)
Conflicts:
diff --git a/plat/imx/imx8mq/imx_csu.c b/plat/imx/common/imx8m/imx_csu.c
similarity index 100%
rename from plat/imx/imx8mq/imx_csu.c
rename to plat/imx/common/imx8m/imx_csu.c
diff --git a/plat/imx/imx8mq/imx_rdc.c b/plat/imx/common/imx8m/imx_rdc.c
similarity index 100%
rename from plat/imx/imx8mq/imx_rdc.c
rename to plat/imx/common/imx8m/imx_rdc.c
diff --git a/plat/imx/common/include/imx_csu.h b/plat/imx/common/include/imx_csu.h
index 9bf9373..a4ae9ab 100644
--- a/plat/imx/common/include/imx_csu.h
+++ b/plat/imx/common/include/imx_csu.h
@@ -1,44 +1,217 @@
/*
- * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
+ * Copyright 2017 NXP
*
* SPDX-License-Identifier: BSD-3-Clause
*/
+
#ifndef __IMX_CSU_H__
#define __IMX_CSU_H__
-#include <arch.h>
+enum csu_mode {
+ CSU_NSR = 0x08,
+ CSU_NSW = 0x80,
+ CSU_NSRW = 0x88,
+ CSU_NUR = 0x04,
+ CSU_NUW = 0x40,
+ CSU_NURW = 0x44,
+ CSU_SSR = 0x02,
+ CSU_SSW = 0x20,
+ CSU_SSRW = 0x22,
+ CSU_SUR = 0x01,
+ CSU_SUW = 0x10,
+ CSU_SURW = 0x11,
+ CSU_RW = 0xff,
+};
-/*
- * Security Reference Manual for i.MX 7Dual and 7Solo Applications Processors,
- * Rev. 0, 03/2017 Section 3.3.1
- *
- * Config secure level register (CSU_CSLn)
- */
-#define CSU_CSL_LOCK_S1 BIT(24)
-#define CSU_CSL_NSW_S1 BIT(23)
-#define CSU_CSL_NUW_S1 BIT(22)
-#define CSU_CSL_SSW_S1 BIT(21)
-#define CSU_CSL_SUW_S1 BIT(20)
-#define CSU_CSL_NSR_S1 BIT(19)
-#define CSU_CSL_NUR_S1 BIT(18)
-#define CSU_CSL_SSR_S1 BIT(17)
-#define CSU_CSL_SUR_S1 BIT(16)
-#define CSU_CSL_LOCK_S2 BIT(8)
-#define CSU_CSL_NSW_S2 BIT(7)
-#define CSU_CSL_NUW_S2 BIT(6)
-#define CSU_CSL_SSW_S2 BIT(5)
-#define CSU_CSL_SUW_S2 BIT(4)
-#define CSU_CSL_NSR_S2 BIT(3)
-#define CSU_CSL_NUR_S2 BIT(2)
-#define CSU_CSL_SSR_S2 BIT(1)
-#define CSU_CSL_SUR_S2 BIT(0)
+enum csu_csln_idx {
+ CSU_CSLn_GPIO1 = 0,
+ CSU_CSLn_GPIO2 = 1,
+ CSU_CSLn_GPIO3 = 2,
+ CSU_CSLn_GPIO4 = 3,
+ CSU_CSLn_GPIO5 = 4,
+ CSU_CSLn_Reserved1 = 5,
+ CSU_CSLn_ANA_TSENSOR = 6,
+ CSU_CSLn_ANA_OSC = 7,
+ CSU_CSLn_WDOG1 = 8,
+ CSU_CSLn_WDOG2 = 9,
+ CSU_CSLn_WDOG3 = 10,
+ CSU_CSLn_Reserved2 = 11,
+ CSU_CSLn_SDMA2 = 12,
+ CSU_CSLn_GPT1 = 13,
+ CSU_CSLn_GPT2 = 14,
+ CSU_CSLn_GPT3 = 15,
+ CSU_CSLn_Reserved3 = 16,
+ CSU_CSLn_ROMCP = 17,
+ CSU_CSLn_LCDIF = 18,
+ CSU_CSLn_IOMUXC = 19,
+ CSU_CSLn_IOMUXC_GPR = 20,
+ CSU_CSLn_OCOTP_CTRL = 21,
+ CSU_CSLn_ANATOP_PLL = 22,
+ CSU_CSLn_SNVS_HP = 23,
+ CSU_CSLn_CCM = 24,
+ CSU_CSLn_SRC = 25,
+ CSU_CSLn_GPC = 26,
+ CSU_CSLn_SEMAPHORE1 = 27,
+ CSU_CSLn_SEMAPHORE2 = 28,
+ CSU_CSLn_RDC = 29,
+ CSU_CSLn_CSU = 30,
+ CSU_CSLn_Reserved4 = 31,
+ CSU_CSLn_MST0 = 32,
+ CSU_CSLn_MST1 = 33,
+ CSU_CSLn_MST2 = 34,
+ CSU_CSLn_MST3 = 35,
+ CSU_CSLn_HDMI_SEC = 36,
+ CSU_CSLn_Reserved5 = 37,
+ CSU_CSLn_PWM1 = 38,
+ CSU_CSLn_PWM2 = 39,
+ CSU_CSLn_PWM3 = 40,
+ CSU_CSLn_PWM4 = 41,
+ CSU_CSLn_SysCounter_RD = 42,
+ CSU_CSLn_SysCounter_CMP = 43,
+ CSU_CSLn_SysCounter_CTRL = 44,
+ CSU_CSLn_HDMI_CTRL = 45,
+ CSU_CSLn_GPT6 = 46,
+ CSU_CSLn_GPT5 = 47,
+ CSU_CSLn_GPT4 = 48,
+ CSU_CSLn_TZASC = 56,
+ CSU_CSLn_MTR = 59,
+ CSU_CSLn_PERFMON1 = 60,
+ CSU_CSLn_PERFMON2 = 61,
+ CSU_CSLn_PLATFORM_CTRL = 62,
+ CSU_CSLn_QoSC = 63,
+ CSU_CSLn_MIPI_PHY = 64,
+ CSU_CSLn_MIPI_DSI = 65,
+ CSU_CSLn_I2C1 = 66,
+ CSU_CSLn_I2C2 = 67,
+ CSU_CSLn_I2C3 = 68,
+ CSU_CSLn_I2C4 = 69,
+ CSU_CSLn_UART4 = 70,
+ CSU_CSLn_MIPI_CSI1 = 71,
+ CSU_CSLn_MIPI_CSI_PHY1 = 72,
+ CSU_CSLn_CSI1 = 73,
+ CSU_CSLn_MU_A = 74,
+ CSU_CSLn_MU_B = 75,
+ CSU_CSLn_SEMAPHORE_HS = 76,
+ CSU_CSLn_Internal1 = 77,
+ CSU_CSLn_SAI1 = 78,
+ CSU_CSLn_Reserved7 = 79,
+ CSU_CSLn_SAI6 = 80,
+ CSU_CSLn_SAI5 = 81,
+ CSU_CSLn_SAI4 = 82,
+ CSU_CSLn_Internal2 = 83,
+ CSU_CSLn_USDHC1 = 84,
+ CSU_CSLn_USDHC2 = 85,
+ CSU_CSLn_MIPI_CSI2 = 86,
+ CSU_CSLn_MIPI_CSI_PHY2 = 87,
+ CSU_CSLn_CSI2 = 88,
+ CSU_CSLn_Internal3 = 89,
+ CSU_CSLn_Reserved10 = 90,
+ CSU_CSLn_QSPI = 91,
+ CSU_CSLn_Reserved11 = 92,
+ CSU_CSLn_SDMA1 = 93,
+ CSU_CSLn_ENET1 = 94,
+ CSU_CSLn_Reserved12 = 95,
+ CSU_CSLn_Internal4 = 96,
+ CSU_CSLn_SPDIF1 = 97,
+ CSU_CSLn_ECSPI1 = 98,
+ CSU_CSLn_ECSPI2 = 99,
+ CSU_CSLn_ECSPI3 = 100,
+ CSU_CSLn_Reserved14 = 101,
+ CSU_CSLn_UART1 = 102,
+ CSU_CSLn_Internal5 = 103,
+ CSU_CSLn_UART3 = 104,
+ CSU_CSLn_UART2 = 105,
+ CSU_CSLn_SPDIF2 = 106,
+ CSU_CSLn_SAI2 = 107,
+ CSU_CSLn_SAI3 = 108,
+ CSU_CSLn_Reserved16 = 109,
+ CSU_CSLn_Internal6 = 110,
+ CSU_CSLn_SPBA1 = 111,
+ CSU_CSLn_MOD_EN3 = 112,
+ CSU_CSLn_MOD_EN0 = 113,
+ CSU_CSLn_CAAM = 114,
+ CSU_CSLn_DDRC_SEC = 115,
+ CSU_CSLn_GIC_EXSC = 116,
+ CSU_CSLn_USB_EXSC = 117,
+ CSU_CSLn_OCRAM_TZ = 118,
+ CSU_CSLn_OCRAM_S_TZ = 119,
+ CSU_CSLn_VPU_SEC = 120,
+ CSU_CSLn_DAP_EXSC = 121,
+ CSU_CSLn_ROMCP_SEC = 122,
+ CSU_CSLn_APBHDMA_SEC = 123,
+ CSU_CSLn_M4_SEC = 124,
+ CSU_CSLn_QSPI_SEC = 125,
+ CSU_CSLn_GPU_EXSC = 126,
+ CSU_CSLn_PCIE = 127,
+};
-#define CSU_CSL_OPEN_ACCESS (CSU_CSL_NSW_S1 | CSU_CSL_NUW_S1 | CSU_CSL_SSW_S1 |\
- CSU_CSL_SUW_S1 | CSU_CSL_NSR_S1 | CSU_CSL_NUR_S1 |\
- CSU_CSL_SSR_S1 | CSU_CSL_SUR_S1 | CSU_CSL_NSW_S2 |\
- CSU_CSL_NUW_S2 | CSU_CSL_SSW_S2 | CSU_CSL_SUW_S2 |\
- CSU_CSL_NSR_S2 | CSU_CSL_NUR_S2 | CSU_CSL_SSR_S2 |\
- CSU_CSL_SUR_S2)
-void imx_csu_init(void);
+enum csu_hp_idx {
+ CSU_HP_A53,
+ CSU_HP_M4,
+ CSU_HP_SDMA1,
+ CSU_HP_CSI,
+ CSU_HP_USB,
+ CSU_HP_PCIE,
+ CSU_HP_VPU,
+ CSU_HP_GPU,
+ CSU_HP_APBHDMA,
+ CSU_HP_ENET,
+ CSU_HP_USDHC1,
+ CSU_HP_USDHC2,
+ CSU_HP_DCSS,
+ CSU_HP_HUGO,
+ CSU_HP_DAP,
+ CSU_HP_SDMA2,
+ CSU_HP_CAAM,
+};
+enum csu_sa_idx {
+ CSU_SA_M4,
+ CSU_SA_SDMA1,
+ CSU_SA_CSI,
+ CSU_SA_USB,
+ CSU_SA_PCIE,
+ CSU_SA_VPU,
+ CSU_SA_GPU,
+ CSU_SA_APBHDMA,
+ CSU_SA_ENET,
+ CSU_SA_USDHC1,
+ CSU_SA_USDHC2,
+ CSU_SA_DCSS,
+ CSU_SA_HUGO,
+ CSU_SA_DAP,
+ CSU_SA_SDMA2,
+ CSU_SA_CAAM,
+};
+
+struct csu_slave_conf {
+ enum csu_csln_idx index;
+ uint16_t mode;
+ uint16_t lock;
+};
+
+struct csu_sa_conf {
+ enum csu_sa_idx index;
+ uint8_t enable;
+ uint8_t lock;
+};
+
+void csu_set_slave_index_mode(enum csu_csln_idx index,
+ uint16_t mode, uint8_t lock);
+void csu_get_slave_index_mode(enum csu_csln_idx index,
+ uint16_t *mode, uint8_t *lock);
+void csu_set_slaves_modes(struct csu_slave_conf *csu_config, uint32_t count);
+void csu_set_default_slaves_modes(void);
+void csu_set_hp_index_config(enum csu_hp_idx index, uint8_t enable,
+ uint8_t set_control, uint8_t lock);
+void csu_set_sa_index_config(enum csu_sa_idx index, uint8_t enable,
+ uint8_t lock);
+void csu_get_sa_index_config(enum csu_sa_idx index, uint8_t *enable,
+ uint8_t *lock);
+void csu_set_sa_configs(struct csu_sa_conf *sa_configs, uint32_t count);
+void csu_set_default_secure_configs(void);
+
+#if defined (CSU_RDC_TEST)
+void csu_test(void);
+#endif
#endif /* __IMX_CSU_H__ */
diff --git a/plat/imx/imx8mq/include/imx_rdc.h b/plat/imx/common/include/imx_rdc.h
similarity index 100%
rename from plat/imx/imx8mq/include/imx_rdc.h
rename to plat/imx/common/include/imx_rdc.h
diff --git a/plat/imx/imx8mm/imx8mm_bl31_setup.c b/plat/imx/imx8mm/imx8mm_bl31_setup.c
index 1a17110..f6f26f3 100644
--- a/plat/imx/imx8mm/imx8mm_bl31_setup.c
+++ b/plat/imx/imx8mm/imx8mm_bl31_setup.c
@@ -19,6 +19,8 @@
#include <xlat_tables.h>
#include <soc.h>
#include <tzc380.h>
+#include <imx_csu.h>
+#include <imx_rdc.h>
IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL31_COHERENT_RAM_START);
IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL31_COHERENT_RAM_END);
@@ -59,7 +61,6 @@
#define GPR_TZASC_EN (1 << 0)
#define GPR_TZASC_EN_LOCK (1 << 16)
-#if 1
void bl31_tzc380_setup(void)
{
unsigned int val;
@@ -121,17 +122,17 @@
mmio_write_32(0x32df004c, 0x0);
mmio_write_32(0x32df0050, 0x0);
}
-#endif
void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
u_register_t arg2, u_register_t arg3)
{
+#if !defined (CSU_RDC_TEST)
int i;
/* enable CSU NS access permission */
for (i = 0; i < 64; i++) {
mmio_write_32(0x303e0000 + i * 4, 0xffffffff);
}
-
+#endif
/* config the aips access permission */
imx8mm_aips_config();
@@ -158,6 +159,11 @@
bl33_image_ep_info.args.arg2 = 0x2000000;
#endif
bl31_tzc380_setup();
+
+#if defined (CSU_RDC_TEST)
+ csu_test();
+ rdc_test();
+#endif
}
void bl31_plat_arch_setup(void)
diff --git a/plat/imx/imx8mm/include/platform_def.h b/plat/imx/imx8mm/include/platform_def.h
index 9afe19a..28b8d06 100644
--- a/plat/imx/imx8mm/include/platform_def.h
+++ b/plat/imx/imx8mm/include/platform_def.h
@@ -65,6 +65,8 @@
#define IMX_ANAMIX_BASE 0x30360000
#define IMX_SRC_BASE 0x30390000
#define IMX_GPC_BASE 0x303a0000
+#define IMX_RDC_BASE 0x303d0000
+#define IMX_CSU_BASE 0x303e0000
#define IMX_WDOG_BASE 0x30280000
#define IMX_SNVS_BASE 0x30370000
#define IMX_NOC_BASE 0x32700000
diff --git a/plat/imx/imx8mm/platform.mk b/plat/imx/imx8mm/platform.mk
index 25b86f8..d40394d 100644
--- a/plat/imx/imx8mm/platform.mk
+++ b/plat/imx/imx8mm/platform.mk
@@ -17,6 +17,8 @@
plat/imx/imx8mm/gpc.c \
plat/imx/imx8mm/imx8mm_misc.c \
plat/imx/common/imx8m/hab.c \
+ plat/imx/common/imx8m/imx_csu.c \
+ plat/imx/common/imx8m/imx_rdc.c \
plat/imx/imx8mm/imx8mm_psci.c \
plat/imx/common/imx8_topology.c \
plat/common/plat_psci_common.c \
diff --git a/plat/imx/imx8mq/include/imx_csu.h b/plat/imx/imx8mq/include/imx_csu.h
deleted file mode 100644
index a4ae9ab..0000000
--- a/plat/imx/imx8mq/include/imx_csu.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * Copyright 2017 NXP
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef __IMX_CSU_H__
-#define __IMX_CSU_H__
-
-enum csu_mode {
- CSU_NSR = 0x08,
- CSU_NSW = 0x80,
- CSU_NSRW = 0x88,
- CSU_NUR = 0x04,
- CSU_NUW = 0x40,
- CSU_NURW = 0x44,
- CSU_SSR = 0x02,
- CSU_SSW = 0x20,
- CSU_SSRW = 0x22,
- CSU_SUR = 0x01,
- CSU_SUW = 0x10,
- CSU_SURW = 0x11,
- CSU_RW = 0xff,
-};
-
-enum csu_csln_idx {
- CSU_CSLn_GPIO1 = 0,
- CSU_CSLn_GPIO2 = 1,
- CSU_CSLn_GPIO3 = 2,
- CSU_CSLn_GPIO4 = 3,
- CSU_CSLn_GPIO5 = 4,
- CSU_CSLn_Reserved1 = 5,
- CSU_CSLn_ANA_TSENSOR = 6,
- CSU_CSLn_ANA_OSC = 7,
- CSU_CSLn_WDOG1 = 8,
- CSU_CSLn_WDOG2 = 9,
- CSU_CSLn_WDOG3 = 10,
- CSU_CSLn_Reserved2 = 11,
- CSU_CSLn_SDMA2 = 12,
- CSU_CSLn_GPT1 = 13,
- CSU_CSLn_GPT2 = 14,
- CSU_CSLn_GPT3 = 15,
- CSU_CSLn_Reserved3 = 16,
- CSU_CSLn_ROMCP = 17,
- CSU_CSLn_LCDIF = 18,
- CSU_CSLn_IOMUXC = 19,
- CSU_CSLn_IOMUXC_GPR = 20,
- CSU_CSLn_OCOTP_CTRL = 21,
- CSU_CSLn_ANATOP_PLL = 22,
- CSU_CSLn_SNVS_HP = 23,
- CSU_CSLn_CCM = 24,
- CSU_CSLn_SRC = 25,
- CSU_CSLn_GPC = 26,
- CSU_CSLn_SEMAPHORE1 = 27,
- CSU_CSLn_SEMAPHORE2 = 28,
- CSU_CSLn_RDC = 29,
- CSU_CSLn_CSU = 30,
- CSU_CSLn_Reserved4 = 31,
- CSU_CSLn_MST0 = 32,
- CSU_CSLn_MST1 = 33,
- CSU_CSLn_MST2 = 34,
- CSU_CSLn_MST3 = 35,
- CSU_CSLn_HDMI_SEC = 36,
- CSU_CSLn_Reserved5 = 37,
- CSU_CSLn_PWM1 = 38,
- CSU_CSLn_PWM2 = 39,
- CSU_CSLn_PWM3 = 40,
- CSU_CSLn_PWM4 = 41,
- CSU_CSLn_SysCounter_RD = 42,
- CSU_CSLn_SysCounter_CMP = 43,
- CSU_CSLn_SysCounter_CTRL = 44,
- CSU_CSLn_HDMI_CTRL = 45,
- CSU_CSLn_GPT6 = 46,
- CSU_CSLn_GPT5 = 47,
- CSU_CSLn_GPT4 = 48,
- CSU_CSLn_TZASC = 56,
- CSU_CSLn_MTR = 59,
- CSU_CSLn_PERFMON1 = 60,
- CSU_CSLn_PERFMON2 = 61,
- CSU_CSLn_PLATFORM_CTRL = 62,
- CSU_CSLn_QoSC = 63,
- CSU_CSLn_MIPI_PHY = 64,
- CSU_CSLn_MIPI_DSI = 65,
- CSU_CSLn_I2C1 = 66,
- CSU_CSLn_I2C2 = 67,
- CSU_CSLn_I2C3 = 68,
- CSU_CSLn_I2C4 = 69,
- CSU_CSLn_UART4 = 70,
- CSU_CSLn_MIPI_CSI1 = 71,
- CSU_CSLn_MIPI_CSI_PHY1 = 72,
- CSU_CSLn_CSI1 = 73,
- CSU_CSLn_MU_A = 74,
- CSU_CSLn_MU_B = 75,
- CSU_CSLn_SEMAPHORE_HS = 76,
- CSU_CSLn_Internal1 = 77,
- CSU_CSLn_SAI1 = 78,
- CSU_CSLn_Reserved7 = 79,
- CSU_CSLn_SAI6 = 80,
- CSU_CSLn_SAI5 = 81,
- CSU_CSLn_SAI4 = 82,
- CSU_CSLn_Internal2 = 83,
- CSU_CSLn_USDHC1 = 84,
- CSU_CSLn_USDHC2 = 85,
- CSU_CSLn_MIPI_CSI2 = 86,
- CSU_CSLn_MIPI_CSI_PHY2 = 87,
- CSU_CSLn_CSI2 = 88,
- CSU_CSLn_Internal3 = 89,
- CSU_CSLn_Reserved10 = 90,
- CSU_CSLn_QSPI = 91,
- CSU_CSLn_Reserved11 = 92,
- CSU_CSLn_SDMA1 = 93,
- CSU_CSLn_ENET1 = 94,
- CSU_CSLn_Reserved12 = 95,
- CSU_CSLn_Internal4 = 96,
- CSU_CSLn_SPDIF1 = 97,
- CSU_CSLn_ECSPI1 = 98,
- CSU_CSLn_ECSPI2 = 99,
- CSU_CSLn_ECSPI3 = 100,
- CSU_CSLn_Reserved14 = 101,
- CSU_CSLn_UART1 = 102,
- CSU_CSLn_Internal5 = 103,
- CSU_CSLn_UART3 = 104,
- CSU_CSLn_UART2 = 105,
- CSU_CSLn_SPDIF2 = 106,
- CSU_CSLn_SAI2 = 107,
- CSU_CSLn_SAI3 = 108,
- CSU_CSLn_Reserved16 = 109,
- CSU_CSLn_Internal6 = 110,
- CSU_CSLn_SPBA1 = 111,
- CSU_CSLn_MOD_EN3 = 112,
- CSU_CSLn_MOD_EN0 = 113,
- CSU_CSLn_CAAM = 114,
- CSU_CSLn_DDRC_SEC = 115,
- CSU_CSLn_GIC_EXSC = 116,
- CSU_CSLn_USB_EXSC = 117,
- CSU_CSLn_OCRAM_TZ = 118,
- CSU_CSLn_OCRAM_S_TZ = 119,
- CSU_CSLn_VPU_SEC = 120,
- CSU_CSLn_DAP_EXSC = 121,
- CSU_CSLn_ROMCP_SEC = 122,
- CSU_CSLn_APBHDMA_SEC = 123,
- CSU_CSLn_M4_SEC = 124,
- CSU_CSLn_QSPI_SEC = 125,
- CSU_CSLn_GPU_EXSC = 126,
- CSU_CSLn_PCIE = 127,
-};
-
-enum csu_hp_idx {
- CSU_HP_A53,
- CSU_HP_M4,
- CSU_HP_SDMA1,
- CSU_HP_CSI,
- CSU_HP_USB,
- CSU_HP_PCIE,
- CSU_HP_VPU,
- CSU_HP_GPU,
- CSU_HP_APBHDMA,
- CSU_HP_ENET,
- CSU_HP_USDHC1,
- CSU_HP_USDHC2,
- CSU_HP_DCSS,
- CSU_HP_HUGO,
- CSU_HP_DAP,
- CSU_HP_SDMA2,
- CSU_HP_CAAM,
-};
-
-enum csu_sa_idx {
- CSU_SA_M4,
- CSU_SA_SDMA1,
- CSU_SA_CSI,
- CSU_SA_USB,
- CSU_SA_PCIE,
- CSU_SA_VPU,
- CSU_SA_GPU,
- CSU_SA_APBHDMA,
- CSU_SA_ENET,
- CSU_SA_USDHC1,
- CSU_SA_USDHC2,
- CSU_SA_DCSS,
- CSU_SA_HUGO,
- CSU_SA_DAP,
- CSU_SA_SDMA2,
- CSU_SA_CAAM,
-};
-
-struct csu_slave_conf {
- enum csu_csln_idx index;
- uint16_t mode;
- uint16_t lock;
-};
-
-struct csu_sa_conf {
- enum csu_sa_idx index;
- uint8_t enable;
- uint8_t lock;
-};
-
-void csu_set_slave_index_mode(enum csu_csln_idx index,
- uint16_t mode, uint8_t lock);
-void csu_get_slave_index_mode(enum csu_csln_idx index,
- uint16_t *mode, uint8_t *lock);
-void csu_set_slaves_modes(struct csu_slave_conf *csu_config, uint32_t count);
-void csu_set_default_slaves_modes(void);
-void csu_set_hp_index_config(enum csu_hp_idx index, uint8_t enable,
- uint8_t set_control, uint8_t lock);
-void csu_set_sa_index_config(enum csu_sa_idx index, uint8_t enable,
- uint8_t lock);
-void csu_get_sa_index_config(enum csu_sa_idx index, uint8_t *enable,
- uint8_t *lock);
-void csu_set_sa_configs(struct csu_sa_conf *sa_configs, uint32_t count);
-void csu_set_default_secure_configs(void);
-
-#if defined (CSU_RDC_TEST)
-void csu_test(void);
-#endif
-#endif /* __IMX_CSU_H__ */
diff --git a/plat/imx/imx8mq/platform.mk b/plat/imx/imx8mq/platform.mk
index 1332f7d..498cae5 100644
--- a/plat/imx/imx8mq/platform.mk
+++ b/plat/imx/imx8mq/platform.mk
@@ -22,8 +22,8 @@
plat/imx/common/imx8_sip_svc.c \
plat/imx/common/misc.c \
plat/imx/imx8mq/imx8mq_psci.c \
- plat/imx/imx8mq/imx_csu.c \
- plat/imx/imx8mq/imx_rdc.c \
+ plat/imx/common/imx8m/imx_csu.c \
+ plat/imx/common/imx8m/imx_rdc.c \
plat/imx/common/imx8_topology.c \
plat/common/plat_psci_common.c \
lib/xlat_tables/aarch64/xlat_tables.c \
