| /* |
| * Copyright (c) 2018, ARM Limited and Contributors. All rights reserved. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| |
| /* |
| * ZynqMP system level PM-API functions for pin control. |
| */ |
| |
| #include <arch_helpers.h> |
| #include <platform.h> |
| #include <string.h> |
| #include "pm_api_pinctrl.h" |
| #include "pm_api_sys.h" |
| #include "pm_client.h" |
| #include "pm_common.h" |
| #include "pm_ipi.h" |
| |
| #define PINCTRL_FUNCTION_MASK U(0xFE) |
| #define PINCTRL_VOLTAGE_STATUS_MASK U(0x01) |
| #define NFUNCS_PER_PIN U(13) |
| #define PINCTRL_NUM_MIOS U(78) |
| #define MAX_PIN_PER_REG U(26) |
| #define PINCTRL_BANK_ADDR_STEP U(28) |
| |
| #define PINCTRL_DRVSTRN0_REG_OFFSET U(0) |
| #define PINCTRL_DRVSTRN1_REG_OFFSET U(4) |
| #define PINCTRL_SCHCMOS_REG_OFFSET U(8) |
| #define PINCTRL_PULLCTRL_REG_OFFSET U(12) |
| #define PINCTRL_PULLSTAT_REG_OFFSET U(16) |
| #define PINCTRL_SLEWCTRL_REG_OFFSET U(20) |
| #define PINCTRL_VOLTAGE_STAT_REG_OFFSET U(24) |
| |
| #define IOU_SLCR_BANK1_CTRL5 U(0XFF180164) |
| |
| #define PINCTRL_CFG_ADDR_OFFSET(addr, reg, miopin) \ |
| ((addr) + 4 * PINCTRL_NUM_MIOS + PINCTRL_BANK_ADDR_STEP * \ |
| ((miopin) / MAX_PIN_PER_REG) + (reg)) |
| |
| #define PINCTRL_PIN_OFFSET(_miopin) \ |
| ((_miopin) - (MAX_PIN_PER_REG * ((_miopin) / MAX_PIN_PER_REG))) |
| |
| #define PINCTRL_REGVAL_TO_PIN_CONFIG(_pin, _val) \ |
| (((_val) >> PINCTRL_PIN_OFFSET(_pin)) & 0x1) |
| |
| static uint8_t pm_pinctrl_mux[NFUNCS_PER_PIN] = { |
| 0x02, 0x04, 0x08, 0x10, 0x18, |
| 0x00, 0x20, 0x40, 0x60, 0x80, |
| 0xA0, 0xC0, 0xE0 |
| }; |
| |
| struct pinctrl_function { |
| char name[FUNCTION_NAME_LEN]; |
| uint16_t (*groups)[]; |
| uint8_t regval; |
| }; |
| |
| /* Max groups for one pin */ |
| #define MAX_PIN_GROUPS U(13) |
| |
| struct zynqmp_pin_group { |
| uint16_t (*groups)[]; |
| }; |
| |
| static struct pinctrl_function pinctrl_functions[MAX_FUNCTION] = { |
| [PINCTRL_FUNC_CAN0] = { |
| .name = "can0", |
| .regval = 0x20, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_CAN0_0, |
| PINCTRL_GRP_CAN0_1, |
| PINCTRL_GRP_CAN0_2, |
| PINCTRL_GRP_CAN0_3, |
| PINCTRL_GRP_CAN0_4, |
| PINCTRL_GRP_CAN0_5, |
| PINCTRL_GRP_CAN0_6, |
| PINCTRL_GRP_CAN0_7, |
| PINCTRL_GRP_CAN0_8, |
| PINCTRL_GRP_CAN0_9, |
| PINCTRL_GRP_CAN0_10, |
| PINCTRL_GRP_CAN0_11, |
| PINCTRL_GRP_CAN0_12, |
| PINCTRL_GRP_CAN0_13, |
| PINCTRL_GRP_CAN0_14, |
| PINCTRL_GRP_CAN0_15, |
| PINCTRL_GRP_CAN0_16, |
| PINCTRL_GRP_CAN0_17, |
| PINCTRL_GRP_CAN0_18, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_CAN1] = { |
| .name = "can1", |
| .regval = 0x20, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_CAN1_0, |
| PINCTRL_GRP_CAN1_1, |
| PINCTRL_GRP_CAN1_2, |
| PINCTRL_GRP_CAN1_3, |
| PINCTRL_GRP_CAN1_4, |
| PINCTRL_GRP_CAN1_5, |
| PINCTRL_GRP_CAN1_6, |
| PINCTRL_GRP_CAN1_7, |
| PINCTRL_GRP_CAN1_8, |
| PINCTRL_GRP_CAN1_9, |
| PINCTRL_GRP_CAN1_10, |
| PINCTRL_GRP_CAN1_11, |
| PINCTRL_GRP_CAN1_12, |
| PINCTRL_GRP_CAN1_13, |
| PINCTRL_GRP_CAN1_14, |
| PINCTRL_GRP_CAN1_15, |
| PINCTRL_GRP_CAN1_16, |
| PINCTRL_GRP_CAN1_17, |
| PINCTRL_GRP_CAN1_18, |
| PINCTRL_GRP_CAN1_19, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_ETHERNET0] = { |
| .name = "ethernet0", |
| .regval = 0x02, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_ETHERNET1] = { |
| .name = "ethernet1", |
| .regval = 0x02, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET1_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_ETHERNET2] = { |
| .name = "ethernet2", |
| .regval = 0x02, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET2_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_ETHERNET3] = { |
| .name = "ethernet3", |
| .regval = 0x02, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET3_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_GEMTSU0] = { |
| .name = "gemtsu0", |
| .regval = 0x02, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_GEMTSU0_0, |
| PINCTRL_GRP_GEMTSU0_1, |
| PINCTRL_GRP_GEMTSU0_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_GPIO0] = { |
| .name = "gpio0", |
| .regval = 0x00, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_GPIO0_0, |
| PINCTRL_GRP_GPIO0_1, |
| PINCTRL_GRP_GPIO0_2, |
| PINCTRL_GRP_GPIO0_3, |
| PINCTRL_GRP_GPIO0_4, |
| PINCTRL_GRP_GPIO0_5, |
| PINCTRL_GRP_GPIO0_6, |
| PINCTRL_GRP_GPIO0_7, |
| PINCTRL_GRP_GPIO0_8, |
| PINCTRL_GRP_GPIO0_9, |
| PINCTRL_GRP_GPIO0_10, |
| PINCTRL_GRP_GPIO0_11, |
| PINCTRL_GRP_GPIO0_12, |
| PINCTRL_GRP_GPIO0_13, |
| PINCTRL_GRP_GPIO0_14, |
| PINCTRL_GRP_GPIO0_15, |
| PINCTRL_GRP_GPIO0_16, |
| PINCTRL_GRP_GPIO0_17, |
| PINCTRL_GRP_GPIO0_18, |
| PINCTRL_GRP_GPIO0_19, |
| PINCTRL_GRP_GPIO0_20, |
| PINCTRL_GRP_GPIO0_21, |
| PINCTRL_GRP_GPIO0_22, |
| PINCTRL_GRP_GPIO0_23, |
| PINCTRL_GRP_GPIO0_24, |
| PINCTRL_GRP_GPIO0_25, |
| PINCTRL_GRP_GPIO0_26, |
| PINCTRL_GRP_GPIO0_27, |
| PINCTRL_GRP_GPIO0_28, |
| PINCTRL_GRP_GPIO0_29, |
| PINCTRL_GRP_GPIO0_30, |
| PINCTRL_GRP_GPIO0_31, |
| PINCTRL_GRP_GPIO0_32, |
| PINCTRL_GRP_GPIO0_33, |
| PINCTRL_GRP_GPIO0_34, |
| PINCTRL_GRP_GPIO0_35, |
| PINCTRL_GRP_GPIO0_36, |
| PINCTRL_GRP_GPIO0_37, |
| PINCTRL_GRP_GPIO0_38, |
| PINCTRL_GRP_GPIO0_39, |
| PINCTRL_GRP_GPIO0_40, |
| PINCTRL_GRP_GPIO0_41, |
| PINCTRL_GRP_GPIO0_42, |
| PINCTRL_GRP_GPIO0_43, |
| PINCTRL_GRP_GPIO0_44, |
| PINCTRL_GRP_GPIO0_45, |
| PINCTRL_GRP_GPIO0_46, |
| PINCTRL_GRP_GPIO0_47, |
| PINCTRL_GRP_GPIO0_48, |
| PINCTRL_GRP_GPIO0_49, |
| PINCTRL_GRP_GPIO0_50, |
| PINCTRL_GRP_GPIO0_51, |
| PINCTRL_GRP_GPIO0_52, |
| PINCTRL_GRP_GPIO0_53, |
| PINCTRL_GRP_GPIO0_54, |
| PINCTRL_GRP_GPIO0_55, |
| PINCTRL_GRP_GPIO0_56, |
| PINCTRL_GRP_GPIO0_57, |
| PINCTRL_GRP_GPIO0_58, |
| PINCTRL_GRP_GPIO0_59, |
| PINCTRL_GRP_GPIO0_60, |
| PINCTRL_GRP_GPIO0_61, |
| PINCTRL_GRP_GPIO0_62, |
| PINCTRL_GRP_GPIO0_63, |
| PINCTRL_GRP_GPIO0_64, |
| PINCTRL_GRP_GPIO0_65, |
| PINCTRL_GRP_GPIO0_66, |
| PINCTRL_GRP_GPIO0_67, |
| PINCTRL_GRP_GPIO0_68, |
| PINCTRL_GRP_GPIO0_69, |
| PINCTRL_GRP_GPIO0_70, |
| PINCTRL_GRP_GPIO0_71, |
| PINCTRL_GRP_GPIO0_72, |
| PINCTRL_GRP_GPIO0_73, |
| PINCTRL_GRP_GPIO0_74, |
| PINCTRL_GRP_GPIO0_75, |
| PINCTRL_GRP_GPIO0_76, |
| PINCTRL_GRP_GPIO0_77, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_I2C0] = { |
| .name = "i2c0", |
| .regval = 0x40, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_I2C0_0, |
| PINCTRL_GRP_I2C0_1, |
| PINCTRL_GRP_I2C0_2, |
| PINCTRL_GRP_I2C0_3, |
| PINCTRL_GRP_I2C0_4, |
| PINCTRL_GRP_I2C0_5, |
| PINCTRL_GRP_I2C0_6, |
| PINCTRL_GRP_I2C0_7, |
| PINCTRL_GRP_I2C0_8, |
| PINCTRL_GRP_I2C0_9, |
| PINCTRL_GRP_I2C0_10, |
| PINCTRL_GRP_I2C0_11, |
| PINCTRL_GRP_I2C0_12, |
| PINCTRL_GRP_I2C0_13, |
| PINCTRL_GRP_I2C0_14, |
| PINCTRL_GRP_I2C0_15, |
| PINCTRL_GRP_I2C0_16, |
| PINCTRL_GRP_I2C0_17, |
| PINCTRL_GRP_I2C0_18, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_I2C1] = { |
| .name = "i2c1", |
| .regval = 0x40, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_I2C1_0, |
| PINCTRL_GRP_I2C1_1, |
| PINCTRL_GRP_I2C1_2, |
| PINCTRL_GRP_I2C1_3, |
| PINCTRL_GRP_I2C1_4, |
| PINCTRL_GRP_I2C1_5, |
| PINCTRL_GRP_I2C1_6, |
| PINCTRL_GRP_I2C1_7, |
| PINCTRL_GRP_I2C1_8, |
| PINCTRL_GRP_I2C1_9, |
| PINCTRL_GRP_I2C1_10, |
| PINCTRL_GRP_I2C1_11, |
| PINCTRL_GRP_I2C1_12, |
| PINCTRL_GRP_I2C1_13, |
| PINCTRL_GRP_I2C1_14, |
| PINCTRL_GRP_I2C1_15, |
| PINCTRL_GRP_I2C1_16, |
| PINCTRL_GRP_I2C1_17, |
| PINCTRL_GRP_I2C1_18, |
| PINCTRL_GRP_I2C1_19, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_MDIO0] = { |
| .name = "mdio0", |
| .regval = 0x60, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_MDIO0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_MDIO1] = { |
| .name = "mdio1", |
| .regval = 0x80, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_MDIO1_0, |
| PINCTRL_GRP_MDIO1_1, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_MDIO2] = { |
| .name = "mdio2", |
| .regval = 0xa0, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_MDIO2_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_MDIO3] = { |
| .name = "mdio3", |
| .regval = 0xc0, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_MDIO3_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_QSPI0] = { |
| .name = "qspi0", |
| .regval = 0x02, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_QSPI0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_QSPI_FBCLK] = { |
| .name = "qspi_fbclk", |
| .regval = 0x02, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_QSPI_FBCLK, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_QSPI_SS] = { |
| .name = "qspi_ss", |
| .regval = 0x02, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_QSPI_SS, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_SPI0] = { |
| .name = "spi0", |
| .regval = 0x80, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_SPI0_0, |
| PINCTRL_GRP_SPI0_1, |
| PINCTRL_GRP_SPI0_2, |
| PINCTRL_GRP_SPI0_3, |
| PINCTRL_GRP_SPI0_4, |
| PINCTRL_GRP_SPI0_5, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_SPI1] = { |
| .name = "spi1", |
| .regval = 0x80, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_SPI1_0, |
| PINCTRL_GRP_SPI1_1, |
| PINCTRL_GRP_SPI1_2, |
| PINCTRL_GRP_SPI1_3, |
| PINCTRL_GRP_SPI1_4, |
| PINCTRL_GRP_SPI1_5, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_SPI0_SS] = { |
| .name = "spi0_ss", |
| .regval = 0x80, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_SPI0_0_SS0, |
| PINCTRL_GRP_SPI0_0_SS1, |
| PINCTRL_GRP_SPI0_0_SS2, |
| PINCTRL_GRP_SPI0_1_SS0, |
| PINCTRL_GRP_SPI0_1_SS1, |
| PINCTRL_GRP_SPI0_1_SS2, |
| PINCTRL_GRP_SPI0_2_SS0, |
| PINCTRL_GRP_SPI0_2_SS1, |
| PINCTRL_GRP_SPI0_2_SS2, |
| PINCTRL_GRP_SPI0_3_SS0, |
| PINCTRL_GRP_SPI0_3_SS1, |
| PINCTRL_GRP_SPI0_3_SS2, |
| PINCTRL_GRP_SPI0_4_SS0, |
| PINCTRL_GRP_SPI0_4_SS1, |
| PINCTRL_GRP_SPI0_4_SS2, |
| PINCTRL_GRP_SPI0_5_SS0, |
| PINCTRL_GRP_SPI0_5_SS1, |
| PINCTRL_GRP_SPI0_5_SS2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_SPI1_SS] = { |
| .name = "spi1_ss", |
| .regval = 0x80, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_SPI1_0_SS0, |
| PINCTRL_GRP_SPI1_0_SS1, |
| PINCTRL_GRP_SPI1_0_SS2, |
| PINCTRL_GRP_SPI1_1_SS0, |
| PINCTRL_GRP_SPI1_1_SS1, |
| PINCTRL_GRP_SPI1_1_SS2, |
| PINCTRL_GRP_SPI1_2_SS0, |
| PINCTRL_GRP_SPI1_2_SS1, |
| PINCTRL_GRP_SPI1_2_SS2, |
| PINCTRL_GRP_SPI1_3_SS0, |
| PINCTRL_GRP_SPI1_3_SS1, |
| PINCTRL_GRP_SPI1_3_SS2, |
| PINCTRL_GRP_SPI1_4_SS0, |
| PINCTRL_GRP_SPI1_4_SS1, |
| PINCTRL_GRP_SPI1_4_SS2, |
| PINCTRL_GRP_SPI1_5_SS0, |
| PINCTRL_GRP_SPI1_5_SS1, |
| PINCTRL_GRP_SPI1_5_SS2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_SDIO0] = { |
| .name = "sdio0", |
| .regval = 0x08, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_SDIO0_0, |
| PINCTRL_GRP_SDIO0_1, |
| PINCTRL_GRP_SDIO0_2, |
| PINCTRL_GRP_SDIO0_4BIT_0_0, |
| PINCTRL_GRP_SDIO0_4BIT_0_1, |
| PINCTRL_GRP_SDIO0_4BIT_1_0, |
| PINCTRL_GRP_SDIO0_4BIT_1_1, |
| PINCTRL_GRP_SDIO0_4BIT_2_0, |
| PINCTRL_GRP_SDIO0_4BIT_2_1, |
| PINCTRL_GRP_SDIO0_1BIT_0_0, |
| PINCTRL_GRP_SDIO0_1BIT_0_1, |
| PINCTRL_GRP_SDIO0_1BIT_0_2, |
| PINCTRL_GRP_SDIO0_1BIT_0_3, |
| PINCTRL_GRP_SDIO0_1BIT_0_4, |
| PINCTRL_GRP_SDIO0_1BIT_0_5, |
| PINCTRL_GRP_SDIO0_1BIT_0_6, |
| PINCTRL_GRP_SDIO0_1BIT_0_7, |
| PINCTRL_GRP_SDIO0_1BIT_1_0, |
| PINCTRL_GRP_SDIO0_1BIT_1_1, |
| PINCTRL_GRP_SDIO0_1BIT_1_2, |
| PINCTRL_GRP_SDIO0_1BIT_1_3, |
| PINCTRL_GRP_SDIO0_1BIT_1_4, |
| PINCTRL_GRP_SDIO0_1BIT_1_5, |
| PINCTRL_GRP_SDIO0_1BIT_1_6, |
| PINCTRL_GRP_SDIO0_1BIT_1_7, |
| PINCTRL_GRP_SDIO0_1BIT_2_0, |
| PINCTRL_GRP_SDIO0_1BIT_2_1, |
| PINCTRL_GRP_SDIO0_1BIT_2_2, |
| PINCTRL_GRP_SDIO0_1BIT_2_3, |
| PINCTRL_GRP_SDIO0_1BIT_2_4, |
| PINCTRL_GRP_SDIO0_1BIT_2_5, |
| PINCTRL_GRP_SDIO0_1BIT_2_6, |
| PINCTRL_GRP_SDIO0_1BIT_2_7, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_SDIO0_PC] = { |
| .name = "sdio0_pc", |
| .regval = 0x08, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_SDIO0_0_PC, |
| PINCTRL_GRP_SDIO0_1_PC, |
| PINCTRL_GRP_SDIO0_2_PC, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_SDIO0_CD] = { |
| .name = "sdio0_cd", |
| .regval = 0x08, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_SDIO0_0_CD, |
| PINCTRL_GRP_SDIO0_1_CD, |
| PINCTRL_GRP_SDIO0_2_CD, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_SDIO0_WP] = { |
| .name = "sdio0_wp", |
| .regval = 0x08, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_SDIO0_0_WP, |
| PINCTRL_GRP_SDIO0_1_WP, |
| PINCTRL_GRP_SDIO0_2_WP, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_SDIO1] = { |
| .name = "sdio1", |
| .regval = 0x10, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_SDIO1_0, |
| PINCTRL_GRP_SDIO1_4BIT_0_0, |
| PINCTRL_GRP_SDIO1_4BIT_0_1, |
| PINCTRL_GRP_SDIO1_4BIT_1_0, |
| PINCTRL_GRP_SDIO1_1BIT_0_0, |
| PINCTRL_GRP_SDIO1_1BIT_0_1, |
| PINCTRL_GRP_SDIO1_1BIT_0_2, |
| PINCTRL_GRP_SDIO1_1BIT_0_3, |
| PINCTRL_GRP_SDIO1_1BIT_0_4, |
| PINCTRL_GRP_SDIO1_1BIT_0_5, |
| PINCTRL_GRP_SDIO1_1BIT_0_6, |
| PINCTRL_GRP_SDIO1_1BIT_0_7, |
| PINCTRL_GRP_SDIO1_1BIT_1_0, |
| PINCTRL_GRP_SDIO1_1BIT_1_1, |
| PINCTRL_GRP_SDIO1_1BIT_1_2, |
| PINCTRL_GRP_SDIO1_1BIT_1_3, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_SDIO1_PC] = { |
| .name = "sdio1_pc", |
| .regval = 0x10, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_SDIO1_0_PC, |
| PINCTRL_GRP_SDIO1_1_PC, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_SDIO1_CD] = { |
| .name = "sdio1_cd", |
| .regval = 0x10, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_SDIO1_0_CD, |
| PINCTRL_GRP_SDIO1_1_CD, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_SDIO1_WP] = { |
| .name = "sdio1_wp", |
| .regval = 0x10, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_SDIO1_0_WP, |
| PINCTRL_GRP_SDIO1_1_WP, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_NAND0] = { |
| .name = "nand0", |
| .regval = 0x04, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_NAND0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_NAND0_CE] = { |
| .name = "nand0_ce", |
| .regval = 0x04, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_NAND0_0_CE, |
| PINCTRL_GRP_NAND0_1_CE, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_NAND0_RB] = { |
| .name = "nand0_rb", |
| .regval = 0x04, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_NAND0_0_RB, |
| PINCTRL_GRP_NAND0_1_RB, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_NAND0_DQS] = { |
| .name = "nand0_dqs", |
| .regval = 0x04, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_NAND0_0_DQS, |
| PINCTRL_GRP_NAND0_1_DQS, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_TTC0_CLK] = { |
| .name = "ttc0_clk", |
| .regval = 0xa0, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_TTC0_0_CLK, |
| PINCTRL_GRP_TTC0_1_CLK, |
| PINCTRL_GRP_TTC0_2_CLK, |
| PINCTRL_GRP_TTC0_3_CLK, |
| PINCTRL_GRP_TTC0_4_CLK, |
| PINCTRL_GRP_TTC0_5_CLK, |
| PINCTRL_GRP_TTC0_6_CLK, |
| PINCTRL_GRP_TTC0_7_CLK, |
| PINCTRL_GRP_TTC0_8_CLK, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_TTC0_WAV] = { |
| .name = "ttc0_wav", |
| .regval = 0xa0, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_TTC0_0_WAV, |
| PINCTRL_GRP_TTC0_1_WAV, |
| PINCTRL_GRP_TTC0_2_WAV, |
| PINCTRL_GRP_TTC0_3_WAV, |
| PINCTRL_GRP_TTC0_4_WAV, |
| PINCTRL_GRP_TTC0_5_WAV, |
| PINCTRL_GRP_TTC0_6_WAV, |
| PINCTRL_GRP_TTC0_7_WAV, |
| PINCTRL_GRP_TTC0_8_WAV, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_TTC1_CLK] = { |
| .name = "ttc1_clk", |
| .regval = 0xa0, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_TTC1_0_CLK, |
| PINCTRL_GRP_TTC1_1_CLK, |
| PINCTRL_GRP_TTC1_2_CLK, |
| PINCTRL_GRP_TTC1_3_CLK, |
| PINCTRL_GRP_TTC1_4_CLK, |
| PINCTRL_GRP_TTC1_5_CLK, |
| PINCTRL_GRP_TTC1_6_CLK, |
| PINCTRL_GRP_TTC1_7_CLK, |
| PINCTRL_GRP_TTC1_8_CLK, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_TTC1_WAV] = { |
| .name = "ttc1_wav", |
| .regval = 0xa0, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_TTC1_0_WAV, |
| PINCTRL_GRP_TTC1_1_WAV, |
| PINCTRL_GRP_TTC1_2_WAV, |
| PINCTRL_GRP_TTC1_3_WAV, |
| PINCTRL_GRP_TTC1_4_WAV, |
| PINCTRL_GRP_TTC1_5_WAV, |
| PINCTRL_GRP_TTC1_6_WAV, |
| PINCTRL_GRP_TTC1_7_WAV, |
| PINCTRL_GRP_TTC1_8_WAV, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_TTC2_CLK] = { |
| .name = "ttc2_clk", |
| .regval = 0xa0, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_TTC2_0_CLK, |
| PINCTRL_GRP_TTC2_1_CLK, |
| PINCTRL_GRP_TTC2_2_CLK, |
| PINCTRL_GRP_TTC2_3_CLK, |
| PINCTRL_GRP_TTC2_4_CLK, |
| PINCTRL_GRP_TTC2_5_CLK, |
| PINCTRL_GRP_TTC2_6_CLK, |
| PINCTRL_GRP_TTC2_7_CLK, |
| PINCTRL_GRP_TTC2_8_CLK, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_TTC2_WAV] = { |
| .name = "ttc2_wav", |
| .regval = 0xa0, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_TTC2_0_WAV, |
| PINCTRL_GRP_TTC2_1_WAV, |
| PINCTRL_GRP_TTC2_2_WAV, |
| PINCTRL_GRP_TTC2_3_WAV, |
| PINCTRL_GRP_TTC2_4_WAV, |
| PINCTRL_GRP_TTC2_5_WAV, |
| PINCTRL_GRP_TTC2_6_WAV, |
| PINCTRL_GRP_TTC2_7_WAV, |
| PINCTRL_GRP_TTC2_8_WAV, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_TTC3_CLK] = { |
| .name = "ttc3_clk", |
| .regval = 0xa0, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_TTC3_0_CLK, |
| PINCTRL_GRP_TTC3_1_CLK, |
| PINCTRL_GRP_TTC3_2_CLK, |
| PINCTRL_GRP_TTC3_3_CLK, |
| PINCTRL_GRP_TTC3_4_CLK, |
| PINCTRL_GRP_TTC3_5_CLK, |
| PINCTRL_GRP_TTC3_6_CLK, |
| PINCTRL_GRP_TTC3_7_CLK, |
| PINCTRL_GRP_TTC3_8_CLK, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_TTC3_WAV] = { |
| .name = "ttc3_wav", |
| .regval = 0xa0, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_TTC3_0_WAV, |
| PINCTRL_GRP_TTC3_1_WAV, |
| PINCTRL_GRP_TTC3_2_WAV, |
| PINCTRL_GRP_TTC3_3_WAV, |
| PINCTRL_GRP_TTC3_4_WAV, |
| PINCTRL_GRP_TTC3_5_WAV, |
| PINCTRL_GRP_TTC3_6_WAV, |
| PINCTRL_GRP_TTC3_7_WAV, |
| PINCTRL_GRP_TTC3_8_WAV, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_UART0] = { |
| .name = "uart0", |
| .regval = 0xc0, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_UART0_0, |
| PINCTRL_GRP_UART0_1, |
| PINCTRL_GRP_UART0_2, |
| PINCTRL_GRP_UART0_3, |
| PINCTRL_GRP_UART0_4, |
| PINCTRL_GRP_UART0_5, |
| PINCTRL_GRP_UART0_6, |
| PINCTRL_GRP_UART0_7, |
| PINCTRL_GRP_UART0_8, |
| PINCTRL_GRP_UART0_9, |
| PINCTRL_GRP_UART0_10, |
| PINCTRL_GRP_UART0_11, |
| PINCTRL_GRP_UART0_12, |
| PINCTRL_GRP_UART0_13, |
| PINCTRL_GRP_UART0_14, |
| PINCTRL_GRP_UART0_15, |
| PINCTRL_GRP_UART0_16, |
| PINCTRL_GRP_UART0_17, |
| PINCTRL_GRP_UART0_18, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_UART1] = { |
| .name = "uart1", |
| .regval = 0xc0, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_UART1_0, |
| PINCTRL_GRP_UART1_1, |
| PINCTRL_GRP_UART1_2, |
| PINCTRL_GRP_UART1_3, |
| PINCTRL_GRP_UART1_4, |
| PINCTRL_GRP_UART1_5, |
| PINCTRL_GRP_UART1_6, |
| PINCTRL_GRP_UART1_7, |
| PINCTRL_GRP_UART1_8, |
| PINCTRL_GRP_UART1_9, |
| PINCTRL_GRP_UART1_10, |
| PINCTRL_GRP_UART1_11, |
| PINCTRL_GRP_UART1_12, |
| PINCTRL_GRP_UART1_13, |
| PINCTRL_GRP_UART1_14, |
| PINCTRL_GRP_UART1_15, |
| PINCTRL_GRP_UART1_16, |
| PINCTRL_GRP_UART1_17, |
| PINCTRL_GRP_UART1_18, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_USB0] = { |
| .name = "usb0", |
| .regval = 0x04, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_USB0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_USB1] = { |
| .name = "usb1", |
| .regval = 0x04, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_USB1_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_SWDT0_CLK] = { |
| .name = "swdt0_clk", |
| .regval = 0x60, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_SWDT0_0_CLK, |
| PINCTRL_GRP_SWDT0_1_CLK, |
| PINCTRL_GRP_SWDT0_2_CLK, |
| PINCTRL_GRP_SWDT0_3_CLK, |
| PINCTRL_GRP_SWDT0_4_CLK, |
| PINCTRL_GRP_SWDT0_5_CLK, |
| PINCTRL_GRP_SWDT0_6_CLK, |
| PINCTRL_GRP_SWDT0_7_CLK, |
| PINCTRL_GRP_SWDT0_8_CLK, |
| PINCTRL_GRP_SWDT0_9_CLK, |
| PINCTRL_GRP_SWDT0_10_CLK, |
| PINCTRL_GRP_SWDT0_11_CLK, |
| PINCTRL_GRP_SWDT0_12_CLK, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_SWDT0_RST] = { |
| .name = "swdt0_rst", |
| .regval = 0x60, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_SWDT0_0_RST, |
| PINCTRL_GRP_SWDT0_1_RST, |
| PINCTRL_GRP_SWDT0_2_RST, |
| PINCTRL_GRP_SWDT0_3_RST, |
| PINCTRL_GRP_SWDT0_4_RST, |
| PINCTRL_GRP_SWDT0_5_RST, |
| PINCTRL_GRP_SWDT0_6_RST, |
| PINCTRL_GRP_SWDT0_7_RST, |
| PINCTRL_GRP_SWDT0_8_RST, |
| PINCTRL_GRP_SWDT0_9_RST, |
| PINCTRL_GRP_SWDT0_10_RST, |
| PINCTRL_GRP_SWDT0_11_RST, |
| PINCTRL_GRP_SWDT0_12_RST, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_SWDT1_CLK] = { |
| .name = "swdt1_clk", |
| .regval = 0x60, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_SWDT1_0_CLK, |
| PINCTRL_GRP_SWDT1_1_CLK, |
| PINCTRL_GRP_SWDT1_2_CLK, |
| PINCTRL_GRP_SWDT1_3_CLK, |
| PINCTRL_GRP_SWDT1_4_CLK, |
| PINCTRL_GRP_SWDT1_5_CLK, |
| PINCTRL_GRP_SWDT1_6_CLK, |
| PINCTRL_GRP_SWDT1_7_CLK, |
| PINCTRL_GRP_SWDT1_8_CLK, |
| PINCTRL_GRP_SWDT1_9_CLK, |
| PINCTRL_GRP_SWDT1_10_CLK, |
| PINCTRL_GRP_SWDT1_11_CLK, |
| PINCTRL_GRP_SWDT1_12_CLK, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_SWDT1_RST] = { |
| .name = "swdt1_rst", |
| .regval = 0x60, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_SWDT1_0_RST, |
| PINCTRL_GRP_SWDT1_1_RST, |
| PINCTRL_GRP_SWDT1_2_RST, |
| PINCTRL_GRP_SWDT1_3_RST, |
| PINCTRL_GRP_SWDT1_4_RST, |
| PINCTRL_GRP_SWDT1_5_RST, |
| PINCTRL_GRP_SWDT1_6_RST, |
| PINCTRL_GRP_SWDT1_7_RST, |
| PINCTRL_GRP_SWDT1_8_RST, |
| PINCTRL_GRP_SWDT1_9_RST, |
| PINCTRL_GRP_SWDT1_10_RST, |
| PINCTRL_GRP_SWDT1_11_RST, |
| PINCTRL_GRP_SWDT1_12_RST, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_PMU0] = { |
| .name = "pmu0", |
| .regval = 0x08, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_PMU0_0, |
| PINCTRL_GRP_PMU0_1, |
| PINCTRL_GRP_PMU0_2, |
| PINCTRL_GRP_PMU0_3, |
| PINCTRL_GRP_PMU0_4, |
| PINCTRL_GRP_PMU0_5, |
| PINCTRL_GRP_PMU0_6, |
| PINCTRL_GRP_PMU0_7, |
| PINCTRL_GRP_PMU0_8, |
| PINCTRL_GRP_PMU0_9, |
| PINCTRL_GRP_PMU0_10, |
| PINCTRL_GRP_PMU0_11, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_PCIE0] = { |
| .name = "pcie0", |
| .regval = 0x04, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_PCIE0_0, |
| PINCTRL_GRP_PCIE0_1, |
| PINCTRL_GRP_PCIE0_2, |
| PINCTRL_GRP_PCIE0_3, |
| PINCTRL_GRP_PCIE0_4, |
| PINCTRL_GRP_PCIE0_5, |
| PINCTRL_GRP_PCIE0_6, |
| PINCTRL_GRP_PCIE0_7, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_CSU0] = { |
| .name = "csu0", |
| .regval = 0x18, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_CSU0_0, |
| PINCTRL_GRP_CSU0_1, |
| PINCTRL_GRP_CSU0_2, |
| PINCTRL_GRP_CSU0_3, |
| PINCTRL_GRP_CSU0_4, |
| PINCTRL_GRP_CSU0_5, |
| PINCTRL_GRP_CSU0_6, |
| PINCTRL_GRP_CSU0_7, |
| PINCTRL_GRP_CSU0_8, |
| PINCTRL_GRP_CSU0_9, |
| PINCTRL_GRP_CSU0_10, |
| PINCTRL_GRP_CSU0_11, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_DPAUX0] = { |
| .name = "dpaux0", |
| .regval = 0x18, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_DPAUX0_0, |
| PINCTRL_GRP_DPAUX0_1, |
| PINCTRL_GRP_DPAUX0_2, |
| PINCTRL_GRP_DPAUX0_3, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_PJTAG0] = { |
| .name = "pjtag0", |
| .regval = 0x60, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_PJTAG0_0, |
| PINCTRL_GRP_PJTAG0_1, |
| PINCTRL_GRP_PJTAG0_2, |
| PINCTRL_GRP_PJTAG0_3, |
| PINCTRL_GRP_PJTAG0_4, |
| PINCTRL_GRP_PJTAG0_5, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_TRACE0] = { |
| .name = "trace0", |
| .regval = 0xe0, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_TRACE0_0, |
| PINCTRL_GRP_TRACE0_1, |
| PINCTRL_GRP_TRACE0_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_TRACE0_CLK] = { |
| .name = "trace0_clk", |
| .regval = 0xe0, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_TRACE0_0_CLK, |
| PINCTRL_GRP_TRACE0_1_CLK, |
| PINCTRL_GRP_TRACE0_2_CLK, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_FUNC_TESTSCAN0] = { |
| .name = "testscan0", |
| .regval = 0x10, |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_TESTSCAN0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| }; |
| |
| static struct zynqmp_pin_group zynqmp_pin_groups[MAX_PIN] = { |
| [PINCTRL_PIN_0] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_QSPI0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_0, |
| PINCTRL_GRP_CAN1_0, |
| PINCTRL_GRP_I2C1_0, |
| PINCTRL_GRP_PJTAG0_0, |
| PINCTRL_GRP_SPI0_0, |
| PINCTRL_GRP_TTC3_0_CLK, |
| PINCTRL_GRP_UART1_0, |
| PINCTRL_GRP_TRACE0_0_CLK, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_1] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_QSPI0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_1, |
| PINCTRL_GRP_CAN1_0, |
| PINCTRL_GRP_I2C1_0, |
| PINCTRL_GRP_PJTAG0_0, |
| PINCTRL_GRP_SPI0_0_SS2, |
| PINCTRL_GRP_TTC3_0_WAV, |
| PINCTRL_GRP_UART1_0, |
| PINCTRL_GRP_TRACE0_0_CLK, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_2] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_QSPI0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_2, |
| PINCTRL_GRP_CAN0_0, |
| PINCTRL_GRP_I2C0_0, |
| PINCTRL_GRP_PJTAG0_0, |
| PINCTRL_GRP_SPI0_0_SS1, |
| PINCTRL_GRP_TTC2_0_CLK, |
| PINCTRL_GRP_UART0_0, |
| PINCTRL_GRP_TRACE0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_3] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_QSPI0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_3, |
| PINCTRL_GRP_CAN0_0, |
| PINCTRL_GRP_I2C0_0, |
| PINCTRL_GRP_PJTAG0_0, |
| PINCTRL_GRP_SPI0_0_SS0, |
| PINCTRL_GRP_TTC2_0_WAV, |
| PINCTRL_GRP_UART0_0, |
| PINCTRL_GRP_TRACE0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_4] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_QSPI0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_4, |
| PINCTRL_GRP_CAN1_1, |
| PINCTRL_GRP_I2C1_1, |
| PINCTRL_GRP_SWDT1_0_CLK, |
| PINCTRL_GRP_SPI0_0, |
| PINCTRL_GRP_TTC1_0_CLK, |
| PINCTRL_GRP_UART1_1, |
| PINCTRL_GRP_TRACE0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_5] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_QSPI_SS, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_5, |
| PINCTRL_GRP_CAN1_1, |
| PINCTRL_GRP_I2C1_1, |
| PINCTRL_GRP_SWDT1_0_RST, |
| PINCTRL_GRP_SPI0_0, |
| PINCTRL_GRP_TTC1_0_WAV, |
| PINCTRL_GRP_UART1_1, |
| PINCTRL_GRP_TRACE0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_6] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_QSPI_FBCLK, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_6, |
| PINCTRL_GRP_CAN0_1, |
| PINCTRL_GRP_I2C0_1, |
| PINCTRL_GRP_SWDT0_0_CLK, |
| PINCTRL_GRP_SPI1_0, |
| PINCTRL_GRP_TTC0_0_CLK, |
| PINCTRL_GRP_UART0_1, |
| PINCTRL_GRP_TRACE0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_7] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_QSPI_SS, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_7, |
| PINCTRL_GRP_CAN0_1, |
| PINCTRL_GRP_I2C0_1, |
| PINCTRL_GRP_SWDT0_0_RST, |
| PINCTRL_GRP_SPI1_0_SS2, |
| PINCTRL_GRP_TTC0_0_WAV, |
| PINCTRL_GRP_UART0_1, |
| PINCTRL_GRP_TRACE0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_8] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_QSPI0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_8, |
| PINCTRL_GRP_CAN1_2, |
| PINCTRL_GRP_I2C1_2, |
| PINCTRL_GRP_SWDT1_1_CLK, |
| PINCTRL_GRP_SPI1_0_SS1, |
| PINCTRL_GRP_TTC3_1_CLK, |
| PINCTRL_GRP_UART1_2, |
| PINCTRL_GRP_TRACE0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_9] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_QSPI0_0, |
| PINCTRL_GRP_NAND0_0_CE, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_9, |
| PINCTRL_GRP_CAN1_2, |
| PINCTRL_GRP_I2C1_2, |
| PINCTRL_GRP_SWDT1_1_RST, |
| PINCTRL_GRP_SPI1_0_SS0, |
| PINCTRL_GRP_TTC3_1_WAV, |
| PINCTRL_GRP_UART1_2, |
| PINCTRL_GRP_TRACE0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_10] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_QSPI0_0, |
| PINCTRL_GRP_NAND0_0_RB, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_10, |
| PINCTRL_GRP_CAN0_2, |
| PINCTRL_GRP_I2C0_2, |
| PINCTRL_GRP_SWDT0_1_CLK, |
| PINCTRL_GRP_SPI1_0, |
| PINCTRL_GRP_TTC2_1_CLK, |
| PINCTRL_GRP_UART0_2, |
| PINCTRL_GRP_TRACE0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_11] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_QSPI0_0, |
| PINCTRL_GRP_NAND0_0_RB, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_11, |
| PINCTRL_GRP_CAN0_2, |
| PINCTRL_GRP_I2C0_2, |
| PINCTRL_GRP_SWDT0_1_RST, |
| PINCTRL_GRP_SPI1_0, |
| PINCTRL_GRP_TTC2_1_WAV, |
| PINCTRL_GRP_UART0_2, |
| PINCTRL_GRP_TRACE0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_12] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_QSPI0_0, |
| PINCTRL_GRP_NAND0_0_DQS, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_12, |
| PINCTRL_GRP_CAN1_3, |
| PINCTRL_GRP_I2C1_3, |
| PINCTRL_GRP_PJTAG0_1, |
| PINCTRL_GRP_SPI0_1, |
| PINCTRL_GRP_TTC1_1_CLK, |
| PINCTRL_GRP_UART1_3, |
| PINCTRL_GRP_TRACE0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_13] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_NAND0_0, |
| PINCTRL_GRP_SDIO0_0, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_13, |
| PINCTRL_GRP_CAN1_3, |
| PINCTRL_GRP_I2C1_3, |
| PINCTRL_GRP_PJTAG0_1, |
| PINCTRL_GRP_SPI0_1_SS2, |
| PINCTRL_GRP_TTC1_1_WAV, |
| PINCTRL_GRP_UART1_3, |
| PINCTRL_GRP_TRACE0_0, |
| PINCTRL_GRP_SDIO0_4BIT_0_0, |
| PINCTRL_GRP_SDIO0_1BIT_0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_14] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_NAND0_0, |
| PINCTRL_GRP_SDIO0_0, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_14, |
| PINCTRL_GRP_CAN0_3, |
| PINCTRL_GRP_I2C0_3, |
| PINCTRL_GRP_PJTAG0_1, |
| PINCTRL_GRP_SPI0_1_SS1, |
| PINCTRL_GRP_TTC0_1_CLK, |
| PINCTRL_GRP_UART0_3, |
| PINCTRL_GRP_TRACE0_0, |
| PINCTRL_GRP_SDIO0_4BIT_0_0, |
| PINCTRL_GRP_SDIO0_1BIT_0_1, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_15] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_NAND0_0, |
| PINCTRL_GRP_SDIO0_0, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_15, |
| PINCTRL_GRP_CAN0_3, |
| PINCTRL_GRP_I2C0_3, |
| PINCTRL_GRP_PJTAG0_1, |
| PINCTRL_GRP_SPI0_1_SS0, |
| PINCTRL_GRP_TTC0_1_WAV, |
| PINCTRL_GRP_UART0_3, |
| PINCTRL_GRP_TRACE0_0, |
| PINCTRL_GRP_SDIO0_4BIT_0_0, |
| PINCTRL_GRP_SDIO0_1BIT_0_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_16] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_NAND0_0, |
| PINCTRL_GRP_SDIO0_0, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_16, |
| PINCTRL_GRP_CAN1_4, |
| PINCTRL_GRP_I2C1_4, |
| PINCTRL_GRP_SWDT1_2_CLK, |
| PINCTRL_GRP_SPI0_1, |
| PINCTRL_GRP_TTC3_2_CLK, |
| PINCTRL_GRP_UART1_4, |
| PINCTRL_GRP_TRACE0_0, |
| PINCTRL_GRP_SDIO0_4BIT_0_0, |
| PINCTRL_GRP_SDIO0_1BIT_0_3, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_17] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_NAND0_0, |
| PINCTRL_GRP_SDIO0_0, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_17, |
| PINCTRL_GRP_CAN1_4, |
| PINCTRL_GRP_I2C1_4, |
| PINCTRL_GRP_SWDT1_2_RST, |
| PINCTRL_GRP_SPI0_1, |
| PINCTRL_GRP_TTC3_2_WAV, |
| PINCTRL_GRP_UART1_4, |
| PINCTRL_GRP_TRACE0_0, |
| PINCTRL_GRP_SDIO0_4BIT_0_1, |
| PINCTRL_GRP_SDIO0_1BIT_0_4, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_18] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_NAND0_0, |
| PINCTRL_GRP_SDIO0_0, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_CSU0_0, |
| PINCTRL_GRP_GPIO0_18, |
| PINCTRL_GRP_CAN0_4, |
| PINCTRL_GRP_I2C0_4, |
| PINCTRL_GRP_SWDT0_2_CLK, |
| PINCTRL_GRP_SPI1_1, |
| PINCTRL_GRP_TTC2_2_CLK, |
| PINCTRL_GRP_UART0_4, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_4BIT_0_1, |
| PINCTRL_GRP_SDIO0_1BIT_0_5, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_19] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_NAND0_0, |
| PINCTRL_GRP_SDIO0_0, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_CSU0_1, |
| PINCTRL_GRP_GPIO0_19, |
| PINCTRL_GRP_CAN0_4, |
| PINCTRL_GRP_I2C0_4, |
| PINCTRL_GRP_SWDT0_2_RST, |
| PINCTRL_GRP_SPI1_1_SS2, |
| PINCTRL_GRP_TTC2_2_WAV, |
| PINCTRL_GRP_UART0_4, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_4BIT_0_1, |
| PINCTRL_GRP_SDIO0_1BIT_0_6, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_20] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_NAND0_0, |
| PINCTRL_GRP_SDIO0_0, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_CSU0_2, |
| PINCTRL_GRP_GPIO0_20, |
| PINCTRL_GRP_CAN1_5, |
| PINCTRL_GRP_I2C1_5, |
| PINCTRL_GRP_SWDT1_3_CLK, |
| PINCTRL_GRP_SPI1_1_SS1, |
| PINCTRL_GRP_TTC1_2_CLK, |
| PINCTRL_GRP_UART1_5, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_4BIT_0_1, |
| PINCTRL_GRP_SDIO0_1BIT_0_7, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_21] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_NAND0_0, |
| PINCTRL_GRP_SDIO0_0, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_CSU0_3, |
| PINCTRL_GRP_GPIO0_21, |
| PINCTRL_GRP_CAN1_5, |
| PINCTRL_GRP_I2C1_5, |
| PINCTRL_GRP_SWDT1_3_RST, |
| PINCTRL_GRP_SPI1_1_SS0, |
| PINCTRL_GRP_TTC1_2_WAV, |
| PINCTRL_GRP_UART1_5, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_4BIT_0_0, |
| PINCTRL_GRP_SDIO0_4BIT_0_1, |
| PINCTRL_GRP_SDIO0_1BIT_0_0, |
| PINCTRL_GRP_SDIO0_1BIT_0_1, |
| PINCTRL_GRP_SDIO0_1BIT_0_2, |
| PINCTRL_GRP_SDIO0_1BIT_0_3, |
| PINCTRL_GRP_SDIO0_1BIT_0_4, |
| PINCTRL_GRP_SDIO0_1BIT_0_5, |
| PINCTRL_GRP_SDIO0_1BIT_0_6, |
| PINCTRL_GRP_SDIO0_1BIT_0_7, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_22] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_NAND0_0, |
| PINCTRL_GRP_SDIO0_0, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_CSU0_4, |
| PINCTRL_GRP_GPIO0_22, |
| PINCTRL_GRP_CAN0_5, |
| PINCTRL_GRP_I2C0_5, |
| PINCTRL_GRP_SWDT0_3_CLK, |
| PINCTRL_GRP_SPI1_1, |
| PINCTRL_GRP_TTC0_2_CLK, |
| PINCTRL_GRP_UART0_5, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_4BIT_0_0, |
| PINCTRL_GRP_SDIO0_4BIT_0_1, |
| PINCTRL_GRP_SDIO0_1BIT_0_0, |
| PINCTRL_GRP_SDIO0_1BIT_0_1, |
| PINCTRL_GRP_SDIO0_1BIT_0_2, |
| PINCTRL_GRP_SDIO0_1BIT_0_3, |
| PINCTRL_GRP_SDIO0_1BIT_0_4, |
| PINCTRL_GRP_SDIO0_1BIT_0_5, |
| PINCTRL_GRP_SDIO0_1BIT_0_6, |
| PINCTRL_GRP_SDIO0_1BIT_0_7, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_23] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_NAND0_0, |
| PINCTRL_GRP_SDIO0_0_PC, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_CSU0_5, |
| PINCTRL_GRP_GPIO0_23, |
| PINCTRL_GRP_CAN0_5, |
| PINCTRL_GRP_I2C0_5, |
| PINCTRL_GRP_SWDT0_3_RST, |
| PINCTRL_GRP_SPI1_1, |
| PINCTRL_GRP_TTC0_2_WAV, |
| PINCTRL_GRP_UART0_5, |
| PINCTRL_GRP_RESERVED, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_24] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_NAND0_0, |
| PINCTRL_GRP_SDIO0_0_CD, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_CSU0_6, |
| PINCTRL_GRP_GPIO0_24, |
| PINCTRL_GRP_CAN1_6, |
| PINCTRL_GRP_I2C1_6, |
| PINCTRL_GRP_SWDT1_4_CLK, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_TTC3_3_CLK, |
| PINCTRL_GRP_UART1_6, |
| PINCTRL_GRP_RESERVED, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_25] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_NAND0_0, |
| PINCTRL_GRP_SDIO0_0_WP, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_CSU0_7, |
| PINCTRL_GRP_GPIO0_25, |
| PINCTRL_GRP_CAN1_6, |
| PINCTRL_GRP_I2C1_6, |
| PINCTRL_GRP_SWDT1_4_RST, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_TTC3_3_WAV, |
| PINCTRL_GRP_UART1_6, |
| PINCTRL_GRP_RESERVED, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_26] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_GEMTSU0_0, |
| PINCTRL_GRP_NAND0_1_CE, |
| PINCTRL_GRP_PMU0_0, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_CSU0_8, |
| PINCTRL_GRP_GPIO0_26, |
| PINCTRL_GRP_CAN0_6, |
| PINCTRL_GRP_I2C0_6, |
| PINCTRL_GRP_PJTAG0_2, |
| PINCTRL_GRP_SPI0_2, |
| PINCTRL_GRP_TTC2_3_CLK, |
| PINCTRL_GRP_UART0_6, |
| PINCTRL_GRP_TRACE0_1, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_27] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET0_0, |
| PINCTRL_GRP_NAND0_1_RB, |
| PINCTRL_GRP_PMU0_1, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_DPAUX0_0, |
| PINCTRL_GRP_GPIO0_27, |
| PINCTRL_GRP_CAN0_6, |
| PINCTRL_GRP_I2C0_6, |
| PINCTRL_GRP_PJTAG0_2, |
| PINCTRL_GRP_SPI0_2_SS2, |
| PINCTRL_GRP_TTC2_3_WAV, |
| PINCTRL_GRP_UART0_6, |
| PINCTRL_GRP_TRACE0_1, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_28] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET0_0, |
| PINCTRL_GRP_NAND0_1_RB, |
| PINCTRL_GRP_PMU0_2, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_DPAUX0_0, |
| PINCTRL_GRP_GPIO0_28, |
| PINCTRL_GRP_CAN1_7, |
| PINCTRL_GRP_I2C1_7, |
| PINCTRL_GRP_PJTAG0_2, |
| PINCTRL_GRP_SPI0_2_SS1, |
| PINCTRL_GRP_TTC1_3_CLK, |
| PINCTRL_GRP_UART1_7, |
| PINCTRL_GRP_TRACE0_1, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_29] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET0_0, |
| PINCTRL_GRP_PCIE0_0, |
| PINCTRL_GRP_PMU0_3, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_DPAUX0_1, |
| PINCTRL_GRP_GPIO0_29, |
| PINCTRL_GRP_CAN1_7, |
| PINCTRL_GRP_I2C1_7, |
| PINCTRL_GRP_PJTAG0_2, |
| PINCTRL_GRP_SPI0_2_SS0, |
| PINCTRL_GRP_TTC1_3_WAV, |
| PINCTRL_GRP_UART1_7, |
| PINCTRL_GRP_TRACE0_1, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_30] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET0_0, |
| PINCTRL_GRP_PCIE0_1, |
| PINCTRL_GRP_PMU0_4, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_DPAUX0_1, |
| PINCTRL_GRP_GPIO0_30, |
| PINCTRL_GRP_CAN0_7, |
| PINCTRL_GRP_I2C0_7, |
| PINCTRL_GRP_SWDT0_4_CLK, |
| PINCTRL_GRP_SPI0_2, |
| PINCTRL_GRP_TTC0_3_CLK, |
| PINCTRL_GRP_UART0_7, |
| PINCTRL_GRP_TRACE0_1, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_31] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET0_0, |
| PINCTRL_GRP_PCIE0_2, |
| PINCTRL_GRP_PMU0_5, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_CSU0_9, |
| PINCTRL_GRP_GPIO0_31, |
| PINCTRL_GRP_CAN0_7, |
| PINCTRL_GRP_I2C0_7, |
| PINCTRL_GRP_SWDT0_4_RST, |
| PINCTRL_GRP_SPI0_2, |
| PINCTRL_GRP_TTC0_3_WAV, |
| PINCTRL_GRP_UART0_7, |
| PINCTRL_GRP_TRACE0_1, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_32] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET0_0, |
| PINCTRL_GRP_NAND0_1_DQS, |
| PINCTRL_GRP_PMU0_6, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_CSU0_10, |
| PINCTRL_GRP_GPIO0_32, |
| PINCTRL_GRP_CAN1_8, |
| PINCTRL_GRP_I2C1_8, |
| PINCTRL_GRP_SWDT1_5_CLK, |
| PINCTRL_GRP_SPI1_2, |
| PINCTRL_GRP_TTC3_4_CLK, |
| PINCTRL_GRP_UART1_8, |
| PINCTRL_GRP_TRACE0_1, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_33] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET0_0, |
| PINCTRL_GRP_PCIE0_3, |
| PINCTRL_GRP_PMU0_7, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_CSU0_11, |
| PINCTRL_GRP_GPIO0_33, |
| PINCTRL_GRP_CAN1_8, |
| PINCTRL_GRP_I2C1_8, |
| PINCTRL_GRP_SWDT1_5_RST, |
| PINCTRL_GRP_SPI1_2_SS2, |
| PINCTRL_GRP_TTC3_4_WAV, |
| PINCTRL_GRP_UART1_8, |
| PINCTRL_GRP_TRACE0_1, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_34] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET0_0, |
| PINCTRL_GRP_PCIE0_4, |
| PINCTRL_GRP_PMU0_8, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_DPAUX0_2, |
| PINCTRL_GRP_GPIO0_34, |
| PINCTRL_GRP_CAN0_8, |
| PINCTRL_GRP_I2C0_8, |
| PINCTRL_GRP_SWDT0_5_CLK, |
| PINCTRL_GRP_SPI1_2_SS1, |
| PINCTRL_GRP_TTC2_4_CLK, |
| PINCTRL_GRP_UART0_8, |
| PINCTRL_GRP_TRACE0_1, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_35] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET0_0, |
| PINCTRL_GRP_PCIE0_5, |
| PINCTRL_GRP_PMU0_9, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_DPAUX0_2, |
| PINCTRL_GRP_GPIO0_35, |
| PINCTRL_GRP_CAN0_8, |
| PINCTRL_GRP_I2C0_8, |
| PINCTRL_GRP_SWDT0_5_RST, |
| PINCTRL_GRP_SPI1_2_SS0, |
| PINCTRL_GRP_TTC2_4_WAV, |
| PINCTRL_GRP_UART0_8, |
| PINCTRL_GRP_TRACE0_1, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_36] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET0_0, |
| PINCTRL_GRP_PCIE0_6, |
| PINCTRL_GRP_PMU0_10, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_DPAUX0_3, |
| PINCTRL_GRP_GPIO0_36, |
| PINCTRL_GRP_CAN1_9, |
| PINCTRL_GRP_I2C1_9, |
| PINCTRL_GRP_SWDT1_6_CLK, |
| PINCTRL_GRP_SPI1_2, |
| PINCTRL_GRP_TTC1_4_CLK, |
| PINCTRL_GRP_UART1_9, |
| PINCTRL_GRP_TRACE0_1, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_37] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET0_0, |
| PINCTRL_GRP_PCIE0_7, |
| PINCTRL_GRP_PMU0_11, |
| PINCTRL_GRP_TESTSCAN0_0, |
| PINCTRL_GRP_DPAUX0_3, |
| PINCTRL_GRP_GPIO0_37, |
| PINCTRL_GRP_CAN1_9, |
| PINCTRL_GRP_I2C1_9, |
| PINCTRL_GRP_SWDT1_6_RST, |
| PINCTRL_GRP_SPI1_2, |
| PINCTRL_GRP_TTC1_4_WAV, |
| PINCTRL_GRP_UART1_9, |
| PINCTRL_GRP_TRACE0_1, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_38] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_1, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_38, |
| PINCTRL_GRP_CAN0_9, |
| PINCTRL_GRP_I2C0_9, |
| PINCTRL_GRP_PJTAG0_3, |
| PINCTRL_GRP_SPI0_3, |
| PINCTRL_GRP_TTC0_4_CLK, |
| PINCTRL_GRP_UART0_9, |
| PINCTRL_GRP_TRACE0_1_CLK, |
| PINCTRL_GRP_SDIO0_4BIT_1_0, |
| PINCTRL_GRP_SDIO0_4BIT_1_1, |
| PINCTRL_GRP_SDIO0_1BIT_1_0, |
| PINCTRL_GRP_SDIO0_1BIT_1_1, |
| PINCTRL_GRP_SDIO0_1BIT_1_2, |
| PINCTRL_GRP_SDIO0_1BIT_1_3, |
| PINCTRL_GRP_SDIO0_1BIT_1_4, |
| PINCTRL_GRP_SDIO0_1BIT_1_5, |
| PINCTRL_GRP_SDIO0_1BIT_1_6, |
| PINCTRL_GRP_SDIO0_1BIT_1_7, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_39] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_1_CD, |
| PINCTRL_GRP_SDIO1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_39, |
| PINCTRL_GRP_CAN0_9, |
| PINCTRL_GRP_I2C0_9, |
| PINCTRL_GRP_PJTAG0_3, |
| PINCTRL_GRP_SPI0_3_SS2, |
| PINCTRL_GRP_TTC0_4_WAV, |
| PINCTRL_GRP_UART0_9, |
| PINCTRL_GRP_TRACE0_1_CLK, |
| PINCTRL_GRP_SDIO1_4BIT_0_0, |
| PINCTRL_GRP_SDIO1_1BIT_0_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_40] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_1, |
| PINCTRL_GRP_SDIO1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_40, |
| PINCTRL_GRP_CAN1_10, |
| PINCTRL_GRP_I2C1_10, |
| PINCTRL_GRP_PJTAG0_3, |
| PINCTRL_GRP_SPI0_3_SS1, |
| PINCTRL_GRP_TTC3_5_CLK, |
| PINCTRL_GRP_UART1_10, |
| PINCTRL_GRP_TRACE0_1, |
| PINCTRL_GRP_SDIO0_4BIT_1_0, |
| PINCTRL_GRP_SDIO0_4BIT_1_1, |
| PINCTRL_GRP_SDIO0_1BIT_1_0, |
| PINCTRL_GRP_SDIO0_1BIT_1_1, |
| PINCTRL_GRP_SDIO0_1BIT_1_2, |
| PINCTRL_GRP_SDIO0_1BIT_1_3, |
| PINCTRL_GRP_SDIO0_1BIT_1_4, |
| PINCTRL_GRP_SDIO0_1BIT_1_5, |
| PINCTRL_GRP_SDIO0_1BIT_1_6, |
| PINCTRL_GRP_SDIO0_1BIT_1_7, |
| PINCTRL_GRP_SDIO1_4BIT_0_0, |
| PINCTRL_GRP_SDIO1_1BIT_0_1, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_41] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_1, |
| PINCTRL_GRP_SDIO1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_41, |
| PINCTRL_GRP_CAN1_10, |
| PINCTRL_GRP_I2C1_10, |
| PINCTRL_GRP_PJTAG0_3, |
| PINCTRL_GRP_SPI0_3_SS0, |
| PINCTRL_GRP_TTC3_5_WAV, |
| PINCTRL_GRP_UART1_10, |
| PINCTRL_GRP_TRACE0_1, |
| PINCTRL_GRP_SDIO0_4BIT_1_0, |
| PINCTRL_GRP_SDIO0_1BIT_1_0, |
| PINCTRL_GRP_SDIO1_4BIT_0_0, |
| PINCTRL_GRP_SDIO1_1BIT_0_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_42] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_1, |
| PINCTRL_GRP_SDIO1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_42, |
| PINCTRL_GRP_CAN0_10, |
| PINCTRL_GRP_I2C0_10, |
| PINCTRL_GRP_SWDT0_6_CLK, |
| PINCTRL_GRP_SPI0_3, |
| PINCTRL_GRP_TTC2_5_CLK, |
| PINCTRL_GRP_UART0_10, |
| PINCTRL_GRP_TRACE0_1, |
| PINCTRL_GRP_SDIO0_1, |
| PINCTRL_GRP_SDIO0_4BIT_1_0, |
| PINCTRL_GRP_SDIO0_1BIT_1_1, |
| PINCTRL_GRP_SDIO1_4BIT_0_0, |
| PINCTRL_GRP_SDIO1_1BIT_0_3, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_43] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_1, |
| PINCTRL_GRP_SDIO1_0_PC, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_43, |
| PINCTRL_GRP_CAN0_10, |
| PINCTRL_GRP_I2C0_10, |
| PINCTRL_GRP_SWDT0_6_RST, |
| PINCTRL_GRP_SPI0_3, |
| PINCTRL_GRP_TTC2_5_WAV, |
| PINCTRL_GRP_UART0_10, |
| PINCTRL_GRP_TRACE0_1, |
| PINCTRL_GRP_SDIO0_4BIT_1_0, |
| PINCTRL_GRP_SDIO0_1BIT_1_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_44] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_1, |
| PINCTRL_GRP_SDIO1_0_WP, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_44, |
| PINCTRL_GRP_CAN1_11, |
| PINCTRL_GRP_I2C1_11, |
| PINCTRL_GRP_SWDT1_7_CLK, |
| PINCTRL_GRP_SPI1_3, |
| PINCTRL_GRP_TTC1_5_CLK, |
| PINCTRL_GRP_UART1_11, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_4BIT_1_0, |
| PINCTRL_GRP_SDIO0_1BIT_1_3, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_45] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_1, |
| PINCTRL_GRP_SDIO1_0_CD, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_45, |
| PINCTRL_GRP_CAN1_11, |
| PINCTRL_GRP_I2C1_11, |
| PINCTRL_GRP_SWDT1_7_RST, |
| PINCTRL_GRP_SPI1_3_SS2, |
| PINCTRL_GRP_TTC1_5_WAV, |
| PINCTRL_GRP_UART1_11, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_4BIT_1_1, |
| PINCTRL_GRP_SDIO0_1BIT_1_4, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_46] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_1, |
| PINCTRL_GRP_SDIO1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_46, |
| PINCTRL_GRP_CAN0_11, |
| PINCTRL_GRP_I2C0_11, |
| PINCTRL_GRP_SWDT0_7_CLK, |
| PINCTRL_GRP_SPI1_3_SS1, |
| PINCTRL_GRP_TTC0_5_CLK, |
| PINCTRL_GRP_UART0_11, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_4BIT_1_1, |
| PINCTRL_GRP_SDIO0_1BIT_1_5, |
| PINCTRL_GRP_SDIO1_4BIT_0_1, |
| PINCTRL_GRP_SDIO1_1BIT_0_4, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_47] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_1, |
| PINCTRL_GRP_SDIO1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_47, |
| PINCTRL_GRP_CAN0_11, |
| PINCTRL_GRP_I2C0_11, |
| PINCTRL_GRP_SWDT0_7_RST, |
| PINCTRL_GRP_SPI1_3_SS0, |
| PINCTRL_GRP_TTC0_5_WAV, |
| PINCTRL_GRP_UART0_11, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_4BIT_1_1, |
| PINCTRL_GRP_SDIO0_1BIT_1_6, |
| PINCTRL_GRP_SDIO1_4BIT_0_1, |
| PINCTRL_GRP_SDIO1_1BIT_0_5, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_48] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_1, |
| PINCTRL_GRP_SDIO1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_48, |
| PINCTRL_GRP_CAN1_12, |
| PINCTRL_GRP_I2C1_12, |
| PINCTRL_GRP_SWDT1_8_CLK, |
| PINCTRL_GRP_SPI1_3, |
| PINCTRL_GRP_TTC3_6_CLK, |
| PINCTRL_GRP_UART1_12, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_4BIT_1_1, |
| PINCTRL_GRP_SDIO0_1BIT_1_7, |
| PINCTRL_GRP_SDIO1_4BIT_0_1, |
| PINCTRL_GRP_SDIO1_1BIT_0_6, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_49] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_1_PC, |
| PINCTRL_GRP_SDIO1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_49, |
| PINCTRL_GRP_CAN1_12, |
| PINCTRL_GRP_I2C1_12, |
| PINCTRL_GRP_SWDT1_8_RST, |
| PINCTRL_GRP_SPI1_3, |
| PINCTRL_GRP_TTC3_6_WAV, |
| PINCTRL_GRP_UART1_12, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO1_4BIT_0_1, |
| PINCTRL_GRP_SDIO1_1BIT_0_7, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_50] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_GEMTSU0_1, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_1_WP, |
| PINCTRL_GRP_SDIO1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_50, |
| PINCTRL_GRP_CAN0_12, |
| PINCTRL_GRP_I2C0_12, |
| PINCTRL_GRP_SWDT0_8_CLK, |
| PINCTRL_GRP_MDIO1_0, |
| PINCTRL_GRP_TTC2_6_CLK, |
| PINCTRL_GRP_UART0_12, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO1_4BIT_0_0, |
| PINCTRL_GRP_SDIO1_4BIT_0_1, |
| PINCTRL_GRP_SDIO1_1BIT_0_0, |
| PINCTRL_GRP_SDIO1_1BIT_0_1, |
| PINCTRL_GRP_SDIO1_1BIT_0_2, |
| PINCTRL_GRP_SDIO1_1BIT_0_3, |
| PINCTRL_GRP_SDIO1_1BIT_0_4, |
| PINCTRL_GRP_SDIO1_1BIT_0_5, |
| PINCTRL_GRP_SDIO1_1BIT_0_6, |
| PINCTRL_GRP_SDIO1_1BIT_0_7, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_51] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_GEMTSU0_2, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_51, |
| PINCTRL_GRP_CAN0_12, |
| PINCTRL_GRP_I2C0_12, |
| PINCTRL_GRP_SWDT0_8_RST, |
| PINCTRL_GRP_MDIO1_0, |
| PINCTRL_GRP_TTC2_6_WAV, |
| PINCTRL_GRP_UART0_12, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO1_4BIT_0_0, |
| PINCTRL_GRP_SDIO1_4BIT_0_1, |
| PINCTRL_GRP_SDIO1_1BIT_0_0, |
| PINCTRL_GRP_SDIO1_1BIT_0_1, |
| PINCTRL_GRP_SDIO1_1BIT_0_2, |
| PINCTRL_GRP_SDIO1_1BIT_0_3, |
| PINCTRL_GRP_SDIO1_1BIT_0_4, |
| PINCTRL_GRP_SDIO1_1BIT_0_5, |
| PINCTRL_GRP_SDIO1_1BIT_0_6, |
| PINCTRL_GRP_SDIO1_1BIT_0_7, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_52] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET2_0, |
| PINCTRL_GRP_USB0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_52, |
| PINCTRL_GRP_CAN1_13, |
| PINCTRL_GRP_I2C1_13, |
| PINCTRL_GRP_PJTAG0_4, |
| PINCTRL_GRP_SPI0_4, |
| PINCTRL_GRP_TTC1_6_CLK, |
| PINCTRL_GRP_UART1_13, |
| PINCTRL_GRP_TRACE0_2_CLK, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_53] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET2_0, |
| PINCTRL_GRP_USB0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_53, |
| PINCTRL_GRP_CAN1_13, |
| PINCTRL_GRP_I2C1_13, |
| PINCTRL_GRP_PJTAG0_4, |
| PINCTRL_GRP_SPI0_4_SS2, |
| PINCTRL_GRP_TTC1_6_WAV, |
| PINCTRL_GRP_UART1_13, |
| PINCTRL_GRP_TRACE0_2_CLK, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_54] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET2_0, |
| PINCTRL_GRP_USB0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_54, |
| PINCTRL_GRP_CAN0_13, |
| PINCTRL_GRP_I2C0_13, |
| PINCTRL_GRP_PJTAG0_4, |
| PINCTRL_GRP_SPI0_4_SS1, |
| PINCTRL_GRP_TTC0_6_CLK, |
| PINCTRL_GRP_UART0_13, |
| PINCTRL_GRP_TRACE0_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_55] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET2_0, |
| PINCTRL_GRP_USB0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_55, |
| PINCTRL_GRP_CAN0_13, |
| PINCTRL_GRP_I2C0_13, |
| PINCTRL_GRP_PJTAG0_4, |
| PINCTRL_GRP_SPI0_4_SS0, |
| PINCTRL_GRP_TTC0_6_WAV, |
| PINCTRL_GRP_UART0_13, |
| PINCTRL_GRP_TRACE0_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_56] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET2_0, |
| PINCTRL_GRP_USB0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_56, |
| PINCTRL_GRP_CAN1_14, |
| PINCTRL_GRP_I2C1_14, |
| PINCTRL_GRP_SWDT1_9_CLK, |
| PINCTRL_GRP_SPI0_4, |
| PINCTRL_GRP_TTC3_7_CLK, |
| PINCTRL_GRP_UART1_14, |
| PINCTRL_GRP_TRACE0_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_57] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET2_0, |
| PINCTRL_GRP_USB0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_57, |
| PINCTRL_GRP_CAN1_14, |
| PINCTRL_GRP_I2C1_14, |
| PINCTRL_GRP_SWDT1_9_RST, |
| PINCTRL_GRP_SPI0_4, |
| PINCTRL_GRP_TTC3_7_WAV, |
| PINCTRL_GRP_UART1_14, |
| PINCTRL_GRP_TRACE0_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_58] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET2_0, |
| PINCTRL_GRP_USB0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_58, |
| PINCTRL_GRP_CAN0_14, |
| PINCTRL_GRP_I2C0_14, |
| PINCTRL_GRP_PJTAG0_5, |
| PINCTRL_GRP_SPI1_4, |
| PINCTRL_GRP_TTC2_7_CLK, |
| PINCTRL_GRP_UART0_14, |
| PINCTRL_GRP_TRACE0_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_59] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET2_0, |
| PINCTRL_GRP_USB0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_59, |
| PINCTRL_GRP_CAN0_14, |
| PINCTRL_GRP_I2C0_14, |
| PINCTRL_GRP_PJTAG0_5, |
| PINCTRL_GRP_SPI1_4_SS2, |
| PINCTRL_GRP_TTC2_7_WAV, |
| PINCTRL_GRP_UART0_14, |
| PINCTRL_GRP_TRACE0_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_60] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET2_0, |
| PINCTRL_GRP_USB0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_60, |
| PINCTRL_GRP_CAN1_15, |
| PINCTRL_GRP_I2C1_15, |
| PINCTRL_GRP_PJTAG0_5, |
| PINCTRL_GRP_SPI1_4_SS1, |
| PINCTRL_GRP_TTC1_7_CLK, |
| PINCTRL_GRP_UART1_15, |
| PINCTRL_GRP_TRACE0_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_61] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET2_0, |
| PINCTRL_GRP_USB0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_61, |
| PINCTRL_GRP_CAN1_15, |
| PINCTRL_GRP_I2C1_15, |
| PINCTRL_GRP_PJTAG0_5, |
| PINCTRL_GRP_SPI1_4_SS0, |
| PINCTRL_GRP_TTC1_7_WAV, |
| PINCTRL_GRP_UART1_15, |
| PINCTRL_GRP_TRACE0_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_62] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET2_0, |
| PINCTRL_GRP_USB0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_62, |
| PINCTRL_GRP_CAN0_15, |
| PINCTRL_GRP_I2C0_15, |
| PINCTRL_GRP_SWDT0_9_CLK, |
| PINCTRL_GRP_SPI1_4, |
| PINCTRL_GRP_TTC0_7_CLK, |
| PINCTRL_GRP_UART0_15, |
| PINCTRL_GRP_TRACE0_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_63] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET2_0, |
| PINCTRL_GRP_USB0_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_63, |
| PINCTRL_GRP_CAN0_15, |
| PINCTRL_GRP_I2C0_15, |
| PINCTRL_GRP_SWDT0_9_RST, |
| PINCTRL_GRP_SPI1_4, |
| PINCTRL_GRP_TTC0_7_WAV, |
| PINCTRL_GRP_UART0_15, |
| PINCTRL_GRP_TRACE0_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_64] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET3_0, |
| PINCTRL_GRP_USB1_0, |
| PINCTRL_GRP_SDIO0_2, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_64, |
| PINCTRL_GRP_CAN1_16, |
| PINCTRL_GRP_I2C1_16, |
| PINCTRL_GRP_SWDT1_10_CLK, |
| PINCTRL_GRP_SPI0_5, |
| PINCTRL_GRP_TTC3_8_CLK, |
| PINCTRL_GRP_UART1_16, |
| PINCTRL_GRP_TRACE0_2, |
| PINCTRL_GRP_SDIO0_4BIT_2_0, |
| PINCTRL_GRP_SDIO0_4BIT_2_1, |
| PINCTRL_GRP_SDIO0_1BIT_2_0, |
| PINCTRL_GRP_SDIO0_1BIT_2_1, |
| PINCTRL_GRP_SDIO0_1BIT_2_2, |
| PINCTRL_GRP_SDIO0_1BIT_2_3, |
| PINCTRL_GRP_SDIO0_1BIT_2_4, |
| PINCTRL_GRP_SDIO0_1BIT_2_5, |
| PINCTRL_GRP_SDIO0_1BIT_2_6, |
| PINCTRL_GRP_SDIO0_1BIT_2_7, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_65] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET3_0, |
| PINCTRL_GRP_USB1_0, |
| PINCTRL_GRP_SDIO0_2_CD, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_65, |
| PINCTRL_GRP_CAN1_16, |
| PINCTRL_GRP_I2C1_16, |
| PINCTRL_GRP_SWDT1_10_RST, |
| PINCTRL_GRP_SPI0_5_SS2, |
| PINCTRL_GRP_TTC3_8_WAV, |
| PINCTRL_GRP_UART1_16, |
| PINCTRL_GRP_TRACE0_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_66] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET3_0, |
| PINCTRL_GRP_USB1_0, |
| PINCTRL_GRP_SDIO0_2, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_66, |
| PINCTRL_GRP_CAN0_16, |
| PINCTRL_GRP_I2C0_16, |
| PINCTRL_GRP_SWDT0_10_CLK, |
| PINCTRL_GRP_SPI0_5_SS1, |
| PINCTRL_GRP_TTC2_8_CLK, |
| PINCTRL_GRP_UART0_16, |
| PINCTRL_GRP_TRACE0_2, |
| PINCTRL_GRP_SDIO0_4BIT_2_0, |
| PINCTRL_GRP_SDIO0_4BIT_2_1, |
| PINCTRL_GRP_SDIO0_1BIT_2_0, |
| PINCTRL_GRP_SDIO0_1BIT_2_1, |
| PINCTRL_GRP_SDIO0_1BIT_2_2, |
| PINCTRL_GRP_SDIO0_1BIT_2_3, |
| PINCTRL_GRP_SDIO0_1BIT_2_4, |
| PINCTRL_GRP_SDIO0_1BIT_2_5, |
| PINCTRL_GRP_SDIO0_1BIT_2_6, |
| PINCTRL_GRP_SDIO0_1BIT_2_7, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_67] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET3_0, |
| PINCTRL_GRP_USB1_0, |
| PINCTRL_GRP_SDIO0_2, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_67, |
| PINCTRL_GRP_CAN0_16, |
| PINCTRL_GRP_I2C0_16, |
| PINCTRL_GRP_SWDT0_10_RST, |
| PINCTRL_GRP_SPI0_5_SS0, |
| PINCTRL_GRP_TTC2_8_WAV, |
| PINCTRL_GRP_UART0_16, |
| PINCTRL_GRP_TRACE0_2, |
| PINCTRL_GRP_SDIO0_4BIT_2_0, |
| PINCTRL_GRP_SDIO0_1BIT_2_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_68] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET3_0, |
| PINCTRL_GRP_USB1_0, |
| PINCTRL_GRP_SDIO0_2, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_68, |
| PINCTRL_GRP_CAN1_17, |
| PINCTRL_GRP_I2C1_17, |
| PINCTRL_GRP_SWDT1_11_CLK, |
| PINCTRL_GRP_SPI0_5, |
| PINCTRL_GRP_TTC1_8_CLK, |
| PINCTRL_GRP_UART1_17, |
| PINCTRL_GRP_TRACE0_2, |
| PINCTRL_GRP_SDIO0_4BIT_2_0, |
| PINCTRL_GRP_SDIO0_1BIT_2_1, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_69] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET3_0, |
| PINCTRL_GRP_USB1_0, |
| PINCTRL_GRP_SDIO0_2, |
| PINCTRL_GRP_SDIO1_1_WP, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_69, |
| PINCTRL_GRP_CAN1_17, |
| PINCTRL_GRP_I2C1_17, |
| PINCTRL_GRP_SWDT1_11_RST, |
| PINCTRL_GRP_SPI0_5, |
| PINCTRL_GRP_TTC1_8_WAV, |
| PINCTRL_GRP_UART1_17, |
| PINCTRL_GRP_TRACE0_2, |
| PINCTRL_GRP_SDIO0_4BIT_2_0, |
| PINCTRL_GRP_SDIO0_1BIT_2_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_70] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET3_0, |
| PINCTRL_GRP_USB1_0, |
| PINCTRL_GRP_SDIO0_2, |
| PINCTRL_GRP_SDIO1_1_PC, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_70, |
| PINCTRL_GRP_CAN0_17, |
| PINCTRL_GRP_I2C0_17, |
| PINCTRL_GRP_SWDT0_11_CLK, |
| PINCTRL_GRP_SPI1_5, |
| PINCTRL_GRP_TTC0_8_CLK, |
| PINCTRL_GRP_UART0_17, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_4BIT_2_0, |
| PINCTRL_GRP_SDIO0_1BIT_2_3, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_71] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET3_0, |
| PINCTRL_GRP_USB1_0, |
| PINCTRL_GRP_SDIO0_2, |
| PINCTRL_GRP_SDIO1_4BIT_1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_71, |
| PINCTRL_GRP_CAN0_17, |
| PINCTRL_GRP_I2C0_17, |
| PINCTRL_GRP_SWDT0_11_RST, |
| PINCTRL_GRP_SPI1_5_SS2, |
| PINCTRL_GRP_TTC0_8_WAV, |
| PINCTRL_GRP_UART0_17, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_2, |
| PINCTRL_GRP_SDIO0_4BIT_2_1, |
| PINCTRL_GRP_SDIO0_1BIT_2_4, |
| PINCTRL_GRP_SDIO1_1BIT_1_0, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_72] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET3_0, |
| PINCTRL_GRP_USB1_0, |
| PINCTRL_GRP_SDIO0_2, |
| PINCTRL_GRP_SDIO1_4BIT_1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_72, |
| PINCTRL_GRP_CAN1_18, |
| PINCTRL_GRP_I2C1_18, |
| PINCTRL_GRP_SWDT1_12_CLK, |
| PINCTRL_GRP_SPI1_5_SS1, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_UART1_18, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_4BIT_2_1, |
| PINCTRL_GRP_SDIO0_1BIT_2_5, |
| PINCTRL_GRP_SDIO1_1BIT_1_1, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_73] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET3_0, |
| PINCTRL_GRP_USB1_0, |
| PINCTRL_GRP_SDIO0_2, |
| PINCTRL_GRP_SDIO1_4BIT_1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_73, |
| PINCTRL_GRP_CAN1_18, |
| PINCTRL_GRP_I2C1_18, |
| PINCTRL_GRP_SWDT1_12_RST, |
| PINCTRL_GRP_SPI1_5_SS0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_UART1_18, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_4BIT_2_1, |
| PINCTRL_GRP_SDIO0_1BIT_2_6, |
| PINCTRL_GRP_SDIO1_1BIT_1_2, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_74] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET3_0, |
| PINCTRL_GRP_USB1_0, |
| PINCTRL_GRP_SDIO0_2, |
| PINCTRL_GRP_SDIO1_4BIT_1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_74, |
| PINCTRL_GRP_CAN0_18, |
| PINCTRL_GRP_I2C0_18, |
| PINCTRL_GRP_SWDT0_12_CLK, |
| PINCTRL_GRP_SPI1_5, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_UART0_18, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_4BIT_2_1, |
| PINCTRL_GRP_SDIO0_1BIT_2_7, |
| PINCTRL_GRP_SDIO1_1BIT_1_3, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_75] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_ETHERNET3_0, |
| PINCTRL_GRP_USB1_0, |
| PINCTRL_GRP_SDIO0_2_PC, |
| PINCTRL_GRP_SDIO1_4BIT_1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_75, |
| PINCTRL_GRP_CAN0_18, |
| PINCTRL_GRP_I2C0_18, |
| PINCTRL_GRP_SWDT0_12_RST, |
| PINCTRL_GRP_SPI1_5, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_UART0_18, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO1_1BIT_1_0, |
| PINCTRL_GRP_SDIO1_1BIT_1_1, |
| PINCTRL_GRP_SDIO1_1BIT_1_2, |
| PINCTRL_GRP_SDIO1_1BIT_1_3, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_76] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO0_2_WP, |
| PINCTRL_GRP_SDIO1_4BIT_1_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_76, |
| PINCTRL_GRP_CAN1_19, |
| PINCTRL_GRP_I2C1_19, |
| PINCTRL_GRP_MDIO0_0, |
| PINCTRL_GRP_MDIO1_1, |
| PINCTRL_GRP_MDIO2_0, |
| PINCTRL_GRP_MDIO3_0, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO1_1BIT_1_0, |
| PINCTRL_GRP_SDIO1_1BIT_1_1, |
| PINCTRL_GRP_SDIO1_1BIT_1_2, |
| PINCTRL_GRP_SDIO1_1BIT_1_3, |
| END_OF_GROUPS, |
| }), |
| }, |
| [PINCTRL_PIN_77] = { |
| .groups = &((uint16_t []) { |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_SDIO1_1_CD, |
| PINCTRL_GRP_RESERVED, |
| PINCTRL_GRP_GPIO0_77, |
| PINCTRL_GRP_CAN1_19, |
| PINCTRL_GRP_I2C1_19, |
| PINCTRL_GRP_MDIO0_0, |
| PINCTRL_GRP_MDIO1_1, |
| PINCTRL_GRP_MDIO2_0, |
| PINCTRL_GRP_MDIO3_0, |
| PINCTRL_GRP_RESERVED, |
| END_OF_GROUPS, |
| }), |
| }, |
| }; |
| |
| /** |
| * pm_api_pinctrl_get_num_pins() - PM call to request number of pins |
| * @npins Number of pins |
| * |
| * This function is used by master to get number of pins |
| * |
| * @return Returns success. |
| */ |
| enum pm_ret_status pm_api_pinctrl_get_num_pins(unsigned int *npins) |
| { |
| *npins = MAX_PIN; |
| |
| return PM_RET_SUCCESS; |
| } |
| |
| /** |
| * pm_api_pinctrl_get_num_functions() - PM call to request number of functions |
| * @nfuncs Number of functions |
| * |
| * This function is used by master to get number of functions |
| * |
| * @return Returns success. |
| */ |
| enum pm_ret_status pm_api_pinctrl_get_num_functions(unsigned int *nfuncs) |
| { |
| *nfuncs = MAX_FUNCTION; |
| |
| return PM_RET_SUCCESS; |
| } |
| |
| /** |
| * pm_api_pinctrl_get_num_func_groups() - PM call to request number of |
| * function groups |
| * @fid Function Id |
| * @ngroups Number of function groups |
| * |
| * This function is used by master to get number of function groups |
| * |
| * @return Returns success. |
| */ |
| enum pm_ret_status pm_api_pinctrl_get_num_func_groups(unsigned int fid, |
| unsigned int *ngroups) |
| { |
| int i = 0; |
| uint16_t *grps; |
| |
| if (fid >= MAX_FUNCTION) |
| return PM_RET_ERROR_ARGS; |
| |
| *ngroups = 0; |
| |
| grps = *pinctrl_functions[fid].groups; |
| if (grps == NULL) |
| return PM_RET_SUCCESS; |
| |
| while (grps[i++] != (uint16_t)END_OF_GROUPS) |
| (*ngroups)++; |
| |
| return PM_RET_SUCCESS; |
| } |
| |
| /** |
| * pm_api_pinctrl_get_function_name() - PM call to request a function name |
| * @fid Function ID |
| * @name Name of function (max 16 bytes) |
| * |
| * This function is used by master to get name of function specified |
| * by given function ID. |
| * |
| * @return Returns success. In case of error, name data is 0. |
| */ |
| enum pm_ret_status pm_api_pinctrl_get_function_name(unsigned int fid, |
| char *name) |
| { |
| if (fid >= MAX_FUNCTION) |
| memcpy(name, END_OF_FUNCTION, FUNCTION_NAME_LEN); |
| else |
| memcpy(name, pinctrl_functions[fid].name, FUNCTION_NAME_LEN); |
| |
| return PM_RET_SUCCESS; |
| } |
| |
| /** |
| * pm_api_pinctrl_get_function_groups() - PM call to request first 6 function |
| * groups of function Id |
| * @fid Function ID |
| * @index Index of next function groups |
| * @groups Function groups |
| * |
| * This function is used by master to get function groups specified |
| * by given function Id. This API will return 6 function groups with |
| * a single response. To get other function groups, master should call |
| * same API in loop with new function groups index till error is returned. |
| * |
| * E.g First call should have index 0 which will return function groups |
| * 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return |
| * function groups 6, 7, 8, 9, 10 and 11 and so on. |
| * |
| * Return: Returns status, either success or error+reason. |
| */ |
| enum pm_ret_status pm_api_pinctrl_get_function_groups(unsigned int fid, |
| unsigned int index, |
| uint16_t *groups) |
| { |
| unsigned int i; |
| uint16_t *grps; |
| |
| if (fid >= MAX_FUNCTION) |
| return PM_RET_ERROR_ARGS; |
| |
| memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN); |
| |
| grps = *pinctrl_functions[fid].groups; |
| if (grps == NULL) |
| return PM_RET_SUCCESS; |
| |
| /* Skip groups till index */ |
| for (i = 0; i < index; i++) |
| if (grps[i] == (uint16_t)END_OF_GROUPS) |
| return PM_RET_SUCCESS; |
| |
| for (i = 0; i < NUM_GROUPS_PER_RESP; i++) { |
| groups[i] = grps[index + i]; |
| if (groups[i] == (uint16_t)END_OF_GROUPS) |
| break; |
| } |
| |
| return PM_RET_SUCCESS; |
| } |
| |
| /** |
| * pm_api_pinctrl_get_pin_groups() - PM call to request first 6 pin |
| * groups of pin |
| * @pin Pin |
| * @index Index of next pin groups |
| * @groups pin groups |
| * |
| * This function is used by master to get pin groups specified |
| * by given pin Id. This API will return 6 pin groups with |
| * a single response. To get other pin groups, master should call |
| * same API in loop with new pin groups index till error is returned. |
| * |
| * E.g First call should have index 0 which will return pin groups |
| * 0, 1, 2, 3, 4 and 5. Next call, index should be 6 which will return |
| * pin groups 6, 7, 8, 9, 10 and 11 and so on. |
| * |
| * Return: Returns status, either success or error+reason. |
| */ |
| enum pm_ret_status pm_api_pinctrl_get_pin_groups(unsigned int pin, |
| unsigned int index, |
| uint16_t *groups) |
| { |
| unsigned int i; |
| uint16_t *grps; |
| |
| if (pin >= MAX_PIN) |
| return PM_RET_ERROR_ARGS; |
| |
| memset(groups, END_OF_GROUPS, GROUPS_PAYLOAD_LEN); |
| |
| grps = *zynqmp_pin_groups[pin].groups; |
| if (!grps) |
| return PM_RET_SUCCESS; |
| |
| /* Skip groups till index */ |
| for (i = 0; i < index; i++) |
| if (grps[i] == (uint16_t)END_OF_GROUPS) |
| return PM_RET_SUCCESS; |
| |
| for (i = 0; i < NUM_GROUPS_PER_RESP; i++) { |
| groups[i] = grps[index + i]; |
| if (groups[i] == (uint16_t)END_OF_GROUPS) |
| break; |
| } |
| |
| return PM_RET_SUCCESS; |
| } |
| |
| /** |
| * pm_api_pinctrl_get_function() - Read function id set for the given pin |
| * @pin Pin number |
| * @nid Node ID of function currently set for given pin |
| * |
| * This function provides the function currently set for the given pin. |
| * |
| * @return Returns status, either success or error+reason |
| */ |
| enum pm_ret_status pm_api_pinctrl_get_function(unsigned int pin, |
| unsigned int *id) |
| { |
| unsigned int i = 0, j = 0; |
| enum pm_ret_status ret = PM_RET_SUCCESS; |
| unsigned int ctrlreg, val, gid; |
| uint16_t *grps; |
| |
| ctrlreg = IOU_SLCR_BASEADDR + 4U * pin; |
| ret = pm_mmio_read(ctrlreg, &val); |
| if (ret != PM_RET_SUCCESS) |
| return ret; |
| |
| val &= PINCTRL_FUNCTION_MASK; |
| |
| for (i = 0; i < NFUNCS_PER_PIN; i++) |
| if (val == pm_pinctrl_mux[i]) |
| break; |
| |
| if (i == NFUNCS_PER_PIN) |
| return PM_RET_ERROR_NOTSUPPORTED; |
| |
| gid = *(*zynqmp_pin_groups[pin].groups + i); |
| |
| for (i = 0; i < MAX_FUNCTION; i++) { |
| grps = *pinctrl_functions[i].groups; |
| if (grps == NULL) |
| continue; |
| if (val != pinctrl_functions[i].regval) |
| continue; |
| |
| for (j = 0; grps[j] != (uint16_t)END_OF_GROUPS; j++) { |
| if (gid == grps[j]) { |
| *id = i; |
| goto done; |
| } |
| } |
| } |
| if (i == MAX_FUNCTION) |
| ret = PM_RET_ERROR_ARGS; |
| done: |
| return ret; |
| } |
| |
| /** |
| * pm_api_pinctrl_set_function() - Set function id set for the given pin |
| * @pin Pin number |
| * @nid Node ID of function to set for given pin |
| * |
| * This function provides the function currently set for the given pin. |
| * |
| * @return Returns status, either success or error+reason |
| */ |
| enum pm_ret_status pm_api_pinctrl_set_function(unsigned int pin, |
| unsigned int fid) |
| { |
| int i, j; |
| unsigned int ctrlreg, val; |
| uint16_t *pgrps, *fgrps; |
| |
| ctrlreg = IOU_SLCR_BASEADDR + 4U * pin; |
| val = pinctrl_functions[fid].regval; |
| |
| for (i = 0; i < NFUNCS_PER_PIN; i++) |
| if (val == pm_pinctrl_mux[i]) |
| break; |
| |
| if (i == NFUNCS_PER_PIN) |
| return PM_RET_ERROR_NOTSUPPORTED; |
| |
| pgrps = *zynqmp_pin_groups[pin].groups; |
| if (!pgrps) |
| return PM_RET_ERROR_NOTSUPPORTED; |
| |
| fgrps = *pinctrl_functions[fid].groups; |
| if (!fgrps) |
| return PM_RET_ERROR_NOTSUPPORTED; |
| |
| for (i = 0; fgrps[i] != (uint16_t)END_OF_GROUPS; i++) |
| for (j = 0; pgrps[j] != (uint16_t)END_OF_GROUPS; j++) |
| if (fgrps[i] == pgrps[j]) |
| goto match; |
| |
| return PM_RET_ERROR_NOTSUPPORTED; |
| |
| match: |
| return pm_mmio_write(ctrlreg, PINCTRL_FUNCTION_MASK, val); |
| } |
| |
| /** |
| * pm_api_pinctrl_set_config() - Set configuration parameter for given pin |
| * @pin: Pin for which configuration is to be set |
| * @param: Configuration parameter to be set |
| * @value: Value to be set for configuration parameter |
| * |
| * This function sets value of requested configuration parameter for given pin. |
| * |
| * @return Returns status, either success or error+reason |
| */ |
| enum pm_ret_status pm_api_pinctrl_set_config(unsigned int pin, |
| unsigned int param, |
| unsigned int value) |
| { |
| enum pm_ret_status ret; |
| unsigned int ctrlreg, mask, val, offset; |
| |
| if (param >= PINCTRL_CONFIG_MAX) |
| return PM_RET_ERROR_NOTSUPPORTED; |
| |
| if (pin >= PINCTRL_NUM_MIOS) |
| return PM_RET_ERROR_ARGS; |
| |
| mask = 1 << PINCTRL_PIN_OFFSET(pin); |
| |
| switch (param) { |
| case PINCTRL_CONFIG_SLEW_RATE: |
| if (value != PINCTRL_SLEW_RATE_FAST && |
| value != PINCTRL_SLEW_RATE_SLOW) |
| return PM_RET_ERROR_ARGS; |
| |
| ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
| PINCTRL_SLEWCTRL_REG_OFFSET, |
| pin); |
| val = value << PINCTRL_PIN_OFFSET(pin); |
| ret = pm_mmio_write(ctrlreg, mask, val); |
| break; |
| case PINCTRL_CONFIG_BIAS_STATUS: |
| if (value != PINCTRL_BIAS_ENABLE && |
| value != PINCTRL_BIAS_DISABLE) |
| return PM_RET_ERROR_ARGS; |
| |
| ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
| PINCTRL_PULLSTAT_REG_OFFSET, |
| pin); |
| |
| offset = PINCTRL_PIN_OFFSET(pin); |
| if (ctrlreg == IOU_SLCR_BANK1_CTRL5) |
| offset = (offset < 12U) ? |
| (offset + 14U) : (offset - 12U); |
| |
| val = value << offset; |
| mask = 1 << offset; |
| ret = pm_mmio_write(ctrlreg, mask, val); |
| break; |
| case PINCTRL_CONFIG_PULL_CTRL: |
| |
| if (value != PINCTRL_BIAS_PULL_DOWN && |
| value != PINCTRL_BIAS_PULL_UP) |
| return PM_RET_ERROR_ARGS; |
| |
| ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
| PINCTRL_PULLSTAT_REG_OFFSET, |
| pin); |
| |
| offset = PINCTRL_PIN_OFFSET(pin); |
| if (ctrlreg == IOU_SLCR_BANK1_CTRL5) |
| offset = (offset < 12U) ? |
| (offset + 14U) : (offset - 12U); |
| |
| val = PINCTRL_BIAS_ENABLE << offset; |
| ret = pm_mmio_write(ctrlreg, 1 << offset, val); |
| if (ret != PM_RET_SUCCESS) |
| return ret; |
| |
| ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
| PINCTRL_PULLCTRL_REG_OFFSET, |
| pin); |
| val = value << PINCTRL_PIN_OFFSET(pin); |
| ret = pm_mmio_write(ctrlreg, mask, val); |
| break; |
| case PINCTRL_CONFIG_SCHMITT_CMOS: |
| if (value != PINCTRL_INPUT_TYPE_CMOS && |
| value != PINCTRL_INPUT_TYPE_SCHMITT) |
| return PM_RET_ERROR_ARGS; |
| |
| ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
| PINCTRL_SCHCMOS_REG_OFFSET, |
| pin); |
| |
| val = value << PINCTRL_PIN_OFFSET(pin); |
| ret = pm_mmio_write(ctrlreg, mask, val); |
| break; |
| case PINCTRL_CONFIG_DRIVE_STRENGTH: |
| if (value > PINCTRL_DRIVE_STRENGTH_12MA) |
| return PM_RET_ERROR_ARGS; |
| |
| ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
| PINCTRL_DRVSTRN0_REG_OFFSET, |
| pin); |
| val = (value >> 1) << PINCTRL_PIN_OFFSET(pin); |
| ret = pm_mmio_write(ctrlreg, mask, val); |
| if (ret) |
| return ret; |
| |
| ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
| PINCTRL_DRVSTRN1_REG_OFFSET, |
| pin); |
| val = (value & 0x01U) << PINCTRL_PIN_OFFSET(pin); |
| ret = pm_mmio_write(ctrlreg, mask, val); |
| break; |
| default: |
| ERROR("Invalid parameter %u\n", param); |
| ret = PM_RET_ERROR_NOTSUPPORTED; |
| break; |
| } |
| |
| return ret; |
| } |
| |
| /** |
| * pm_api_pinctrl_get_config() - Get configuration parameter value for given pin |
| * @pin: Pin for which configuration is to be read |
| * @param: Configuration parameter to be read |
| * @value: buffer to store value of configuration parameter |
| * |
| * This function reads value of requested configuration parameter for given pin. |
| * |
| * @return Returns status, either success or error+reason |
| */ |
| enum pm_ret_status pm_api_pinctrl_get_config(unsigned int pin, |
| unsigned int param, |
| unsigned int *value) |
| { |
| enum pm_ret_status ret; |
| unsigned int ctrlreg, val; |
| |
| if (param >= PINCTRL_CONFIG_MAX) |
| return PM_RET_ERROR_NOTSUPPORTED; |
| |
| if (pin >= PINCTRL_NUM_MIOS) |
| return PM_RET_ERROR_ARGS; |
| |
| switch (param) { |
| case PINCTRL_CONFIG_SLEW_RATE: |
| ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
| PINCTRL_SLEWCTRL_REG_OFFSET, |
| pin); |
| |
| ret = pm_mmio_read(ctrlreg, &val); |
| if (ret != PM_RET_SUCCESS) |
| return ret; |
| |
| *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); |
| break; |
| case PINCTRL_CONFIG_BIAS_STATUS: |
| ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
| PINCTRL_PULLSTAT_REG_OFFSET, |
| pin); |
| |
| ret = pm_mmio_read(ctrlreg, &val); |
| if (ret) |
| return ret; |
| |
| if (ctrlreg == IOU_SLCR_BANK1_CTRL5) |
| val = ((val & 0x3FFF) << 12) | ((val >> 14) & 0xFFF); |
| |
| *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); |
| break; |
| case PINCTRL_CONFIG_PULL_CTRL: |
| |
| ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
| PINCTRL_PULLCTRL_REG_OFFSET, |
| pin); |
| |
| ret = pm_mmio_read(ctrlreg, &val); |
| if (ret) |
| return ret; |
| |
| *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); |
| break; |
| case PINCTRL_CONFIG_SCHMITT_CMOS: |
| ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
| PINCTRL_SCHCMOS_REG_OFFSET, |
| pin); |
| |
| ret = pm_mmio_read(ctrlreg, &val); |
| if (ret) |
| return ret; |
| |
| *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); |
| break; |
| case PINCTRL_CONFIG_DRIVE_STRENGTH: |
| ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
| PINCTRL_DRVSTRN0_REG_OFFSET, |
| pin); |
| ret = pm_mmio_read(ctrlreg, &val); |
| if (ret) |
| return ret; |
| |
| *value = PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val) << 1; |
| |
| ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
| PINCTRL_DRVSTRN1_REG_OFFSET, |
| pin); |
| ret = pm_mmio_read(ctrlreg, &val); |
| if (ret) |
| return ret; |
| |
| *value |= PINCTRL_REGVAL_TO_PIN_CONFIG(pin, val); |
| break; |
| case PINCTRL_CONFIG_VOLTAGE_STATUS: |
| ctrlreg = PINCTRL_CFG_ADDR_OFFSET(IOU_SLCR_BASEADDR, |
| PINCTRL_VOLTAGE_STAT_REG_OFFSET, |
| pin); |
| |
| ret = pm_mmio_read(ctrlreg, &val); |
| if (ret) |
| return ret; |
| |
| *value = val & PINCTRL_VOLTAGE_STATUS_MASK; |
| break; |
| default: |
| return PM_RET_ERROR_NOTSUPPORTED; |
| } |
| |
| return PM_RET_SUCCESS; |
| } |
