fdts/fvp-foundation-motherboard.dtsi

/*
 * Copyright (c) 2013-2018, ARM Limited and Contributors. All rights reserved.
 *
 * SPDX-License-Identifier: BSD-3-Clause
 */

	motherboard {
		arm,v2m-memory-map = "rs1";
		compatible = "arm,vexpress,v2m-p1", "simple-bus";
		#address-cells = <2>; /* SMB chipselect number and offset */
		#size-cells = <1>;
		ranges;

		ethernet@2,02000000 {
			compatible = "smsc,lan91c111";
			reg = <2 0x02000000 0x10000>;
			interrupts = <0 15 4>;
		};

		v2m_clk24mhz: clk24mhz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <24000000>;
			clock-output-names = "v2m:clk24mhz";
		};

		v2m_refclk1mhz: refclk1mhz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <1000000>;
			clock-output-names = "v2m:refclk1mhz";
		};

		v2m_refclk32khz: refclk32khz {
			compatible = "fixed-clock";
			#clock-cells = <0>;
			clock-frequency = <32768>;
			clock-output-names = "v2m:refclk32khz";
		};

		iofpga@3,00000000 {
			compatible = "arm,amba-bus", "simple-bus";
			#address-cells = <1>;
			#size-cells = <1>;
			ranges = <0 3 0 0x200000>;

			v2m_sysreg: sysreg@10000 {
				compatible = "arm,vexpress-sysreg";
				reg = <0x010000 0x1000>;
				gpio-controller;
				#gpio-cells = <2>;
			};

			v2m_sysctl: sysctl@20000 {
				compatible = "arm,sp810", "arm,primecell";
				reg = <0x020000 0x1000>;
				clocks = <&v2m_refclk32khz>, <&v2m_refclk1mhz>, <&v2m_clk24mhz>;
				clock-names = "refclk", "timclk", "apb_pclk";
				#clock-cells = <1>;
				clock-output-names = "timerclken0", "timerclken1", "timerclken2", "timerclken3";
			};

			v2m_serial0: uart@90000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x090000 0x1000>;
				interrupts = <0 5 4>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial1: uart@a0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0a0000 0x1000>;
				interrupts = <0 6 4>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial2: uart@b0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0b0000 0x1000>;
				interrupts = <0 7 4>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "uartclk", "apb_pclk";
			};

			v2m_serial3: uart@c0000 {
				compatible = "arm,pl011", "arm,primecell";
				reg = <0x0c0000 0x1000>;
				interrupts = <0 8 4>;
				clocks = <&v2m_clk24mhz>, <&v2m_clk24mhz>;
				clock-names = "uartclk", "apb_pclk";
			};

			wdt@f0000 {
				compatible = "arm,sp805", "arm,primecell";
				reg = <0x0f0000 0x1000>;
				interrupts = <0 0 4>;
				clocks = <&v2m_refclk32khz>, <&v2m_clk24mhz>;
				clock-names = "wdogclk", "apb_pclk";
			};

			v2m_timer01: timer@110000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x110000 0x1000>;
				interrupts = <0 2 4>;
				clocks = <&v2m_sysctl 0>, <&v2m_sysctl 1>, <&v2m_clk24mhz>;
				clock-names = "timclken1", "timclken2", "apb_pclk";
			};

			v2m_timer23: timer@120000 {
				compatible = "arm,sp804", "arm,primecell";
				reg = <0x120000 0x1000>;
				interrupts = <0 3 4>;
				clocks = <&v2m_sysctl 2>, <&v2m_sysctl 3>, <&v2m_clk24mhz>;
				clock-names = "timclken1", "timclken2", "apb_pclk";
			};

			rtc@170000 {
				compatible = "arm,pl031", "arm,primecell";
				reg = <0x170000 0x1000>;
				interrupts = <0 4 4>;
				clocks = <&v2m_clk24mhz>;
				clock-names = "apb_pclk";
			};

			virtio_block@130000 {
				compatible = "virtio,mmio";
				reg = <0x130000 0x1000>;
				interrupts = <0 0x2a 4>;
			};
		};

		v2m_fixed_3v3: fixedregulator@0 {
			compatible = "regulator-fixed";
			regulator-name = "3V3";
			regulator-min-microvolt = <3300000>;
			regulator-max-microvolt = <3300000>;
			regulator-always-on;
		};


		mcc {
			compatible = "arm,vexpress,config-bus", "simple-bus";
			arm,vexpress,config-bridge = <&v2m_sysreg>;

			/*
			 * Not supported in FVP models
			 *
			 * reset@0 {
			 * 	compatible = "arm,vexpress-reset";
			 * 	arm,vexpress-sysreg,func = <5 0>;
			 * };
			 */

			muxfpga@0 {
				compatible = "arm,vexpress-muxfpga";
				arm,vexpress-sysreg,func = <7 0>;
			};

			/*
			 * Not used - Superseded by PSCI sys_poweroff
			 *
			 * shutdown@0 {
			 * 	compatible = "arm,vexpress-shutdown";
			 * 	arm,vexpress-sysreg,func = <8 0>;
			 * };
			 */

			/*
			 * Not used - Superseded by PSCI sys_reset
			 *
			 * reboot@0 {
			 * 	compatible = "arm,vexpress-reboot";
			 * 	arm,vexpress-sysreg,func = <9 0>;
			 * };
			 */

			dvimode@0 {
				compatible = "arm,vexpress-dvimode";
				arm,vexpress-sysreg,func = <11 0>;
			};
		};
	};