| /* |
| * Copyright 2017 NXP |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| |
| #include <debug.h> |
| #include <stdlib.h> |
| #include <stdint.h> |
| #include <smcc_helpers.h> |
| #include <std_svc.h> |
| #include <types.h> |
| #include <platform_def.h> |
| #include <fsl_sip.h> |
| #include <sci/sci.h> |
| |
| extern sc_ipc_t ipc_handle; |
| |
| #ifdef PLAT_IMX8QM |
| const static int ap_cluster_index[2] = { |
| SC_R_A53, SC_R_A72, |
| }; |
| #endif |
| |
| static void imx_cpufreq_set_target(uint32_t cluster_id, unsigned long freq) |
| { |
| sc_pm_clock_rate_t rate = (sc_pm_clock_rate_t)freq; |
| |
| #ifdef PLAT_IMX8QM |
| sc_pm_set_clock_rate(ipc_handle, ap_cluster_index[cluster_id], SC_PM_CLK_CPU, &rate); |
| #endif |
| #ifdef PLAT_IMX8QXP |
| sc_pm_set_clock_rate(ipc_handle, SC_R_A35, SC_PM_CLK_CPU, &rate); |
| #endif |
| } |
| |
| int imx_cpufreq_handler(uint32_t smc_fid, |
| u_register_t x1, |
| u_register_t x2, |
| u_register_t x3) |
| { |
| switch(x1) { |
| case FSL_SIP_SET_CPUFREQ: |
| imx_cpufreq_set_target(x2, x3); |
| break; |
| default: |
| return SMC_UNK; |
| } |
| |
| return 0; |
| } |