| /* |
| * Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved. |
| * |
| * SPDX-License-Identifier: BSD-3-Clause |
| */ |
| |
| #include <asm_macros.S> |
| #include <platform_def.h> |
| #include <cortex_a35.h> |
| |
| .globl plat_is_my_cpu_primary |
| .globl plat_my_core_pos |
| .globl plat_calc_core_pos |
| .globl plat_reset_handler |
| .globl plat_get_my_entrypoint |
| .globl plat_secondary_cold_boot_setup |
| .globl plat_crash_console_init |
| .globl plat_crash_console_putc |
| .globl platform_mem_init |
| .globl imx_mailbox_init |
| |
| /* -------------------------------------------------------------------- |
| * Helper macro that reads the part number of the current CPU and jumps |
| * to the given label if it matches the CPU MIDR provided. |
| * |
| * Clobbers x0. |
| * -------------------------------------------------------------------- |
| */ |
| .macro jump_if_cpu_midr _cpu_midr, _label |
| |
| mrs x0, midr_el1 |
| ubfx x0, x0, MIDR_PN_SHIFT, #12 |
| cmp w0, #((\_cpu_midr >> MIDR_PN_SHIFT) & MIDR_PN_MASK) |
| b.eq \_label |
| |
| .endm |
| |
| /* ---------------------------------------------- |
| * The mailbox_base is used to distinguish warm/cold |
| * reset. The mailbox_base is in the data section, not |
| * in .bss, this allows function to start using this |
| * variable before the runtime memory is initialized. |
| * ---------------------------------------------- |
| */ |
| .section .data.mailbox_base |
| .align 3 |
| mailbox_base: .quad 0x0 |
| |
| /* ---------------------------------------------- |
| * unsigned int plat_is_my_cpu_primary(void); |
| * This function checks if this is the primary CPU |
| * ---------------------------------------------- |
| */ |
| func plat_is_my_cpu_primary |
| mrs x0, mpidr_el1 |
| and x0, x0, #(MPIDR_CPU_MASK) |
| cmp x0, #PLAT_PRIMARY_CPU |
| cset x0, eq |
| ret |
| endfunc plat_is_my_cpu_primary |
| |
| /* ---------------------------------------------- |
| * unsigned int plat_my_core_pos(void) |
| * This Function uses the plat_calc_core_pos() |
| * to get the index of the calling CPU. |
| * ---------------------------------------------- |
| */ |
| func plat_my_core_pos |
| mrs x0, mpidr_el1 |
| and x1, x0, #MPIDR_CPU_MASK |
| and x0, x0, #MPIDR_CLUSTER_MASK |
| add x0, x1, x0, LSR #6 |
| ret |
| endfunc plat_my_core_pos |
| |
| /* |
| * unsigned int plat_calc_core_pos(uint64_t mpidr) |
| * helper function to calculate the core position. |
| * With this function. |
| */ |
| func plat_calc_core_pos |
| and x1, x0, #MPIDR_CPU_MASK |
| and x0, x0, #MPIDR_CLUSTER_MASK |
| add x0, x1, x0, LSR #6 |
| ret |
| endfunc plat_calc_core_pos |
| |
| /* --------------------------------------------- |
| * function to get the entrypoint. |
| * --------------------------------------------- |
| */ |
| func plat_get_my_entrypoint |
| |
| #if defined(PLAT_IMX8QX) || defined(PLAT_IMX8QM) |
| /* --------------------------------------------- |
| * SCU will signal through a GIR bit when a |
| * partition boot has taken place which requires |
| * cold boot setup to take place once again |
| * --------------------------------------------- |
| */ |
| |
| mov x0, #PLAT_BOOT_MU_BASE |
| add x0, x0, #PLAT_MU_SR_OFF |
| ldr w1, [x0] |
| and w1, w1, #PLAT_MU_COLD_BOOT_FLG_MSK |
| cbz w1, warm_boot |
| str w1, [x0] |
| mov x0, #0 |
| ret |
| warm_boot: |
| #endif |
| adrp x1, mailbox_base |
| ldr x0, [x1, :lo12:mailbox_base] |
| ret |
| endfunc plat_get_my_entrypoint |
| |
| func imx_mailbox_init |
| adrp x1, mailbox_base |
| str x0, [x1, :lo12:mailbox_base] |
| ret |
| endfunc imx_mailbox_init |
| |
| func plat_secondary_cold_boot_setup |
| b . |
| endfunc plat_secondary_cold_boot_setup |
| |
| func plat_crash_console_init |
| ret |
| endfunc plat_crash_console_init |
| |
| func plat_crash_console_putc |
| ret |
| endfunc plat_crash_console_putc |
| |
| func platform_mem_init |
| ret |
| endfunc platform_mem_init |
