plat: imx8mm: enable PU domains' clocks before power up
VPU, GPU and PCIE's clock need to be on before power on
these power domains.
Signed-off-by: Bai Ping <ping.bai@nxp.com>
(cherry picked from commit ee094d86280c0e3d899d973db24b4b9b563944da)
diff --git a/plat/imx/imx8mm/gpc.c b/plat/imx/imx8mm/gpc.c
index 0517e14..2cec438 100644
--- a/plat/imx/imx8mm/gpc.c
+++ b/plat/imx/imx8mm/gpc.c
@@ -635,8 +635,17 @@
/* TODO release dispmix sft reset */
/* enable all the PU for bringup up purpose */
- mmio_write_32(IMX_GPC_BASE + 0xf8, 0x3fcf);
+ mmio_write_32(0x30384450, 0x3);
+ mmio_write_32(0x303844d0, 0x3);
+ mmio_write_32(0x303844f0, 0x3);
+ mmio_write_32(0x30384560, 0x3);
+ mmio_write_32(0x30384570, 0x3);
+ mmio_write_32(0x30384590, 0x3);
+ mmio_write_32(0x303845a0, 0x3);
mmio_write_32(0x303845d0, 0x3);
+ mmio_write_32(0x30384630, 0x3);
+ mmio_write_32(0x30384660, 0x3);
+ mmio_write_32(IMX_GPC_BASE + 0xf8, 0x3fcf);
mmio_write_32(0x32e28000, 0x7f);
mmio_write_32(0x32e28004, 0x1fff);
mmio_write_32(0x32e28008, 0x30000);
