MLK-22207 plat: imx8m: Fix the data sync issue in dram dvfs flow
Explict memory barrier(DSB) is necessary to make sure
other cores observe the correct flags updated by the primary
core before the primary begins doing DRAM DVFS.
Signed-off-by: Jacky Bai <ping.bai@nxp.com>
(cherry picked from commit dac8d677447c153cd148fee9e35445c24162f190)
diff --git a/plat/imx/common/imx8m/dram.c b/plat/imx/common/imx8m/dram.c
index b8245db..109569e 100644
--- a/plat/imx/common/imx8m/dram.c
+++ b/plat/imx/common/imx8m/dram.c
@@ -228,6 +228,7 @@
/* set the WFE done status */
spin_lock(&dfs_lock);
wfe_done |= (1 << cpu_id * 8);
+ dsb();
spin_unlock(&dfs_lock);
while (1) {
@@ -239,6 +240,7 @@
}
} else {
wait_ddrc_hwffc_done = true;
+ dsb();
/* trigger the IRQ */
for (int i = 0; i < 4; i++) {
int irq = irqs_used[i] % 32;
